Please do not share these notes on apps like WhatsApp or Telegram.

The revenue we generate from the ads we show on our website and app
funds our services. The generated revenue helps us prepare new notes
and improve the quality of existing study materials, which are
available on our website and mobile app.

If you don't use our website and app directly, it will hurt our revenue,
and we might not be able to run the services and have to close them.
So, it is a humble request for all to stop sharing the study material we
provide on various apps. Please share the website's URL instead.
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)

As shown in the block diagram, the subroutine READIN reads the SPICE input file. ERRCHK verifies that the input syntax
is correct. Temperature effects are handled in SPICE by repeating the entire analysis for each temperature. The
subroutines DCTRAN, DCOP, and CAN perform the bulk of the manipulations. DCTRAN, DCOP are used for DC transfer
characteristics, DC operating point calculations, and transient analysis, CAN perform the small signal AC analysis.
SPICE is the inclusion of respectable models for the basic devices, specially, the diode, BJT, JFET and MOSFET. The user
can create generic models for the active devices that correspond to, and are consistent with, the process parameters
and design rules of the process used for specific design. SPICE version has different MOSFET models designated as
levels. Device models used by SPICE (Simulation Program for Integrated Circuit Engineering) simulators can be divided
into three classes:
1. First Generation Models (Level 1, Level 2, Level 3 models)
2. Second Generation Models (BISM, BSIM2, HSPICE Level 28)
3. Third Generation Models (Level 7, Level 48, BSIM3, etc.)
To run SPICE, the user must first create a file, referred to as spice deck, which contains the complete description of the
circuit (including device models) along with a description of the excitation and the type of analysis desired. This file is
accessed when the SPICE program runs.
Brief introduction to SPICE:
• Simulation Program with Integrated Circuit Emphasis (SPICE)
– Developed at UC Berkeley
– Industry-standard general-purpose circuit simulator
• Numerical simulation
– Modified nodal analysis
– External nodes define boundary conditions
• Circuit elements represented by device models
• Text input, text or graphical output
Circuit Elements in SPICE
• Resistors
• Capacitors
• Inductors and coupled inductors
• Independent sources (V, I)
• Dependent sources
• Transmission lines
• Switches
• Uniform distributed RC lines
• Active devices
– Diodes, BJTs, JFETs, MOSFETs, MESFETs
SPICE File
• A SPICE file is made of a series of statements.
• First line is a title statement.
• Last line is an end statement.
• The order of other statement is arbitrary.
• Element statements describe the circuit.
• Control statements describe model parameters and execute analyses.

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

2
STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)
MOSFET Model, Level 1 Large signal model, Level 2 Large Signal Model :
MOSFET Model:
SPICE provides a wide variety of MOS transistor models with various trade-offs between complexity and accuracy. Level
1 and Level 3 models were historically important, but they are no longer adequate to accurately model very small
modern transistors. BSIM models are more accurate and are presently the most widely used. Some companies use their
own proprietary models.
SPICE Version 2G has three different MOSFET models, designated as Level 1, Level 2, and Level 3. Version 3 of SPICE
also contains a fourth MOSFET model, the BSIM model. The BSIM model is a process oriented model which places a
major emphasis on short channel devices. The discussion here will be restricted to the Level 1, Level 2, and Level 3
models.
The Level 1 model is termed the Shichman-Hodges model. It closely follows the work of Sah 13. The Level 1 model
is the simplest model and is useful for verifying that no errors occurred in the hand calculations. In some applications
the Level 1 model may be adequate for computer simulations.
The Level 2 model differs from the Level 1 model both in its method of calculating the effective channel length and
the transition between the saturation and ohmic regions. A time consuming polynomial routine is required for the
Level 2 model to determine the transition point between the linear and saturation regions. The Level 2 model offers
improvements in performance which are particularly significant for short channel devices.
The Level 3 model is termed a semi-empirical model. Several empirical parameters are introduced in the Level 3 model.
These parameters may offer improvements in fit of the model. The Level 3 model also offers a reduction in time
required to calculate the transition point between the linear and saturation regions of operation.
The Level 1, Level 2, and Level 3 device models can be found respectively in subroutines MOSEQ1, MOSEQ2, and
MOSEQ3 of the SPICE source code. Subroutine MODCHK is used for some of the hierarchical parameter definitions. The
terminal voltages of the MOSFET are passed to these subroutines, and the nodal currents are returned along
with the small signal model parameters at the operating point. In each interval of time in a transient analysis,
nodal currents are comprised of two parts. The first is the dc current obtainable from the large signal device model.
The second is the charge current associated with the parasitic capacitances in the devices. This latter current plays a
major role in high-frequency transient analyses.

Enter model parameter Calculate VTH Calculate mobility

device branch voltages

Calculate K’ Calculate LEFF Calculate VDSAT

Calculate large signal Calculate charge current Return branch current

current and small signal
parameters

Fig. 3.1 : Simplified flow chart for spice subroutines MOSEQ 1, MOSEQ2, MOSEQ3

A simplified flow chart for spice subroutines MOSEQ 1, MOSEQ2, MOSEQ3 is shown in figure above . The large signal
currents in quadrant-1 of Id –Vds are calculated from the expression:
IG= IB =0
ID = I CUTOFF VGS< VTH
ID = I OHMIC VGS>VTH ; VDS< VDSAT
ID =I SAT VGS>VTH ; VDS> VDSAT

Level 1 large signal model:

The regions of operation are given by:
IG = IB = 0
I CUTOFF VGS < VTH

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

3
STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)
ID = I OHMIC VGS > VTH VDS < VDSAT (Where VDSAT = VGS - VTH )
I SAT VGS > VDS > VDSAT
And diferent drain currents are :
ICUTOFF = 0
IOHMIC = K’(W/LEFF)([VGS –VTH]-VDS/2)VDS
I SAT = K’/2 (W/LEFF)[VGS –VTH]2
where VDSAT is given by VDSAT = VGS –VTH
The parameters VTH and LEFF represent the threshold voltage and effective length of the device and are given by:
VTH= VT0 +γ* √(φ-VBS) – √(φ)
LEFF = LADJ /(1+λ VDS)
VT0 is zero bias threshold voltage; λ is channel length modulation and SPICE input parameter ;
γ is the bulk threshold parameter, φ is the surface potential;
The parameter K’ is given as:
K’ = µ0 C ox
Where µ0 norminal channel mobility; Cox gate oxide capicitance and T OX oxide thickness
C ox = ε ox / T OX where, ε ox dielectric constant of Sio2
Ladj represent the adjusted length which is drawn length reduced the lateral diffusion on the drain and source, LD:
Ladj = L  2 LD
The parameter in VTH if not input, are calculated from
γ =( √(2 q εsi NSUB ) / C ox ;  = (2kT/q ) ln ( NSUB / ni )
VTO = VFB + γ √(φ ) + φ
where, εsi is the dielectric constant of silicon, NSUB is the substrate doping, q is the charge of an electron, ni is the
intrinsic carrier concentration of silicon. NSUB is a spice input parameter and εsi & ni are physical constants .
The flatband voltage, VFB is given by
VFB = φms  (qNss / C ox)
Where VFB is flat band voltage; input parameter, NSS , is the effective surface density and φms is the semiconductor work
function difference and is calculated as: φms = WFN  (/2) where the parameter WFN is an internal function of physical
constants characteristics of the materials involved, TGP which specifies the type of materials used to construct the
device and temperature.

Level 2 Large Signal Model:

ICUTOFF = 0 NFS=0
= Iweak inversion NFS≠0

𝑲′𝟐 𝑾 𝑽𝑫𝑺
IOHMIC = 𝑽𝑮𝑺 𝑽°𝑻𝑯 − 𝜼 𝑽𝑫𝑺 + IBSO
𝑳𝒆𝒇𝒇 𝟐
𝑲′𝟐 𝑾 𝟐
ISAT = 𝑳𝒆𝒇𝒇
𝑽𝑮𝑺−𝑽°𝑻𝑯 𝟐 − 𝜼 + IBSS
Where the cutoff transition region is determined by:
𝝅 𝜺𝒔𝒊
VTH = VTO+ γ 𝝋 − 𝑽𝑩𝑺 − 𝝋 – γα 𝝋 − 𝑽𝑩𝑺 + 𝝋 − 𝑽𝑩𝑺
𝟒 𝑪𝒐𝒙 𝑳𝒂𝒅𝒋
(DELTA)
Parameter VMAX is used to characterize the saturation/ohmic transition, it denotes the maximum drift velocity of the
carriers in the channel. If parameter VMAX is not input, the saturation or ohmic transition region is determined by:
−𝟐 𝟏/𝟐
𝑽𝑮𝑺− 𝑽°𝑻𝑯 𝟏 𝜸𝒔 𝟐 𝜸 𝑽𝑮𝑺− 𝑽°𝑻𝑯
VDSAT = 𝜼
+ 𝟐 𝜼
. 𝟏− 𝟏+𝟒 𝜼
(𝟏 − 𝜶) 𝜼
+ 𝝋 − 𝑽𝑩𝑺

The parameters , VTH, IBSO and IBSS are given as follows:

𝝅 𝜺𝒔𝒊
η= 1+ 𝟒 𝑪𝒐𝒙 𝑳𝒂𝒅𝒋
(DELTA)
𝝅 𝜺𝒔𝒊
𝑽°𝑻𝑯= VTO - γ 𝝋 + (𝝋 − 𝑽𝑩𝑺 ) 𝟒 𝑪𝒐𝒙 𝑳𝒂𝒅𝒋
(DELTA)
𝟑 𝟑
𝟐 𝑲′𝟐 𝑾 𝜸𝒔
IBSO =− 𝟑 (𝝋 + 𝑽𝑫𝑺 − 𝑽𝑩𝑺 )𝟐 − (𝝋 − 𝑽𝑩𝑺 )𝟐
𝑳𝒆𝒇𝒇 𝜼

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

4
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)

The gate source overlap capacitance CGSOL= ε L D.W /t OR CGSOL= CGSO W

where, CGSO= ε L D/t represents the overlap capacitance per unit width of the gate. W.LD is effective area of the overlap
component of the gate –source capacitance where W is the channel width and LD is lateral difusion of source. CGSO
serves as an input parameter in SPICE to model overlap capacitance.
If CGSO is not entered in SPICE, then CGSOL= Cox. (L D).W
The gate-drain overlap capacitance is modeled in the same manner.
From above figure 3.2, gate-bulk overlap capacitance is linearly proportional to L and dependent upon d1 and d2. The
dielectric thickness of the gate bulk overlap is essentially equal to the gate oxide thickness on the sides adjacent to the
channel and equal to the hight of the field oxide on the sides from the channel. It is voltage independent and
proportional to L, it is modeled by
CGBOL= CGBO .L where, CGBO represent the bulk capacitance per unit length of the device. CGBO serves as an input
parameter in SPICE to characterize the gate-bulk overlap.
Those capacitor that are voltage dependent are the pn junction capacitors. They occur between bulk and source, bulk
and drain, and bulk and channel. They are modeled as:
C=Cj0 A / (1 - VF /B)n for VF < FC. B
Cjo is zero bias junction capacitance density; FC is called the forward biased capacitance coefficient (FC≈ 0.5) , B is the
barrier potential, n is constant that characterize the junction type, A is the junction cross sectional area and V F is the
forward biased on the junction (usually negative for MOS devices).
A cross section of diffused region showing parasitic junction capacitors is shown in figure 3.3.

Large Junction Small Junction

n Side walls n

CSW CSW
CB
CB

p-substrate

Fig . 3.3 : Cross section of diffused region showing parasitic junction capacitors

The junction is not planar. The impurity concentrations in the p and n type materials at the bottom of the junctions are
different than the concentrations along the sidewalls causing the grading coefficient, n, to vary as a function of
position. Although the side wall capacitances become negligible for large structures, they may actually dominate for
small or narrow junctions. The total junction capacitance associated with the "reverse biased" (actually for VF< FC. ɸB)
junction of either the source or drain is thus
CRB TOTAL = CJ.A/[1-(VF/Φ B)MJ] + CJSW.P/[1-(VF/Φ B)MJSW]
where CJ is the zero-bias bottom capacitance area density, CJSW is the zero-bias sidewall capacitance per unit length of
the perimeter, MJ is the bottom junction grading coefficient. FC is the forward bias coefficient and MJSW is the
sidewall grading coefficient. A is the junction bottom area and P is the junction sidewall perimeter. The
parameters FC, CJ, CJSW, MJ, MJSW and Φ B can be entered in SPICE on the .MODEL card (line). The parameters
A and P for the drain and source junctions must be entered on the device card (line). CJ is calculated Under
the assumption of a step graded junction, from the expression CJ = √(εsi q NSUB / 2φB)

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

6
STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)
Under forward biased ( VF > FC. φB), the total junction capacitance are modeled by
CFB TOTAL = [( CJ.A )/ (1FC) (1+MJ) ][ (1FC) (1+MJ) + (VBS / φB ).MJ] + [( CJSW.P )/ (1FC) (1+MJSW) ][ (1FC) (1+MJSW) + (VBS
/ φB ).MJSW]

Noise Model of the MOSFET :

There are four noise current generator in MOSFET device model in SPICE . Two of these represent thermal noise
associated with the parasitic series resistances in the drain and source. These are modeled by spectral densities of SIRD
= 4kT/RD and SIRS = 4kT / RS.
Where k is Boltzmann constant , T is temperature in Kelvin and RD and RS are drain and source parasitic resistance .
The other two noise current generators are modeled as current sources from drain to source. One represent white shot
noise and other flicker (1/f) noise. These are characterized in the saturation region by spectral densities of Sw = 8kTgm/3
and Sf = (Kf)Idq AF/(f. Cox .W. Leff)
Where Kf and AF are user enterable parameters, gm is small signal trans conductance gain at Q – point, IDQ is the
quiescent drain current, Leff is the effective channel length and f is the frequency in Hz. All noise sources are assumed to
be uncorrelated. SW and SF add to obtain the overall noise spectral density .

Diode Model :
Individual diodes are modeled by two step process in SPICE. The device element line (card) contains information about
the nodal location of the device in the circuit as well as geometric information and optional initial condition variables
useful in transient analysis.
In the device element line, reference is made to a specific device modal. The model line card contains generic
information about the electrical characteristics of the device formed in the process based on the characterizing process
parameters. Each diode has separate device elements lines.
A philosophy distinctly different from that used for characterizing MOS processes has been adopted for characterizing
the process used to fabricate diodes. The difference lies is that the characteristics of the specific reference diode are
specified in model line. The size of the reference is conceptually random, although it is advice to select a reference that
is geometrically similar, in size and shape of those devices that will be modeled. In the device element line (card) the
relative area of the reference diode used to characterize the model is specified.
The diode is modeled as series combination of resistors, rs and a non ideal diode, D2, shunted by parasitic capacitor, CD
as indicated in figure 3.4 (a ). The resistor rs accounts for both the series resistance of the diode as well as high level
injection effects.
The current of diode D2 is modeled as sum of dc (large signal) current be denoted by IDC, and a current that flows
through the parasitic shunting capacitance associated with the pn junction.

rS

D1 IC IDC

D2 VD
CD
( a) (b)
Fig.3.4 : Diode model in spice (a) Physical two terminal device (b)Equivalent circuit

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

7
STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)
Large Signal Diode Current:
The large signal diode current, IDC, is modeled by that given in standard diode equation.
IDC = IS An(e VD/(nVT)  1) where VT = KT/q
Is = Saturation current and n= emission coefficient
The parameter An represents the normalized cross section area of the junctions. It is a dimensional parameter that is
entered on the device element line; it represents the ratio of the cross sectional area of the device on the device
element line. If not specified, SPICE adopt a default value of An=1. The reverse breakdown voltage, BV is not major
concern, in VLSI, design since Bv generally exceeds the maximum voltage which is permitted in VLSI circuit.

BJT Model:
The SPICE model of the BJT is based upon a modified Gummel - Poon model. Simulations based upon the simpler
Gummel-Poon model made by setting the appropriate Ebers-Moll parameters to zero . Use of the Ebers-Moll model in
the early stages of a simulation may be useful for verifying theoretical hand calculations.
The bipolar junction transistor is modeled by two input lines (cards) in SPICE. The device line (card) is used for
indicating the nodal connections of the BJT in a circuit. It is also used to reference a specific model, by name, which
contains process information. An optional normalized parameter on the device line, An, is used to indicate the ratio of
the area of the emitter to the emitter area of the device of the referenced model. An optional initial condition
parameter can also be included on the device line if desired.
The second input line (card) that is used to model the BJT is the MODEL line. SPICE version 2G.6 provides for user entry
of up to 40 parameters on the MODEL line for characterizing the device. As was the case with the diode, a user-
selected reference transistor is used to characterize the bipolar process. The BJT model information is contained
primarily in subroutines MODCHK and BJT in the SPICE source code. MODCHK does pre-processing of some of the input
parameters. The model itself basically appears in subroutine BJT.
The case for the other semiconductor models in SPICE, the BJT model is characterized by four types of input
parameters. These are 1) large signal or DC parameters, 2) charge storage or capacitance parameters, 3) noise
parameters, 4) temperature characterization parameters.
The small signal low-frequency model used in SPICE is obtained from a symbolic differentiation of the large
signal current equations evaluated at the DC operation point. As is the case for all small signal analyses in SPICE,
the small signal model of the BJT is linear and thus the small signal simulation gives no distortion information.
Distortion information at a specific frequency can be obtained from a much more time consuming transient
response with a sinusoidal excitation of fixed frequency and amplitude. To obtain reliable distortion information,
it is crucial that the transient analysis interval is long enough to guarantee essentially steady state operation.
CA
CA

Rc Rc
CBX
CA
CBC
T2
Rb +
BA T1 VCE T2
BA BA Rb
VBE _ CBE

EA
Re CCS
Re

EA
EA

Fig. 3.5 : Modeling of BJT in SPICE(A)DC Modeling (B)High frequency BJT Modeling

A series resistance is modeled in series with each lead of the BJT as shown in fig. 3.5. These resistances are input
parameters in SPICE. In the model, all formulation is relative to transistor T2.

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

8
STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)

High-Frequency BJT Model

The high-frequency model of the BIT used in SPICE is obtained by adding three parasitic capacitors to the transistor
T2 in Fig. 3.5 and one capacitor, CBX, between the base of T1 (node BA) and the collector of T2 (node C). The
parasitic capacitors are, in general, voltage dependent. The capacitor values used in SPICE are defined by the derivative
𝒅𝑸
C = 𝒅𝑽
where Q is the charge on the capacitor and V is the corresponding port voltage. Seventeen parameters are used to
characterize the four parasitic capacitors in SPICE.
The parasitic capacitors are, in general, modeled by the parallel combination (sum) of a depletion region capacitor and
a capacitor which occurs due to charge accumulation in the depletion region .The capacitor attributed to the charge
accumulation is current dependent. Finally, under forward bias the model for the parasitic capacitors has a different
parametric form, than under reverse bias. The voltage where transition must be made from the reverse bias parametric
capacitance model to the forward bias parametric model is termed the transition voltage.
The depletion region reverse-biased junction capacitors are defined by the
CBEDR = An. CJE (1-VBE /ΦB)-MJE
CBCDR = θAn. CJC (1-VBC /ΦC)-MJC
CCSDR = An. CJS (1-VCS /ΦS)-MJS
CXSDR = (1 ΦS)An. CJC (1-VBC /ΦC)-MJC
where MJE, MJS, MJC, CJE, CJS and CJC are input parameters. ΦB, ΦC, ΦS and θ are also spice input parameters, denoted by
PB, PS, PC and XCJC. The parameter θ represents the percentage of the B-C capacitance which is associated with the
internal base node (base of T2 in fig. 3.5). VBC is the voltage from the base of T1 to the collector of T2 in fig. 3.5. The
transition voltages VBET, VBCT, VCST and VXST are FC. ΦB, FC. ΦC, 0 V and FC. ΦC respectively where FC is a SPICE input
parameter used to characterize the transition.

BJT NOISE MODEL:

Five noise sources are used to model the noise characteristics of BJT. Thermal resistance noise source are characterized
by current source with spectral density of
𝟒𝒌𝑻
SNR = 𝑹x
for x ε {b,e,c}
These are modeled in parallel with three resistors, Rb, Re, Rc, of fig.3.5. Shot and flicker noise are modeled by two
current sources, the first with spectral density of
SNB = 2q ICQ
Is connected from the base of emitter, of T2. The second current source has spectral density of

AF
𝑲F 𝑰BQ
SNC = 2qIBQ + 𝒇
and is connected from the collector to the emitter of T2 in the same figure. KF and AF are spice, input parameters and f
is frequency in hertz. IBQ and ICQ represent the quiescent values of IB and IC respectively. All noise source the BJT are
assumed to be uncorrelated.

Temperature Dependence of BJT:

Several of the parameters that characterize the BJT are temperature dependent. SPICE models the temperature
dependence of the saturation currents IS, ISE and ISC, betas (BF and BR), the junction capacitance parameters (CJE, CJC, CJS,
φB, φC, φS ) and the noise coefficient KF and AF. The saturation currents at temperature T are characterized by equations
𝑻 XTI 𝑻 𝑬𝑮 𝑻 .𝒒
IS(T) = IS(T1) 𝐓1
exp 𝑻 − 𝟏 𝒌𝑻
𝟏
𝑻 {(XTI/NE)- XTB} 𝑻 𝑬𝑮 𝑻 .𝒒
ISE(T) = IS(T1) 𝐓 exp 𝐓 − 𝟏 [ 𝒌𝑻 ]
1 𝟏
𝑻 {(XTI/NC)- XTB} 𝑻 𝑬𝑮 𝑻 .𝒒
ISE(T) = ISC(T1) 𝑻 exp 𝑻 − 𝟏 [ 𝑵𝑪.𝒌𝑻 ]
𝟏 𝟏
Where T1 is any reference temperature.
The parameters BF and BR are given by expressions

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

9
STUDY MATERIAL
Downloaded from www.rgpvnotes.in, whatsapp: 8989595022 VLSI DESIGN (EC701)
𝑻 XTB
BF = BF (T1) 𝑻𝟏
𝑻 XTB
BR = BR (T1) 𝑻𝟏
The temperature dependence CJE, CJC, CJS, φB, φC, φS is given for Y∈ {𝐶, 𝐸, 𝑆} by
CJY (T) = CJYT1 . 𝟏 + 𝜽𝒀 (𝑻) where
𝜽 Y (T) = MJY {0.0004 (T-T1) + 1- *φY(T)/ φY (T1)]} and
φ Y (T) = φ Y (T1) . (T/T1) + φBF (T)

follow us on instagram for frequent updates: www.instagram.com/rgpvnotes.in

10
Thank you for using our services. Please support us so that we can
improve further and help more people.
https://www.rgpvnotes.in/support-us

If you have questions or doubts, contact us on

WhatsApp at +91-8989595022 or by email at [email protected].

For frequent updates, you can follow us on

Instagram: https://www.instagram.com/rgpvnotes.in/.