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COURSE MATERIAL

SUBJECT VLSI DESIGN (15A04604)

UNIT 5

COURSE B.TECH

DEPARTMENT ECE

SEMESTER 32

PREPARED BY Mr. ALLABAKSH SHAIK

(Faculty Name/s) Assistant Professor

Version V-1

PREPARED / REVISED DATE 21-03-2021

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TABLE OF CONTENTS – UNIT V

S. NO CONTENTS PAGE NO.
1 COURSE OBJECTIVES 1

2 PREREQUISITES 1
3 SYLLABUS 1
4 COURSE OUTCOMES 1

5 CO - PO/PSO MAPPING 2
6 LESSON PLAN 2
7 ACTIVITY BASED LEARNING 2

8 LECTURE NOTES 2
5.1 Introduction on HDL 2
5.2 Features of VHDL 3

5.3 VHDL Synthesis 3

5.4 Circuit Synthesis 4
5.5 Simulation 6

5.6 Types of Simulation 6

5.7 DESIGN CAPTURE TOOLS 8
5.8 DESIGN VERIFICATION TOOLS 9

5.9 TESTING 10
5.10 Test Classification 11
5.11 Design for Testability 11

5.12 Controllability/Observability 12
5.13 Test Approaches 12
5.14 Generating and Validating Test-Vectors-Automatic test-
13
pattern generation (ATPG)

5.15 Generating and Validating Test-Vectors-Fault simulation 13

5.16 Fault Models 13
5.17 Path Sensitization 14

5.18 Ad-hoc Test 16

5.19 Scan-based Test 17

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5.20 Scan-Path Register 19

5.21 Boundary Scan (JTAG) 21

5.22 Self-test 21
5.23 Linear-Feedback Shift Register (LFSR) 22

5.24 Signature Analysis 22

5.25 BILBO 23
5.26 Memory Self-Test 24

5.27 BIST (Built-In Self-Test) 24

5.28 Test Pattern Generation Techniques 25
5.29 Test Response compression techniques 26

9 PRACTICE QUIZ 27
10 ASSIGNMENTS 29
11 PART A QUESTIONS & ANSWERS (2 MARKS QUESTIONS) 29

12 PART B QUESTIONS 30
13 SUPPORTIVE ONLINE CERTIFICATION COURSES 31
14 REAL TIME APPLICATIONS 31

15 CONTENTS BEYOND THE SYLLABUS 31

16 PRESCRIBED TEXT BOOKS & REFERENCE BOOKS 31
17 MINI PROJECT SUGGESTION 32

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1. Course Objectives
The objectives of this course is to
1. To acquire knowledge on adders and shifters.
2. To understand the functioning of ALUs.
3. To present different types of multipliers.
4. To explain parity generators and comparators.
5. To analyze high density memory elements.
6. To describe different VLSI design styles.

2. Prerequisites
Students should have knowledge on
1. Electronic Devices and Circuits
2. Switching Theory and Logic Design
3. Digital System Design

3. Syllabus
UNIT V
VHDL Synthesis: VHDL Synthesis, Circuit Design Flow, Circuit Synthesis, Simulation,
Layout, Design capture tools, Design Verification Tools.
Test and Testability: Fault-modelling and simulation, test generation, design for
testability, Built-in-self-test.

4. Course outcomes
1. Understand the concepts of Sub-System Design.
2. Analyze and Design High density memory elements and counters
3. Identify and Understand Various VLSI design styles.
4. Understand the full custom and semi-custom design approaches.

5. Co-PO / PSO Mapping

Linear
Integrated
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
Circuits and
Applications
CO1 3 3 3 2 2 1 1 1 1 1 2

CO2 3 3 3 2 2 1 1 1 1 1 2

CO3 3 3 3 2 2 1 1 1 1 1 2

CO4 3 3 3 2 2 1 1 1 1 1 2

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6. Lesson Plan

Lecture No. Weeks Topics to be covered References

1 VHDL Synthesis T1,R1

2 Circuit Design Flow T1, R1

3 1 Circuit Synthesis, Simulation T1, R1

4 Layout, Design capture tools, T1, R1

5 Design Verification Tools. T1, R2

6 Fault-modelling and simulation, T1, R1

7 test generation T1, R1

8 2 Test generation T1, R1

9 design for testability T1, R1

10 design for testability T1, R1

11 3 Built-in-self-test. T1, R1

7. Activity Based Learning

1. Prepare power point presentations on Sub-System design circuits
2. Prepare Journals on Multipliers, ALUs and High density memory elements.
3. Prepare posters on various VLSI Design Styles.

8. Lecture Notes

5.1 Introduction on HDL

 HDL stands for Hardware Description Language.
 HDL is similar to a computer programming language except that an HDL is
used to describe hardware rather than a program which is executed on a
computer. There are two HDLs are available
o VHDL
o Verilog
 Traditional Methods of Hardware Design:
 Design with Boolean equations
 Schematic based design

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5.2 Features of VHDL

 Concurrent language
 Sequential language
 Netlist- It is textual information of logic cells and their interconnections.
Data is available in the EDIF format.
 Test bench - used for verification of design
 Timing specification -supports synchronous and asynchronous timing
models
 Supports all types of design methodologies-top-down and bottom-up or
mixed design.

5.3 VHDL SYNTHESIS

Synthesis is an automatic method of converting a higher level abstraction likes
behavioural into a gate level description. The basic function of synthesis is to
produce a gate level netlist for target technology. There are three steps followed
for converting to gate level design RTL description is translated to un-optimized
Boolean descriptions. It consisting of primitive gates like AND, OR & FFs. This is the
functionally correct but un-optimized description. To produce the optimized
Boolean equivalent description. Optimized description is mapped to actual logic
gates by making use of technology library of the target process.

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5.4 CIRCUIT SYNTHESIS

Circuit synthesis has the following steps:

 Translation
 Boolean optimization
 Flattening
 Factoring
 Mapping to Gates

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Translation
The RTL description is converted by the logic synthesis tool to an un-optimized,
intermediate, internal representation. This process is known as translation. It is not
user controllable. It is relatively simple and uses techniques of HDL constructs
interpretation is a process which converts all conditional or sequential and
concurrent statements to Boolean equivalent format.

Boolean optimization
The optimization process takes an unoptimized Boolean description and converts
it to an optimized Boolean description. Optimization is the process which
decreases the area or increases the speed of a design.

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Flattening
The process of converting unoptimized Boolean description to PLA format is known
as flattening. A PLA structure is a very easy description in which to perform Boolean
optimization. (conversion of Boolean equation into a two level sum of product
form)

Factoring
Factoring is to add intermediate terms.

Mapping to gates
The mapping process takes the optimised Boolean description and uses the logical
and timing information from a technology library to build a netlist. This netlist is
targeted to the users needs for area and speed. There are a number of possible
netlists that are functionally same but vary widely in speed and area.

5.5 SIMULATION
Simulation is the process of applying stimuli (test inputs) to design under test over
same duration of time and producing the response from the design under test.
Simulation verifies the operation of user’s design before actually implementing it
as hardware. Necessity of simulation is:
 Need to test the designs prior to implementation and usage.
 Reduce the time for development
 Decrease the time to market.

5.6 TYPES OF SIMULATION

Simulators are usually divided into the following categories or simulation modes:
 Behavioural simulation
 Functional simulation
 Static timing analysis
 Gate-level simulation
 Switch-level simulation
 Transistor-level or circuit-level simulation

This list is ordered from high-level to low-level simulation (high-level being more
abstract and low-level being more detailed). Proceeding from high-level to low-
level simulation, the simulations become more accurate, but they also become
progressively more complex and take longer to run. While it is just possible to
perform a behavioural-level simulation of a complete system, it is impossible to
perform a circuit-level simulation of more than a few hundred transistors.

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There are several ways to create an imaginary simulation model of a system.
One method models large pieces of a system as black boxes with inputs and
outputs. This type of simulation (often using VHDL or Verilog) is called behavioural
simulation. Functional simulation ignores timing and includes unit-delay simulation,
which sets delays to a fixed value (for example, 1 ns). Once a behavioural or
functional simulation predicts that a system works correctly, the next step is to
check the timing performance. At this point a system is partitioned into ASICs and
a timing simulation is performed for each ASIC separately (otherwise the simulation
run times become too long). One class of timing simulators employs timing
analysis that analyzes logic in a static manner, computing the delay times for each
path. This is called static timing analysis because it does not require the creation
of a set of test (or stimulus) vectors (an enormous job for a large ASIC). Timing
analysis works best with synchronous systems whose maximum operating
frequency is determined by the longest path delay between successive flip-flops.
The path with the longest delay is the critical path.

Logic simulation or gate-level simulation can also be used to check the timing
performance of an ASIC. In a gate-level simulator a logic gate or logic cell (NAND,
NOR, and so on) is treated as a black box modelled by a function whose variables
are the input signals. The function may also model the delay through the logic cell.
Setting all the delays to unit value is the equivalent of functional simulation. If the
timing simulation provided by a black-box model of a logic gate is not accurate
enough, the next, more detailed, level of simulation is switch-level simulation which
models transistors as switches—on or off. Switch-level simulation can provide more
accurate timing predictions than gate-level simulation, but without the ability to
use logic-cell delays as parameters of the models. The most accurate, but also the
most complex and time-consuming, form of simulation is transistor-level simulation.
A transistor-level simulator requires models of transistors, describing their nonlinear
voltage and current characteristics.
Each type of simulation normally uses a different software tool. A mixed-mode
simulator permits different parts of an ASIC simulation to use different simulation
modes. For example, a critical part of an ASIC might be simulated at the transistor
level while another part is simulated at the functional level. Be careful not to
confuse mixed-level simulation with a mixed analog/digital simulator, these
are mixed-level simulators.

Simulation is used at many stages during ASIC design. Initial prelayout

simulations include logic-cell delays but no interconnect delays. Estimates of
capacitance may be included after completing logic synthesis, but only after
physical design is it possible to perform an accurate post layout simulation.

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5.7 DESIGN CAPTURE TOOLS

HDL Design
 Schematic Design
 Floorplanning
HDL Design
HDLs are used to design two kinds of systems:
 Integrated Circuit
 Programmable Logic Devices

 HDL design can be used for designing ICs like processor or any other kind of
digital logic chip.
 HDL specifies the model for the expected behaviour of circuit before actual
circuit design and implementation.
 PLDs like FPGA or CPLD can be designed with HDLs. HDL code is fed into
logic compiler and output is uploaded into actual device. The important
property of this procedure is that it is possible to change the code many
times, compile it and upload in the same device.

Schematic Design

 Schematic design provides a means to draw and connect components.

 Schematic editors are available with various features like
 Creating, selecting and deleting parts by pointing
 Changing the graphic view by panning, zooming.

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5.8 DESIGN VERIFICATION TOOLS

 The functionality of the CMOS chips is to be verified certain set of verification
tools are used for testing specifications.
 The following tools are popular for design verification
1. Simulation
 Circuit Level Simulation
 Timing Simulation
 Logical Level Simulation
 Mixed mode Simulation
2. Timing verifiers
3. Netlist comparison
4. Layout extraction
5. Design rule verification

Schematic Rule Check (SRC)

 In cell based designs a schematic rule checker used to verify the schematics
i.e schematic rule violation. The violation of rule may be indicated in terms
of warning or errors.
 SRC warnings:
o Floating wire segments
o Open connection
o Higher fan-out

 SRC errors
 Undefined inputs/open inputs
 Unmatched bus connections
 Multiple drivers connection to single line
 Different I/O pins

Design Rule Check (DRC)

 The mask database provides interface between the semiconductor and

chip designer. Two important requirements for this interface are:
o 1. Specified geometric design
o 2. Inter relationships of the mask
 The test for above two requirements is carried out by a CAD tools called
DRC.
 Two different categories of DRC programs are used
o 1. Polygonal check
o 2. Raster scan check
 The polygonal design rule checks involves various mathematical operations
during the check.

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5.9 TESTING
 Testing is everything when it comes to making $$$$$.
 Selling bad silicon can bankrupt a company.
Three main categories
– Functionality test or logic verification (before tapeout)
• Make sure functionality is correct
– Silicon debug (on first batch of chips from fab)
• detective work
• You don’t want to mass-produce bad chips
– Manufacturing test (on each mfg’d chip before shipping)
• You don’t want to ship bad chips
Testing and/or debugging a chip costs at various levels
 Wafer level -$0.01-$0.10
 Packaged chip level -$0.10-$1
 Board level -$1-$10
 System level -$10-$100
 Field level -$100-$1000
Cost goes up exponentially if fault detected at later stages
$0.01-$0.10 $0.10-$1 $1-$10 $10-$100 $100-$1000
Testing is one of the most expensive parts of chips
– Logic verification accounts for > 60% of design effort for many chips
– Debug time after fabrication has enormous opportunity cost
– Shipping defective parts can sink a company

Logic Verification
Does the chip simulate correctly?
– Usually done at HDL level
– Verification engineers write test bench for HDL
• Can’t test all cases
• Look for corner cases
• Try to break logic design
- Good tests require ingenuity

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Manufacturing Test
A speck of dust on a wafer is sufficient to kill chip
-Yield of any chip is < 100%
– Must test chips after manufacturing before delivery to customers to only ship
good parts
-Manufacturing testers are very expensive
– Minimize time on tester
– Careful selection of test vectors

Tester and test fixtures –

-Can be very expensive (e.g., $1-2M)
If you don’t have a multimillion dollar tester:
– Build a breadboard with LEDs and switches
– Hook up a logic analyzer and pattern generator
– Or use a low-cost functional chip tester

5.10 Test Classification

 Diagnostic test
o used in chip/board debugging
o defect localization
 “go/no go” or production test
o Used in chip production
 Parametric test
o x e [v,i] versus x e [0,1]
o check parameters such as NM, Vt, tp, T

5.11 Design for Testability

DFT techniques are design efforts specifically employed to ensure that a device in
testable.

 In general, DFT is achieved by employing extra H/W.

 ⇒Conflict between design engineers and test engineers.
 ⇒ Balanced between amount of DFT and gain achieved.

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 Examples:
DFT increase in Area & increase in Logic complexity Yield decreases
For fixed fault coverage, defect level increases.
 Therefore, DFT must guarantee to increase fault coverage
 Provide circuitry to enable test
 Provide test patterns that guarantee reasonable coverage
N inputs K outputs
N inputs Combinational K outputs Combinational
Logic Logic

Module Module

M state regs

(a) Combinational function (b) Sequential engine

2N patterns 2N+M patterns

Exhaustive test is impossible or unpractical

5.12 Controllability/Observability
 Combinational Circuits:
Controllable and observable: The ability to set some circuit nodes to a
certain states or logic values. The ability to observe the state or logic
values of internal nodes.
 Sequential Circuits: State! -Turn into combinational circuits or use self-
test
 Memory: requires complex patterns- Use self-test

5.13 Test Approaches

 Ad-hoc testing
 Scan-based Test
 Self-Test

Problem is getting harder

» Increasing complexity and heterogeneous combination of modules in system-
on-a-chip.

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» Advanced packaging and assembly techniques extend problem to the
board level

5.14 Generating and Validating Test-Vectors-Automatic test-pattern generation

(ATPG)
o for given fault, determine excitation vector (called test vector) that will
propagate error to primary (observable) output

o majority of available tools: combinational networks only

o sequential ATPG available from academic research

o Both require adequate models of faults in CMOS integrated circuits

5.15 Generating and Validating Test-Vectors-Fault simulation

o determines test coverage of proposed test-vector set

o simulates correct network in parallel with faulty networks

o Both require adequate models of faults in CMOS integrated circuits

5.16 Fault Models

sa0
0 (output)

1
sa1
(input)

Most Popular - “Stuck - at” model

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Z
x1 

, : x1 sa1
 : x1 sa0 or
x3
x2 

x2 sa0
 : Z sa1
Covers almost all (other) occurring faults, such as opens and shorts.

Problem with stuck-at model: CMOS open fault

x1 x2

Z
x1

x2

Sequential effect -Needs two vectors to ensure detection!

C D
‘0’
Other options: use stuck-open or stuck-short models
A B
‘0’
This requires fault-simulation and analysis at the switch or
transistor level - Very expensive!
‘0’ A C

Causes short circuit between Vdd and GND for A=C=0, B=1
‘1’ B D
Possible approach: Supply Current Measurement (IDDQ)

but: not applicable for gigascale integration

5.17 Path Sensitization

Determine input pattern that makes a fault controllable (triggers the fault, and
makes its impact visible at the output nodes)
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sa0
Fault enabling
1
1 1
Out
1
1
Fault propagation 1 0
0
Techniques Used: D-algorithm, Podem

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5.18 Ad-hoc Test

 Test points
 Initialization
 Monostable multivibrators (one shot)
 Oscillators and clocks
 Counter / Shift registers
 Partitioning large circuits
 Logic redundancy
 Break global feedback paths

 Rule: to enhance controllability and observability by inserting control points

(cp) and observation points (op), respectively.

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 Can be done only on board

Inserting multiplexer improves testability

5.19 Scan-based Test

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ScanIn ScanOut

Out
In Combinational Combinational
Register

Register

Logic Logic
A B

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5.20 Scan-Path Register

OUT
SCAN PHI2 PHI1

SCANIN SCANOUT

IN

LOAD KEEP

Scan-based Test —Operation

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In 0 In1 In2 In 3

Test Test Test Test Test Test Test Test

ScanIn ScanOut

Latch Latch Latch Latch

Out0 Out1 Out2 Out3

Test

1

2

N cycles 1 cycle N cycles

scan-in evaluation scan-out

Scan-Path Testing

A B

SCANIN
REG[1] REG[0]

REG[2] REG[3]

REG[4]
COMPIN

COMP

SCANOUT
REG[5]

OUT

Partial-Scan can be more effective for pipelined data paths

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5.21 Boundary Scan (JTAG)

 Board testing becomes as problematic as chip testing

5.22 Self-test

(Sub)-Circuit

Stimulus Generator Under Response Analyzer

Test

Test Controller

 Rapidly becoming more important with increasing chip-complexity and

larger modules

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5.23 Linear-Feedback Shift Register (LFSR)

Pseudo-Random Pattern Generator

5.24 Signature Analysis

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In
Counter

 Counts transitions on single-bit stream  Compression in time

5.25 BILBO
D0 D1 D2
B0

B1

ScanIn ScanOut
mux

R R R
S0 S1 S2

B0 B1 Operation mode
1 1 Normal
0 0 Scan
1 0 Pattern generation or
Signature analysis
0 1 Reset

BILBO Application
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ScanIn ScanOut

In Combinational Combinational Out

BILBO-B
BILBO-A
Logic Logic

5.26 Memory Self-Test

 Patterns: Writing/Reading 0s, 1s, Walking 0s, 1s Galloping 0s, 1s

5.27 BIST (Built-In Self-Test) :

 BIST is a design technique in which parts of a circuit are used to test the
circuit itself.
 Hardcore : Parts of a circuit that must be operational to execute a self test
 BIST categories :
 Memory BIST
 Logic BIST
 Logic + Embedded memory (ASICs)

Applications: Mission-critical system, self-diagnostic circuitry (consumer

electronics).

BIST TECHNIQUES:

 Test Pattern Generation Techniques (TPG)

 Test Response Compression Techniques

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The BIST techniques are classified based on the operational condition of the
circuit under test (CUT):

 Off-Line BIST
 On-Line BIST

ON-LINE BIST:

Testing occurs during normal functional operating conditions (No test mode,
Real-Time error detection).

Concurrent: Occurs simultaneously with normal functional operation (Realized

by using coding techniques).

Non-concurrent: Carried out while in idle state (Interruptible in any state,

realized by executing diagnostic software/firmware routines).

Off-Line BIST:

Deals with testing a system when it is not carrying out its normal functions (Test
mode, Non-Real-Time error detection).

Testing by using on-board TPG + Output Response Analyzer (ORA) or Micro

diagnostic routines.

Structural : Execution based on the structure of the CUT(Explicit fault model -

LFSR, ...).

Functional: Running based on functional description of CUT (Functional fault

model - Diagnostic software).

5.28 Test Pattern Generation Techniques

Exhaustive: Applying all 2**n input combinations, generated by binary counters
or complete LFSR.

Pseudo exhaustive: Circuit is segmented & each segment is tested exhaustively

(Less no. of tests required)

Logical segmentation: Cone + Sensitized-path

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Physical segmentation

Pseudorandom : Not all 2**n input combinations, Random patterns generated

deterministically & repeatable, pattern with/without replacement, applicable
to both combinational and sequential circuits.

Weighted: Non-uniform distribution of 0’s & 1’s, improved fault coverage, using
LFSR added with combinational circuits.

Adaptive: Using intermediate results of fault simulation to modify 0’s & 1’s
weights, more efficient, more hardware complexity.

5.29 Test Response compression techniques

Response compression: A process to form a “signature” from complete output
responses.

Signature: Compressed form of saved test results.

Alias: Error we output when faulty & fault-free sig. are the same.

Compression procedure: Composition of test vector applying, results storing and

comparison of the faulty & fault free signatures.

Compression of:

 Simple hardware implementation.

 Small performance degradation - No effect on normal circuit behaviour

(delay, execution time).

 High degree of compression - Signature lenghts to be a logarithmic

factor of responses lengths.

 Small aliasing errors.

Compression problems:

 Existing aliasing errors.

 Calculating the good circuit signature.

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Calculation of good circuit signatures:

 Golden Unit: Applying the test to good part of the CUT.

 Simulation: Simulating the CUT and making sure of having good
signature.
 Fault Tolerant : Producing copies of CUT and conclude the correct
signature by finding the subset which generates the same signature.

One’s count : The no. Of times when 1 occurs in each output (counter).

Transition count : The no. of transitions (0 =>1,1=>0) in the output (XOR +counter).

Parity checking : The parity of response string, 0 if even & 1 if odd (XOR + D-FF).

Syndrome checking : the normalized no. of 1’s in output string (k/2**n when k is no.
of min-terms in an n input circuit), (All possible combination tests).

Signature analysis : Based on redundancy checking (LFSR).

Advantages

 Lower cost of test

 Better fault coverage
 Possibly shorter test times
 Tests can be performed throughout the operational life of the chip

Disadvantages

 Silicon area overhead

 Access time
 Requires the use of extra pins
 Correctness is not assured

9. Practice Quiz
1. What is the process of flattening?
(a) Converting an optimized function to unoptimized form
(b) Converting a Boolean function to PAL format
(c) Converting a Boolean function to PLA format
(d) Converting a Boolean function to POS form

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2. Flattening creates a flat signal representation of ______ levels.

(a) 2
(b) 1
(c) 3
(d) 4

3. Which of the following is the opposite of flattening of functions?

a) Structure
b) Adding intermediate nodes
c) Un-flattening
d) Factoring

4. The main advantage of using factoring is ________

a) Reducing the speed
b) Reducing the number of terms
c) Adding intermediate nodes
d) Reducing flattening

5. What is another name for the factoring of functions?

a) De-flattening
b) Intermediation
c) Structuring
d) De-structuring

6. What does RTL in digital circuit design stand for?

a) Register transfer language
b) Register transfer logic
c) Register transfer level
d) Resistor-transistor logic

7. RTL is a design abstraction of what kind of circuit?

a) Asynchronous digital circuit
b) Synchronous digital circuit
c) Asynchronous sequential circuit
d) Analog circuit

8. RTL is used in HDL to create what level of representations in the circuit?

a) High-level
b) Low-level
c) Mid-level
d) Same level

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9. Which flip-flop is usually used in the implementation of the registers?

a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) J-K flip-flop

10. Which of the following tool performs logic optimization?

a) Simulation tool
b) Synthesis tool
c) Routing tool
d) RTL compiler

11.Setup time is the time required for input data to settle after the triggering edge of the
clock.
a) True
b) False

10. Assignments

S.No Question BL CO
What is the need for testing? Discuss in detail about testing at CO3,
1 2
various levels of chip fabrication? CO4
CO3,
2 Explain about synthesis and simulation steps 2
CO4
Explain about the VHDL synthesis? CO3,
3 2
CO4
2 CO3,
4 What is DFT? Explain the types of DFT
CO4
2 CO3,
5 What is simulation? Explain about different types of Simulation?
CO4

11. Part A- Question & Answers

S.No Question & Answers BL CO
1 What is meant by synthesis?
CO3,
Synthesis is an automatic method of converting a higher level 2
CO4
abstraction likes behavioural into a gate level description
2 What is meant by translation?
The RTL description is converted by the logic synthesis tool to an CO3,
2
un-optimized, intermediate, internal representation. This process CO4
is known as translation.
3 What is meant by Flattening ?
The process of converting unoptimized Boolean description to CO3,
2
PLA format is known as flattening. A PLA structure is a very easy CO4
description in which to perform Boolean optimization.

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(conversion of Boolean equation into a two level sum of product
form)
4 What are the TYPES OF SIMULATION
Simulators are usually divided into the following categories
or simulation modes :
 Behavioural simulation
 Functional simulation CO3,
2
 Static timing analysis CO4
 Gate-level simulation
 Switch-level simulation
 Transistor-level or circuit-level simulation

5 Explain briefly about Design verification tools?

The functionality of the CMOS chips is to be verified certain set of
verification tools are used for testing specifications.
The following tools are popular for design verification
1. Simulation
 Circuit Level Simulation
 Timing Simulation CO3,
2
 Logical Level Simulation CO4
 Mixed mode Simulation
2. Timing verifiers
3. Netlist comparison
4. Layout extraction
5. Design rule verification
6 What is testing? what is the need for testing?
Testing and/or debugging a chip costs at various levels
Wafer level -$0.01-$0.10
CO3,
Packaged chip level -$0.10-$1 2
CO4
Board level -$1-$10
System level -$10-$100
Field level -$100-$1000

12. Part B- Questions

S.No Question BL CO
1. What is the need for testing? Discuss in detail about testing at CO3,
2
various levels of chip fabrication? CO4
2. CO3,
Explain about synthesis and simulation steps 2
CO4
3. Explain about the VHDL synthesis? CO3,
2
CO4
4. 2 CO3,
What is DFT? Explain the types of DFT
CO4
5. What is simulation? Explain about different types of 2 CO3,
Simulation? CO4

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13. Supportive Online Certification Courses

1. Digital circuits By Prof. Santanu Chattopdhayay, conducted by IIT Kharagpur on
NPTEL – 12 weeks
2. Digital Electronic Circuits By Prof. Goutam Saha, conducted IIT Kharagpur on
NPTEL – 12 weeks

14. Real Time Applications

S.No Application CO
1 Design and implementation of FPGA based traffic control system 3
2 FPGA based Digital hearing aid chip 3
3 Security logging system based on FPGA 3

15. Contents Beyond the Syllabus

Register Transfer Level (RTL)
For digital VLSIs or for digital blocks within a mixed-signal chip, this phase is
basically the detailed logic implementation of the entire VLSI. This is where the
detailed system specifications is converted into VHDL or Verilog language. In
addition to the digital implementation, functional verification is performed to
ensure the RTL design is done according to the specifications. When all the blocks
are implemented and verified the RTL is then converted into a gate-level netlist.
Synthesis
the hardware description (RTL) is converted to a gate-level netlist. This process is
performed by a synthesis tool that takes a standard cell library, constraints and
the RTL code and produces an gate-level netlist. Synthesis tools are running
different implementations to provide best gate level netlist that meets the
constraints. It takes into account power, speed, size and therefore the results can
vary much from each other. To verify whether the synthesis tool has correctly
generated the gate-level netlist verification should be done.

16. Prescribed Text Books & Reference Books

Text Book:
1. Kamran Eshraghian, Eshraghian Douglas and A. Pucknell, “Essentials of VLSI
circuits and systems”, PHI, 2013 Edition.
2. K.Lal Kishore and V.S.V. Prabhakar, “VLSI Design”, IK Publishers
References:
1. Weste and Eshraghian, “Principles of CMOS VLSI Design”, Pearson Education,
1999.
2. Wayne Wolf, “Modern VLSI Design”, Pearson Education, 3rd Edition, 1997.
3. John P. Uyemura, “Chip Design for Submicron VLSI: CMOS layout and
Simulation”, Thomson Learning.
4. John P. Uyemura, “Introduction to VLSI Circuits and Systems”, John wiley, 2003.
5. John M. Rabaey, “Digital Integrated Circuits”, PHI, EEE, 1997.

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17. Mini Project Suggestion

1. An Efficient VLSI Architecture for Removal of Impulse Noise in Image:
This project aims to enhance the visual quality of images and to avoid chances
of being corrupted by impulse noise by implementing an efficient VLSI
architecture using edge preserving filter.

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