CPE18 Module2
CPE18 Module2
Learning Outcomes
Intended
Learning Students should be able to meet the following intended learning outcomes:
Outcomes Learn about the Relevant Tools, Standards, and/ or Engineering Constraints of
Digital Signal Processing (DSP)
Learn about the Digital Signal Processing (DSP) Convolution.
Targets/
Objectives At the end of the lesson, students should be able to:
Identify the Relevant Tools, Standards, and/ or Engineering Constraints of
Digital Signal Processing (DSP)
Know what is Digital Signal Processing (DSP) Convolution.
Lecture Guide
Code generation
Code generation methods for DSP applications are hampered by the
combination of tight timing constraints imposed by the performance
requirements of DSP algorithms, and resource constraints imposed by a
hardware architecture. We present a method to analyse resource and timing
constraints in a single model. The analysis identifies sequencing constraints
between operations additional to the precedence constraints. Without the
explicit modeling of these sequencing constraints, a scheduler is often not
capable of finding a solution that satisfies the timing and resource constraints.
The presented approach results in an efficient method of obtaining high quality
instruction schedules
DSP Algorithms
Digital Signal Processing (DSP) algorithms have the following characteristics:
Offline Activities they allow parallel execution of a number of operations, periodic executions,
(e-Learning/Self- and tight timing requirements. These algorithms can be represented using a
Paced) signal flow graph (SFG), consisting of operations, data flow edges and sequence
edges. The precedence constraints expressed in such a SFG combined with the
tight timing requirements, already pose a problem for most scheduling
methods targeting for efficient hardware. However, mapping the DSP algorithm
on a hardware platform also introduces hardware constraints, which make the
schedule problem.
Cost
Costs are generally kept constant, and are dictated by device or commercial
criteria.
Performance
The speed of a computer may also be affected. The amount of cache a
processor has can also be used to assess computer performance. If the rpm,
measured in MHz or GHz, were a vehicle, the cache would be a traffic light. A
green traffic light will not stop the vehicle, no matter how fast it is driving. The
faster a processor runs, the higher its speed and the larger its cache. Modern
CPUs can execute several instructions per clock cycle, allowing a program to
run much faster. Other variables that affect speed include the number of
functional units in the system, bus speeds, usable memory, and the type and
order of instructions in the programs being executed. Latency and throughput
are the two main types of speed. The interval between the start of a process
and its completion is known as latency. The sum of work completed per unit of
time is referred to as throughput. The system's guaranteed optimal response
time to an electronic event is known as interrupt latency (e.g. when the disk
drive finishes moving some data). A wide variety of design decisions have an
effect on performance — for example. A wide variety of design decisions
influence performance; for example, pipelining a processor reduces
latency(slower) while increasing throughput. Low interrupt latencies are
needed by computers that control machinery. These computers work in a
real-time environment, and if an operation takes longer than expected, they
will fail. Anti-virus software, for example, is computer-controlled. Computer-
controlled anti-lock brakes, for example, must begin braking almost
immediately after being told to do so.
Power consumption
Another quality criterion that influences the design of modern computers is
power consumption. Power efficiency is often exchanged for results or cost
savings. Power efficiency has become more important as the number of
transistors per chip scales (Moore's Law), owing to the power density of
modern circuits. Recent processor designs, such as the Intel I7, have placed a
greater focus on increasing performance. Recent processor designs, such as the
Intel I7, have put a greater focus on energy efficiency. In addition, power
efficiency has long been and continues to be the primary design objective in
embedded computing, second only to success.
Data dependencies.
The translation of the data dependencies in this model is straightforward: each
dependency translates to an arc with weight equal to the execution delay of the
producing operation.
Convolution
Definition
The convolution of f and g is written f∗g, denoting the operator with the symbol ∗. It is
defined as the integral of the product of the two functions after one is reversed and shifted.
As such, it is a particular kind of integral transform:
While the symbol t is used above, it need not represent the time domain. But in
Derivation
Given two functions f(t) and g(t) with bilateral Laplace transforms
and
respectively, the convolution operation f(t) * g(t) can be defined as the inverse Laplace
transform of the product of and More precisely,
Visual explanation
The sequence h(k) and x(k) in equation above are interchangeable. Hence, we
have an alternative form: (Expanded form)
Graphical Method
Table Method
Sample Problem:
Solution (a)
Sequence 1
Sequence 2
Sequence 3:
Sequence 4:
Sequence 4:
Sequence 4:
Performance Tasks
PT 1
Directions:
Advance Reading on Transform Analysis and Frequency Response
Learning Resources
https://www.researchgate.net/publication/3711737_Constraint_analysis_for_DSP_code_generation
https://www.sciencedirect.com/science/article/pii/B9781558607026500430
https://www.geeksforgeeks.org/advantages-and-disadvantages-of-digital-signals/
https://en.wikipedia.org/wiki/Convolution
http://www.analog.com/media/en/technical-documentation/dsp-book/dsp_book_ch6.pdf
https://www.youtube.com/watch?v=yu3t5bC5ut8
I am your Faculty-in-Charge. There is more information about me in our course website in LMS. You
may reach me at:
DIGITAL SIGNAL
PROCESSING
(CPE18)