EE4605 Integrated Circuits and Systems for Wireless Applications

Chapter 3, Active RF Devices

(Recap)

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EE4605 Integrated Circuits and Systems for Wireless Applications

Outline
• Figures of Merit for active devices
• Device candidates for microwave applications

• Bipolar Transistor
– Modelling the bipolar transistor
– The hybrid p model
– Scaling bipolar devices
– fT and fmax for bipolar devices
– The noise parameters
– Scaling for speed, noise & power handling
• RF CMOS devices
– Long channel devices
– Short channel devices
– fT and fMax
– The noise parameters
– scaling
• Device speed versus breakdown
• CMOS versus SiGe (Bipolar)
• References (recommended reading)
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EE4605 Integrated Circuits and Systems for Wireless Applications

Figures of Merit for Active Devices

There is the general desire to quantify device performance, e.g.
• fT - frequency @ unit current gain, fT  f measurement  | h21 |
(Speed performance)
with,

• fmax - frequency @ unit power gain, f Max  f measurement  Gmax

(Power gain capabilities)
with, G 
| s21 |
max 
. K  K 1
| s12 |
2
 K
1 | s11 |2  | s22 |2  |  |2
with
2 | s12 .s21 |

• Fmin - minimum noise figure, rn

(Noise performance) F  Fmin  | Ysource  Yoptnoise |2
gs
or,
3
 High frequency device performance is measured at high frequencies!
EE4605 Integrated Circuits and Systems for Wireless Applications

High frequency device characterization

On wafer reference planes
co-planar co-planar
“SOURCE”
probe [S] “LOAD”
probe
G G

S S

G on wafer G
transistor
50 environment with contact 50 environment
pads

4
EE4605 Integrated Circuits and Systems for Wireless Applications

History,
Silicon Technology versus Time
fT (GHz)

The high-frequency performance of silicon transistors is compatible with

microwave applications since the mid 90’s
5
EE4605 Integrated Circuits and Systems for Wireless Applications

FET Device performance

“Today”

Sweet spot for analogue CMOS performance (ft,& fmax ~ Lgate= 22 nm) 6
EE4605 Integrated Circuits and Systems for Wireless Applications

BJT Device performance

“Today”

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EE4605 Integrated Circuits and Systems for Wireless Applications

Silicon device candidates for

microwave applications
g
e
c b s d

Si or SiGe HBT Si NMOS

+ Low static power
+ High fT, fMax (100-300 GHz) (no DC current gate)
+ Higher gm for same bias
+ Small
+ Breakdown Voltage
+ 1/f noise + High fT, fMax (80-200 GHz)
+ Output imp. (Early voltage) + High-Speed Switch
-/+ linearity? + Device yield
- Base resistance + /- linearity ???
- input current (noise)
- Breakdown Voltage
- Device yield
- 1/f noise
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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor, Basics

Base needs to be thin to

keep recombination low

Band diagram
Cross section simplified bipolar NPN at
transistor equilibrium

By controlling a small base

Band diagram
current the much larger collector NPN at
current can be controlled! forward mode,
showing
(Pictures taken from Wikipedia) electron
injection from
symbols emitter to
Bands Hetero junction base and their
bipolar transistor with the overshoot into
barriers indicated for the the collector
holes and electrons, as
well the grading in the
9
base to assist electron
npn pnp transport
EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor, Basics

• Current gain needs to be large Boosted by in SiGe BJTs
Vbe Vbe
Vce
I c  I se VT
or I c  I s e (1 
VT
) 2
Dn nib N e Lpe
Ib 
Ic
VA
with  2
Where;
 D n N Wb F
p ie b
• VT is the thermal voltage k T / q (~ 26 mV at 300 K ≈ room temperature).
• Vbe is the base–emitter voltage
• Vce is the collector–emitter voltage qDn nib 2 Ae
• Is is the saturation current (on the order of 10−15 to 10−12 A) Is 
N bWb
• VA is the Early voltage
• Dn (/Dp) are the diffusion constant for electrons (/ holes) in the p-type base (n-type emitter)
• q is the electron charge
• Wb is the base width (thickness)
• Ae is the active emitter area
• nib (/ nie) are the intrinsic carrier concentration in the base( / emitter)
• Ne (/Nb) are the doping levels in the emitter and base respectively
• Lpe is the diffusion length of the holes in the emitter (NPN)
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EE4605 Integrated Circuits and Systems for Wireless Applications

BJT Output Characteristic

Idealized bipolar output characteristic, only Early effect (Ebers-Moll like)

no avalanche, no Kirk (quasi-saturation) effect,
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EE4605 Integrated Circuits and Systems for Wireless Applications

Hetero Bipolar transistor: SiGe

A SiGe transistor (NPN)
The addition of Germanium to the
dope base yields to a locally smaller
concentration (&graded) bandgap improving the
e inherent current gain significantly.
This allows the use of a higher
n+ Ge profile
base doping.
b p
When graded
Highly doped base
Advantages:
x • lower base resistance
n Selective implanted
collector doping • higher fT
• higher fMax
• higher Early voltage
n+ • improved temperature
dependency of 
c
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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor:
Modern device structure
Cross section A SiGe transistor (NPN)
Typical doping profile
dope
concentration
e
n+ Ge profile
b p
When graded
Highly doped base

x
n Selective implanted
collector doping

n+

c
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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor, Basics

Designer controls planar layout (mask) and bias conditions
 Mask sets emitter width (typically the most narrow one), emitter length,
number of fingers and contacts. Thus controlling BJT device size with related
series resistances and shunt capacitances

Technology determines vertical structure BJT

 sets current gain, sheet resistances, delay times (device speed), depletion
capacitance per unit area and breakdown

Depleted
Regions
(for a given bias)
Electrons need time to travel
from emitter to collector (NPN)
Lowly doped
Collector to handle
Applied collector voltage
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EE4605 Integrated Circuits and Systems for Wireless Applications

Johnson’s Figure of Merit

Johnson's figure of merit, suitability of a semiconductor material for high
frequency power transistor applications.
 It is the product of the charge carrier saturation velocity in the material
and the electric breakdown field (under same conditions) = Constant
• So, for practical device speed is exchanged for breakdown voltage
(also applicable to FETs)

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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar transistor:
Today fT’s over 100 GHz
Performance overkill? fT
Exchange:
speed for power dissipation Si/SiGe
device
SiGe HBTs require: desired
device
1
I c  I c _ Si speed
Si BJT
3
for equivalently dimensioned
technology
Silicon technologies
Ibias Ic
for same speed 16
EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar transistor: Modeling

The hybrid p model (RF; hand calculations only)
Ibb’ Qb’c
b b’ c
This simple model describes only the
most dominant effects.
Ib
It is only to some extend (f< fT/50) Qb’e
Cs
suitable for circuit simulation Ic

It is very important in the s

e
understanding and analysis of
circuit concepts! Large signal schematic

The small signal equivalent circuit is found by taking the derivatives of the
main functions at the bias point
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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar transistor: Modeling

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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar transistor: Modeling

The small signal hybrid-p circuit
Rb

Rc

Re
•All small-signal parameters follow from the main functions and are therefore
bias- dependent!
•  and tF are defined by the vertical transistor structure and, in first order
approximation, independent of bias and scale (active emitter area)
•The ohmic series resistance Rb, Rc and Re are inverse proportional with the
device scale (active emitter area), Rb is typically also bias dependent
•The depletion capacitances cTE, cTC and cTS are proportional to the device scale
(active emitter area), Cbe, Cbc, and CS are also bias dependent especially Cbe 19
EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar transistor: Device scaling

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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor, Device Scaling

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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor,
the cut-off frequency fT
• The most commonly used Figure of Merit for the HF behavior of a
bipolar transistor is cut-off frequency fT. Which is defined as:
• The cut-off or transition frequency (fT) is the frequency for which the
magnitude of the AC current gain |h21| drops to unity for a transistor
in common emitter configuration with an AC-shorted collector.

Ic DC |h21| f -3dB
(dB) 
ic 6 dB/oct
|h21 |meas
ib
fT according 6 dB/oct slope

is f T levelling-off due
to zero in h21
0
Cb‘c/(Cb‘e+Cb‘c)
i f meas
f T = f@ ----c = 1 0.0 f (Hz)
ib
22
The parameter |h21| as function of frequency
EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor,
the cut-off frequency fT
• In terms of the hybrid p circuit, the two-port parameter |h21| is given by:
C b'c 
– jw -------- - + 1
i ge
h 21 = ---c- = ---------------------------------------------------
-
ib uc = 0 
jw ----- Cb'e + Cb'c  + 1
ge
• Substitution of |h21|=1, assuming a large  and wCb‘c / ge << 1, yields the
commonly used equation:
ge 1
f T = ------------------------------------
- = ----------------------------------------------
-
2p Cb'e + Cb'c   c TE + c TC
2p t0 + -----------------------
ge
• Note this implies a single-pole device. The neglect of the zero
(wCb‘c / ge ) in the current gain will affect the value found for the cut-off
frequency, since the leveling-off in fT is now ignored.

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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor,
2.5e+10
the cut-off frequency fT
Vcb=0V
Cje Cjb Vcb=2V
fT (Hz) t T  t F + ------
- + -------- Vcb=4V
gm gm
2e+10

1.5e+10
Decrease in fT due to
1-
fT  ---- Decrease in fT due to
drop in gm tF high current effects:
1e+10
- Kirk effect
- Quasi-saturation
- high injection
5e+09 - parasitic series
resitances

0
1e-05 0.0001 0.001 0.01
Ic (A)

Plot of fT versus Ic for a minimum geometry BJT in a conventional double

poly technology

• Information on device speed as function of bias current is obtained by

plotting the fT versus bias. The fT is found by extrapolation using: FT = FME A S H21
ME A S
(which assumes a one pole device).
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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor,
the cut-off frequency fT
Dependency of bias current and emitter length
• The fT is bias (ge) dependent. It increases with Ic up to the point where quasi-
saturation, high injection in the base, or current crowding sets in. These effects lead
to an increase in the transit time and storage charge, and thus to a decrease of the fT,
consequently, the fT(Ic) characteristic has a maximum of fTmax.

• The maximum cut-off frequency fTmax (which occurs at Ic max) is in first order
approximation independent of the emitter length; Since t0 is independent of Le and
both ge max and (cTE+cTC) are linearly proportional to Le.
g e ma x
fTma x = ------------------------------------------------------------------
2p  c TE + c TC  + t0 gemax 
Discussion
• The fT as Figure of Merit is simple but represents a non-realistic circuit configuration
(short-circuited output and the use of a high ohmic current source as input).

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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor, fMax

The maximum frequency of oscillation fmax
• The capability to amplify power at high frequencies is an important measure. However the
transistor may oscillate when in- and output terminations consistent with maximum power gain
conditions are placed (Conjugate match at input and output). The maximization of power gain for a
given device should therefore take place within the constraints that ensure stable operation.
However, for a qualitative comparison of individual devices, the capability of power amplification is
more interesting than the realization of the actual circuit itself. For this reason designers use
different definitions of high-frequency power gain

• fMax is the frequency where the magnitude of the power gain of a transistor becomes unity. (This is
in principle, the highest frequency at which a transistor can oscillate)

• In terms of the hybrid p circuit, an approximation can be found in the following formulation:

fT
fma x = ---------------------
8prb Cb'c
• It should be noted that this expression is not generally valid but is only valid for a limited range of
values of rb and Cbc (e.g. if the base resistance rb goes to zero, fMax becomes infinite). An
alternative method is the extrapolation of the maximum unilateral power gain. The disadvantage of
this method is that it can lead to an over-estimation of the device properties by the fact that s12 is
set to zero. The most objective method is to shift up in frequency up to the point where the device
under test has become unconditionally stable, after which fMax can be found by the extrapolation of
GAmax
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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor, fMax

2e+10 2e+ 10
f meas = 1.5 GHz
fmax fmax fMax (V cb = 0V) acc. C)
fT (Hz) (K<1) fT(Hz)
(Hz) fMax (V cb = 1V) acc. C)
(Hz) GTUMax fMax
fMax
(V cb = 3V)
(V cb =0V)
acc.
ac c.
C)
A)
1.5e+10 1.5e+ 10 fMax (V cb =1V) ac c. A)
fMax (V cb =3V) ac c. A)
GAMax
1e+10 1e+ 10
Hybrid p
fMax (Vcb=0V) acc. A) Hybrid p
5e+09 fMax (Vcb=1V) acc. A) 5e+ 09
fMax (Vcb=3V) acc. A)
fMax (Vcb=0V) acc. B)
fmeas = 5 GHz
fMax (Vcb=1V) acc. B) (K>1)
fMax (Vcb=3V) acc. B)
0 0
0.0001 0.001 0.01 0.0001 0.001 0.01
I c (A) I c (A)

• fMax as function of the DC collector current for the DIMES03 transistor

using: A) hybrid p approximation B) unilateral power gain definition GTumax
when K<1 (at 1.5 GHz) and C) max. power gain GAmax when K>1 (at 5 GHz)

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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor, fMax

Measurement of the fMax
• By using similar calibration and de-embedding techniques as for the fT measurement,
the unilateral power gain can be calculated from the s-parameters:

f Max = fmeas GTmax

• Again a single-pole device is assumed.

Discussion
• The advantage of fMax above fT is the additional information about the base
resistance. This base resistance is a very important parameter in circuit design with
respect to speed and noise.

• The frequency fMax however is most useful in narrow-band design since its definition
assumes that the feedback of base-collector capacitance can be compensated. This
is in general a difficult task and can only be realized in a relative narrow frequency
band, which yields the conclusion that this Figure of Merit is not suitable for wide-
band design.

• The dependency of the bias current and the emitter length will be the same as that of
the cut off frequency fT. Note that the maximum in fMax as function of Ic can shift away
from the maximum in fT.
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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor, Noise

• The noise figure of a linear two-port as function of the source
admittance can be represented by:
Rn
F = F min + ------   Gopt – Gg  2 +  Bopt – BG 2 
• In which:
Gg
Matching dependent term
• Yg is the generator admittance, given by: Y g = Gg + jB g

• Yopt is the optimum noise match, given by: Yopt = G opt + jBopt

• Fmin is the lowest achievable noise figure (F = Fmin when Yopt=Yg).

• Rn is the “noise resistance”:

(gives the sensitivity of the noise figure F to the source admittance.

• Note that Fmin is a narrowband figure of merit

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EE4605 Integrated Circuits and Systems for Wireless Applications

Bipolar Transistor, Noise

For an Ideal bipolar transistor (no base resistance, no feedback capacitance)
we can write (see chapter 4):

In first order approx. Fmin

does not depend on the
device scaling (Le) while
Yopt is proportional and
Rn inverse proportional
30
with the emitter length
EE4605 Integrated Circuits and Systems for Wireless Applications

Device scaling
for optimum speed & noise
device area
set to 1

ADS input, see ADS examples

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EE4605 Integrated Circuits and Systems for Wireless Applications

Device scaling
for optimum speed & noise
General approach:
• Plot fT or GMax, Fmin and Gopt as function of bias current for the design
frequency. Make a compromise for the required gain, noise and impedance
level with respect to the biasing level. 2.0E10 4.5

40 1.0 4.0

1.5E10 3.5
0.8 3.0
30

NFmin
StabFact1
MaxGain1

fT
1.0E10 2.5
0.6
Sopt

20 fTminnoise 2.0

0.4 5.0E9 1.5

minnoise 1.0
10
0.2
0.0 0.5
1E-6 1E-5 1E-4 1E-3 6E-3
0 0.0
0.6 0.7 0.8 0.9 Icol.i
freq (1.000GHz to 1.000GHz) minnoise fTminnoise
vbe Icol.i=2.009E-4 Icol.i=2.009E-4
vbe=0.757500 vbe=0.757500
plot_vs(NFmin, Icol.i)=0.779 plot_vs(fT, Icol.i)=5.380E9

• Note that Fmin is indeed a weak function of Ic, while the gain is strongly
dependent on Ic 32
EE4605 Integrated Circuits and Systems for Wireless Applications

Device scaling
for optimum speed & noise
Area=1um2
Area=10um2
Area=1um2

device_characterization10um..NFmin

S(1,1)
Sopt
2.0E10 5

4
1.5E10

NFmin
freq (1.000GHz to 1.000GHz)
fT10
fT

1.0E10
2

5.0E9 Area=10um2

S(1,1)
Sopt
1

0.0 0
1E-6 1E-5 1E-4 1E-3 1E-2 6E-2
freq (1.000GHz to 1.000GHz)
Icol.i
• In first order approximation the ft, gain and noise do not change with the scale of the
device, (while keeping the current density constant). However, the impedance levels and
33
noise match of the device at the in- and output are proportional to the scale of the device
EE4605 Integrated Circuits and Systems for Wireless Applications

Save Operating Conditions Peak fT

With BJT devices 1.5E11 4.0
3.5
• When working with active devices make (VCE=1V)
Low noise
3.0
operation
sure that your device has the proper 1.0E11
2.5

NFmin
scaling (can it deliver / provide the

ft
2.0
current or power you need) Is it not 5.0E10
1.5

biased beyond the current density for 1.0

maximum fT? 0.5

0.0 0.0
• When designing for low noise are you 1E-4 1E-3 1E-2 1E-1
operating it at not at too high current Icol.i
densities? (Note that a too low current 100.0

density will result in a low gain) 87.5

Kirk Effect
• When designing for high speed is your 75.0 (Soft saturation)
device biased close to its peak fT current 62.5

density and not beyond? Icol.i, mA

50.0
Avalanche
37.5 (breakdown)
• Is the device not biased close to 25.0

breakdown (avalanche effects)? 12.5

 Plot output characteristic! 0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0
• Check if the device is not driven into vce
(soft) saturation / breakdown in large (Point were the peak fT occurs (VCE=1)) 34
signal operation
EE4605 Integrated Circuits and Systems for Wireless Applications

EXAMPLE, SiGe class-B amplifier 0.10

ts(device_load_line..HB.Icol.i)
0.08

0.06

Icol.i, A
0.04

0.02 Low Vce

0.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0

vce
ts(device_load_line..HB.vce)

0.10

ts(device_load_line..HB.Icol.i)
Transistor 0.08

overdriven 0.06

Icol.i, A
0.04

0.02

0.00
0.10 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Load line optimized for
ts(device_load_line..HB.Icol.i)

vce
0.08 ts(device_load_line..HB.vce)
maximum output power
0.10
0.06
Device driven almost in
Icol.i, A

ts(device_load_line..HB.Icol.i)
0.08
0.04 breakdown and hard
saturation 0.06

Icol.i, A
0.02
0.04
Higher Rload
0.00
0.02
(4x)
0.0 0.5 1.0 1.5 2.0 2.5 3.0

vce 0.00 35
ts(device_load_line..HB.vce) 0.0 0.5 1.0 1.5 2.0 2.5 3.0

vce
ts(device_load_line..HB.vce)
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF

CMOS dominates the semiconductor market, but

compared to HBJT devices it requires more work to
obtain good Analogue performance at RF!

Trend,  Move analogue functions to the digital

domain, where we benefit from technology scaling!
(Course “Digital RF”

Here we will mainly focus on the analogue CMOS

considerations 36
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF
(Long channel) device considerations
W

Drain current in the linear (Triode Region, Vds<Vsat)

W  Vds 2 
I D  nCox (Vgs  Vt )Vds  
L  2 
In this region the device acts like a voltage-controlled resistor, which
linearly depends on Vds as long Vds<Vsat
For background information on CMOS devices please consider: Thomas H. Lee,
37
The design of CMOS Radio-Frequency integrated circuits
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF
• Drain current in saturation region (Long-Channel)
When Vds is high so that the inversion layer does not extend form Source to
Drain, the channel is “pinched off”, In this mode the channel charge increases
with Vds causing the current to remain constant. The formulation for this
operation is obtained by substituting Vds with Vdsat in our previous expression

W  Vdsat 2  W
I D  nCox 
 gs t dsat
(V V )V     C
n ox (Vgs  Vt ) 2

L  2  2 L
Using: Vdsat=Vgs-Vt
This results in a square law dependence on the gate-source voltage and is
independent on the drain voltage. The trans-conductance for this operation
mode is found by differentiating the expression for the drain current
W
gm  nCox (Vgs  Vt )
L W
Which can also be expressed as:
g m  2  C
n ox ID
L 38
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF
Capacitive parasitics

Cjsb = source-to-bulk junction capacitance

Cjdb = drain-to-bulk junction capacitance
CGC = gate-to-channel capacitance
Cov = overlap capacitances
CCB = channel-to-bulk (junction) capacitance

Depending on the operation (bias) mode, which influences the

channel of the CMOS device these capacitances translate in different
terminal capacitances Cgs, Cgd, Csb,Cdb 39
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF
Cgd
gate drain
+
Cgs V
- c
ri
gmVc rds Cds

source
Simplified equivalent circuit of a CMOS device

The cut-off frequency fT

The cut-off frequency fT can be found by investigating the point where

id gm gm
 1 yielding: wT 
iin w (Cgs  Cgd ) (C gs  C gd )

40
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF
The maximum frequency of oscillation fMax
For the calculation of fMax we use the following simplifying assumptions
•Input impedance calculated with AC shorted drain
•Output impedance includes the feedback from drain to gate through Cgd
iin 2 rg
Power delivered to the input of a FET: Pin 
2
(rg is the gate resistance, the only dissipative component at the input)
id wT
The magnitude of the short-circuit output current gain is given by: 
iin w
It can be shown that the resistive part of the output conductance is roughly:

Cgd
gout  gm  wT Cgd
Cgd  Cgs
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EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF
fMax
Assume a conjugate match for maximizing the power transfer, we can
write: Output current output
current
Output resistance
1  wT
2
1 1
  i  
2 w 2  (wT Cgd ) wT
in
PL
 
PS  iin 2 rg  w 2 8rg Cgd RL
2 
 2  Only half the current
Which has a value of unity at the frequency given by: leaves the device

wT
wmax 
8rg Cgd
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EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF
• The drain current in Short-channel devices
In short devices the electric field approaches 106V/m resulting a saturation of
the electrons speed to 105m/s. As a result of this saturation the drain current
becomes less dependent on the actual drain voltage. To included these effects
in the formulation of ID we start with the long channel formulation
W
I D  nCox (Vgs  Vt )2
2L
W
Which may be rewritten as: I D  nCox (Vgs  Vt )Vdsat ,l
2L
Where Vdsat is denoted Vdsat,l and is equal to: (Vgs  Vt )
The drain current saturates when the velocity saturation does occur and this
saturation starts at smaller voltages as the device gets shorter, consequently
Vdsat will diminish with channel length. In fact Vdsat is determined by the
minimum of (Vgs-Vt) and L.Esat consequently Vdsat can be expressed as,
(Vgs  Vt )( L.Esat )
Vdsat  [(Vgs  Vt ) || ( L.Esat )] 
(Vgs  Vt )  L.Esat 43
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF
• The drain current in Short-channel devices
W
So that, I D  nCox (Vgs  Vt )[(Vgs  Vt ) || ( L.Esat )]
2L
From this it can be concluded that the presents of short channel effects
depend on the ratio of (Vgs-Vt)/L to Esat. If this ratio is small then the device
still behaves as a long device. When the device shortens less (Vgs-Vt) is
needed to for the onset of Id saturation.

For values of (Vgs-Vt)/L that are high compared to Esat, ID approximates the
following limit
W
I D  nCox (Vgs  Vt ) Esat
2
Note that the drain current is no longer a direct function of channel length,
also the ID(VGs) dependence has become much more linear, consequently:
I D nCoxW .Esat is a constant and a therefore a measure for a
gm  
Vgs 2 technology: e.g. 300mS per mm 44
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF
• Scaling of short channel devices
I D nCoxW .Esat
Using the fact that: gm  
Vgs 2
2
C
and assuming that Cgs dominates, which we can approximate by: gs  WLCox
3
Taking the ration of gm to Cgs yields:
1
g m 2 ( nCox )W .Esat 3 n Esat vs 1
wT     
Cgs 2
WLCox 4 L L t
3
We observe for short channel devices that wT depends on 1/L rather then
1/L2. In addition we see that in the saturation regime there is no strong
dependence on the bias. This will make the device behavior quite linear
45
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS for RF

Cgd
gate drain
Cgs
Cdb
gmvgs gmvbs

Csb

bulk source

MOSFET model including back-gate effect (resistive elements not shown)

46
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS, Gate Length Scaling

increases
47
Figure from Alvin J. Joseph et al, Proc. of the IEEE, vol. 93, no. 9 Sept. 2005
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS, Gate Length Scaling

Improved device performance by “lateral” scaling 48

Table from Alvin J. Joseph et al, Proc. of the IEEE, vol. 93, no. 9 Sept. 2005
EE4605 Integrated Circuits and Systems for Wireless Applications

Moores Law

Moores law is still going strong but mainly for digital!

49
EE4605 Integrated Circuits and Systems for Wireless Applications

IC interconnect

• Layer stack (older) CPU processors

50
EE4605 Integrated Circuits and Systems for Wireless Applications

High Frequency Noise in

MOSFETS
• Since FETs are basically voltage controlled resistors the thermal fluctuations
of the channel charge results in current noise sources in the drain and gate
rg Cgd
These noise current sources are
Cgs partial correlated with each other
ing2 gmvgs ind2 since they share a common origin
posses a spectral power density
source given by:
Equivalent noise circuit CMOS device

With a correlation
between them given by :

51
EE4605 Integrated Circuits and Systems for Wireless Applications

The noise parameters

Using the definition of the noise current sources one can derive the expression
for the noise parameters
In which:
gd0 is the output drain conductance
gg is the real part of gate-to-source  w 2C gs 2 
 g g  
admittance  5 g d0 

g bias dependent constant ~2/3

 bias dependent constant ~4/3
ζ= constant =0.2
c correlation factor = j0.395

With these parameters the noise

Figure can be calculated.

52
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS Noise parameters and scaling

The shortest gate length (L) results in the
highest fT thus the lowest noise. Since the fT
and the constants g,,z, do not depend on the
device width (W) and gm gd0 and Cgs are
linear proportional to (W) we are able to
make conclusions on how scaling influence
the noise parameters, consequently:

Which implies that a large device width

(W) reduces Rn offering the best chance
on lowering the noise figure
53
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS Gate Width Scaling,

CMOS Technology, Lgate = 0.25m, fTmax=~35GHz, Fmin~0.4dB
Wgate = 10 m
3.5E10 25

3.0E10
20
The impedance levels 2.5E10

required at the input of 2.0E10

15

NFmin
nf(2)
CMOS devices in order
S(2,2)
S(1,1)

ft
Sopt
m1
1.5E10
ID.i=9.950E-4 10
to obtain a noise or 1.0E10
m1=0.375
vgate=1.060000
power match are very 5.0E9
5

high compared to the m1

0.0 0
bipolar device. Up

1.00E-4

1.00E-3

0.01

0.10
0.12
freq (2.000GHz to 2.000GHz)

scaling the device

Wgate = 100 m 3.5E10 ID.i 25
width (W) works but m1
3.0E10
directly increases the ID.i=0.010
m1=0.375
20

vgate=1.060000
power consumption. 2.5E10

15
2.0E10

NFmin
nf(2)
Note that again FTmax

ft
S(1,1)
S(2,2)
Sopt

1.5E10
10
and Fmin do not change
1.0E10

on the gate Width 5

5.0E9
scaling. m1
0.0 0
1.00E-4

1.00E-3

0.01

0.10
0.12
freq (2.000GHz to 2.000GHz) 54
ID.i
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS versus SiGe

CMOS gain comes with high
current consumption and requires
the availability of high
performance passive components

0.2 m BJT

0.18 m CMOS

55
Invited paper J. Long, proceedings IEEE, Sept 5 2005
EE4605 Integrated Circuits and Systems for Wireless Applications

Generating RF Power
at High Frequencies
Next to fmax also the achievable output power with a given
technology is of importance, when we assume class-B
operation for the active device the output power is,

l/4 Vdd
Zo
Vout 2
Pout  Output
2 Rout R
Vout out
match RL

• Being able to handle a high Vout is a big advantage!

 Less sensitive for series parasitics, e.g. series resistance due to
the limited sheet conductance provided by the metal stack of an
IC technology or bondwire ground inductance.
 Device speed and breakdown are two conflicting requirements! 56
EE4605 Integrated Circuits and Systems for Wireless Applications

Device Speed vs. Breakdown

Power handling active device depends on
material parameters and device design

• Device speed depends mostly on: mobility and electron velocity and
dimensions
• Power handling depends mostly on: bandgap, thermal conductivity and
breakdown Electric field and device dimensions
57
EE4605 Integrated Circuits and Systems for Wireless Applications

FETs, Speed vs. Breakdown

Non power optimized CMOS
Note the significant parasitics
(e.g. feedback capacitance as
added by the metal connections)

Improvements over standard

CMOS for power handling
• Grounded source
• Extended drain (lowly doped
to handle the high voltage)
• WSI shield (shunt any
capacitive feedback from the
output to ground)
58
Structure of a 50V RF LDMOS Device Electrons will need time to travel (low fT)
EE4605 Integrated Circuits and Systems for Wireless Applications

Device Speed vs. Breakdown

59
EE4605 Integrated Circuits and Systems for Wireless Applications

Current issues:
Time to market & Cost, Cost, Cost
Most RF products are first
implemented in BiCMOS and
at a later stage transferred to
CMOS to achieve lower costs
in volume production.
However, performance and DC
power consumption might
influence that process.

Price performance comparison

between BiCMOS and CMOS
(advanced nodes are
projected). After Alvin. J.
Joseph et al., invited paper
proc. IEEE, Sept. 2005

60
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS versus SiGe, Conclusions

• CMOS the only choice for digital base Is Moores law coming to its end?
band processing

• Slightly lower noise figure than bipolar

for narrow band applications (no
base shot noise source)
• Low third-order intermodulation
distortion
• Difficult input matching due to large
|Gopt noise| required reflection for
noise match
Gopt noise
High-Q
matching
network
Gin
• In general lower breakdown voltage
than bipolar for comparable fT
 less suited for PA applications 61
EE4605 Integrated Circuits and Systems for Wireless Applications

CMOS versus SiGe, Conclusions

• Bipolar are most suitable for analogue low power applications
– Higher gm for a given current
– Higher output impedance (Early voltage)
=> Higher gain

• CMOS for low power digital due to complementary logic

- Switching speed & capacitive load determine the
power consumption

62
EE4605 Integrated Circuits and Systems for Wireless Applications

Recommended reading
• Thomas H. Lee, The design of CMOS Radio-
Frequency Integrated Circuits

• Alvin J. Joseph et al. “Status and Direction of

Communication Technologies-SiGe BiCMOS
and RFCMOS, Proc. of the IEEE, vol. 93, no. 9
Sept. 2005

• John R. Long SiGe Radio Frequency ICs for

Low-Power Portable Communications, Proc. of
the IEEE, vol. 93 no. 9 Sept. 2005.

63