Transcede® 2xxx

Wireless Base Station System on Chip

Data Sheet

842xx-DSH-001-A
September, 2013
Contents

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.1 Transcede 2xxx Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.2 Transcede 2xxx Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.3 Transcede 2xxx Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4 Device Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5 Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.6 Transcede 2xxx System Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.1 CEVA Group Slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.2 CEVA Group Partition Slaves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.3 SYS Partition Slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.4 Radio Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.6.5 System Masters/Slaves Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2 Device Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.1 Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.2 JTAG Debug Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.3 Bootstraps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3 Pinout and Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1 Transcede 2xxx Ball Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.2 Summary of Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.3 Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.4 Unused Interface Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.4.1 Unused TDM Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.4.2 Unused SPI Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
3.4.3 Unused Radio Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.4.4 Unused SerDes Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.4.5 Unused RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
3.4.6 Unused TSU Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.4.7 Unused RPDIF CMOS Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
3.4.8 Unused RPDIF LVDS Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3.4.9 Unused USB Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
3.4.10 Unused USIM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.4.11 Unused eFuse Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

842xx-DSH-001-A Mindspeed Technologies® 2

Mindspeed Proprietary and Confidential
Contents

3.4.12 Unused Trace Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4 DDR3 Memory Sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.2 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
4.3 Transcede 2xxx DDR3 SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.4 DDR3 SDRAM Device Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5 SerDes for CPRI, PCIe or SGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.2 Supported Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6 Common Public Radio Interface (CPRI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.1.1 General Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.1.2 AxC Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.1.3 Control and Management (C&M) Channel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
6.2 CPRI System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
6.3 CPRI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.3.1 Feature List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
6.3.3 Template Based Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
6.3.3.1 TSL Entry Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
6.3.3.2 Template Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.3.3.3 Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.3.4 Cyclic Prefix Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
6.3.5 Synchronized DMA Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
6.3.5.1 Sync Mode in Downlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
6.3.5.2 Sync Mode in Uplink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
6.3.5.3 Data Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
6.3.5.4 MAP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
6.3.6 CPDMA Usage Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
7 Peripheral Component Interconnect Express (PCIe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.1 Feature list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.2 Channel AC Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
7.3 Transmitter Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
8 10/100/1G Ethernet Media Access Controller (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
8.2 Management Data Input/Output (MDIO) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
8.3 RGMII Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4 SGMII (SerDes) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.5 MAC Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8.6 MAC Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.7 IEEE 1588 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.8 Network Timing Generator (NTG) for 1588 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

842xx-DSH-001-A Mindspeed Technologies® 3

Mindspeed Proprietary and Confidential
Contents

9 Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

9.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
9.2 Expansion Bus Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
9.3 I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
9.3.1 External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
9.3.2 Slave AHB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
9.3.3 Configuration APB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
9.3.4 General Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
9.4 Block Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9.4.1 AHB Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.4.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9.4.2.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
9.4.2.2 ALE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
9.4.2.3 Strobe Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.4.2.4 NAND Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.5 External Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.6 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.8 Enable /Disable Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.9 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
9.10 Expansion Interface AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
10 Inter-IC Interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
10.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.2 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
10.3 I2C Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
11 Serial Peripheral Interface (SPI) and High Speed SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
11.1 Feature List—SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
11.2 Feature List—High Speed SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
11.3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
11.4 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
11.5 SPI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
11.6 High Speed SPI DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
12 Universal Asynchronous Receiver / Transmitter (UART) Interface . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.1 Feature List—UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
12.2 Feature List—HS-UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
12.3 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
13 General Purpose Input Output (GPIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
13.2 GPIO Muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
13.3 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
14 Time-Division Multiplexing (TDM) Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
14.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

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14.2 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

14.3 TDM Bus Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.4 TDM Interface AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
14.5 TDM Input-to-Output Loopback Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
14.6 Network Timing Generator (NTG) for TDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
15 Universal Serial Bus (USB) Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
15.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
16 Universal Subscriber Identity Module (USIM) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
16.1 Feature List—Electrical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
16.2 Feature List—Functional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
16.3 Smart Card Session Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
16.3.1 Smart Card Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
16.3.2 Automatic Operating Voltage Class Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
16.3.3 Activation of Contacts and Cold Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
16.3.4 Answer to Reset (ATR) Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
16.3.5 Execution of Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
16.3.6 Deactivation of Contacts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
16.3.7 Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
17 Radio Parallel Digital Interface (RPDIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
17.1 Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
17.2 RPDIF Control Plane Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
17.3 RPDIF Data Plane Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
17.4 RPDIF Functional Muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
17.5 RPDIF Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
17.5.1 RPDIF CMOS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
17.5.2 RPFIF LVDS Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
18 Joint Test Action Group (JTAG) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
18.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
18.2 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
19 ARM Subsystem (with Dual-ARM Cores) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
19.1 A9 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
19.2 L2 Feature List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
19.3 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
19.4 256KB System Internal RAM (IRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
19.4.1 Feature List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
19.4.2 Implementation Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
19.5 TrustZone Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
20 Ceva-XC323 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
20.1 Ceva-XC323 DSP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
20.2 768KB CEVA Internal RAM (CRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
20.2.1 Feature List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
20.2.2 Implementation Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164

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21 Mindspeed Advanced Processor (MAP) Array / FFT Accelerator. . . . . . . . . . . . . . . . . . . . . . . . . . . 166

21.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
21.2 MAP Processor Array Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
21.3 MAP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
21.4 MAP Processor Array APB Bus Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
21.5 DMA Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
21.6 MAP Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
21.6.1 Feature List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
21.6.2 MAP DMA and FFT_MC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
21.6.3 MAP Master Controller (MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
21.6.4 DMA Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
21.6.5 Frame and Buffer Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
22 Forward Error Correction (FEC) Hardware Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
22.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
22.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
22.3 Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
22.4 FEC Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
22.4.1 Feature List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
22.4.2 DMA Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
22.4.3 DMA Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
22.4.4 Frame and Buffer Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
22.4.5 DMA Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
22.4.5.1 Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
22.4.5.2 DMA Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
23 Security Protocol Accelerator (SPA) and Security Encryption Engine . . . . . . . . . . . . . . . . . . . . . . . 187
23.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
23.2 IPSec Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
23.3 SPAcc-PDU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
23.4 True Random Number Generator (TRNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
23.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
23.4.2 TRNG Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
23.4.2.1 Random Noise Seed Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
23.4.2.2 Whitening Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
23.4.3 TRNG Usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
24 Chip Rate Processor (CRP) Correlator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
24.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
24.2 RACH Preamble Detector (RPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
24.3 Pilot Search Correlator (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
24.4 Correlator for Control Channels (COR-C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
24.5 Correlator for Traffic Channels (COR-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
24.6 Memory to Memory DMA Controller for CRP (MDMA-CRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
24.6.1 Feature List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
24.6.2 DMA Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
24.6.3 DMA Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

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24.6.4 Frame and Buffer Descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

24.6.5 DMA Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
24.6.5.1 Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
24.6.5.2 DMA Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
25 Bit Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
25.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
25.2 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
26 Memory to Memory DMA (MDMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
26.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
26.2 DMA Data Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
26.3 Frame and Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
26.4 DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
26.4.1 Design Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
26.4.2 DMA Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
27 Internal Boot ROM (IBR) Implementing Secure Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
27.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
27.2 IBR Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
27.3 Transcede 2xxx Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
27.4 Clock and Frequency Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
27.5 IRAM Memory Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
27.6 Boot Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
27.7 Transcede 2xxx Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
27.8 Extended Boot Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
27.9 Transcede 2xxx eFuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
27.9.1 eFuse Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
27.9.2 eFuse Sense Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
27.9.3 eFuse Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
28 Interrupts, Timers, Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
28.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
28.1.1 CevaXC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
28.1.2 Cortex-A9 MPCore (Dual ARM) Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
28.2 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
28.2.1 Feature List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
28.2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
28.2.3 Radio Frame Synchronization Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
28.2.3.1 Feature List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
28.2.3.2 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
28.2.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
28.2.3.4 IQ Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
28.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
28.3.1 Clocking Scheme Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
28.3.2 Reference Clock Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
28.3.3 System Clock Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
28.3.4 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241

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28.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

28.4.1 Global Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
28.4.2 Block Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
28.4.3 Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
28.4.4 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
29 Electrical and Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
29.1 Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
29.2 Power Turn-On Sequence and Timing Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
29.3 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
29.3.1 Thermal Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
29.3.2 Package Thermal Design and Test Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
29.3.3 Product Thermal Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
30 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

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Figures

Figure 1-1 Transcede 2xxx Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 1-2 System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 3-1 Transcede 2xxx Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 4-1 Transcede 2xxx DDR3 SDRAM Interface Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 4-2 DDR3 SDRAM Device Interface Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 6-1 CPRI System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Figure 6-2 CPDMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Figure 6-3 CPDMA AxC - Control Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Figure 6-4 TSL Entry Format (8 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Figure 6-5 Template Format (128 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Figure 6-6 Descriptor Format (32 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Figure 6-7 Cyclic Prefix Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Figure 6-8 Synchronized DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Figure 6-9 Synchronous TX and RX MAP Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Figure 6-10 Symbols in CRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Figure 6-11 Symbols in DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Figure 8-1 MDIO Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Figure 8-2 RGMII Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Figure 8-3 Reference Data and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Figure 8-4 Driver Clock and Data Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Figure 9-1 Expansion Bus Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Figure 9-2 Normal Mode Timing Diagram (RDY_EN = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Figure 9-3 Normal Mode Timing Diagram (RDY_EN = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Figure 9-4 ALE Mode Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Figure 9-5 Strobe Mode Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Figure 9-6 NAND Command Latch Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Figure 9-7 NAND Address Latch Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Figure 9-8 NAND Data Latch Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Figure 9-9 Expansion Bus Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Figure 9-10 AC Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Figure 10-1 I2C Timing Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Figure 11-1 Hardware/Software Slave Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Figure 11-2 SPI Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Figure 13-1 GPIO Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

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Figures

Figure 14-1 Transmit Timing (FE = 1, CMSX = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Figure 14-2 Transmit Timing (FE = 0, CMSX = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Figure 14-3 Received Timing (FE = 1, CMSR = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Figure 14-4 Received Timing (FE = 0, CMSR = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Figure 14-5 Transmit Timing (FE = 1, CMSX = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Figure 14-6 Transmit Timing (FE = 0, CMSX = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Figure 14-7 Received Timing (FE = 1, CMSR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Figure 14-8 Received Timing (FE = 0, CMSR = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Figure 14-9 TDM Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Figure 14-10 TDM Loopback Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Figure 16-1 USIM Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Figure 16-2 Activation, Cold Reset and ATR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Figure 16-3 Deactivation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Figure 16-4 Warm Reset and ATR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Figure 17-1 SPI Control Word Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Figure 17-2 Interfacing with AD936x in Single Port Full Duplex Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Figure 17-3 Interfacing with AD936x in Dual Port Full Duplex - CMOS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
Figure 17-4 Interfacing with AD936x in LVDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Figure 17-5 Data Path 2T2R RX LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Figure 17-6 Data Path 2T2R TX LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Figure 17-7 Functional Muxing of RPDIF SPI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Figure 17-8 RPDIF CMOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Figure 17-9 RPDIF LVDS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Figure 19-1 ARM CA9 with CoreSight Debugging System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Figure 19-2 IRAM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Figure 19-3 IRAM Memory Bank Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
Figure 20-1 CRAM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Figure 20-2 CRAM Memory Bank Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Figure 21-1 MAP Processor Array Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
Figure 21-2 MAP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Figure 21-3 Memory Bank Structure of MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Figure 21-4 APB Bus Address Mapping For Each Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Figure 21-5 MAP DMA and FFT_MC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Figure 21-6 DMA Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Figure 22-1 FEC Downlink Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
Figure 22-2 FEC Uplink Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
Figure 22-3 Data Structure of Control Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
Figure 22-4 FEC DMA Data Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Figure 23-1 IPSec Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
Figure 23-2 SPAcc-PDU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Figure 23-3 SPAcc Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Figure 23-4 Random Noise Seed Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

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Figures

Figure 23-5 Seed/Whitener Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192

Figure 23-6 TRNG Signaling Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
Figure 24-1 Top Level Block Diagram of CRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Figure 24-2 RPD Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Figure 24-3 Top Level Diagram of PSC Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
Figure 24-4 Block Diagram of COR-C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Figure 24-5 Traffic Channel Despreader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
Figure 24-6 DMA Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Figure 25-1 Bit Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Figure 26-1 DMA Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
Figure 27-1 IRAM Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Figure 27-2 Boot Image Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
Figure 27-3 eFuse ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
Figure 27-4 eFuse Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
Figure 28-1 Individual Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
Figure 28-2 Timer Top-level Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Figure 28-3 Example Frame Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Figure 28-4 Radio Timers Top Level Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
Figure 28-5 Frame Sync Pulse Phase Shift Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
Figure 28-6 Timer Count Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
Figure 28-7 IQ Transfer Counter Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
Figure 28-8 Normal Case Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Figure 28-9 Overflow Case Timing Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
Figure 28-10 Overflow Case Timing Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
Figure 28-11 Clock Muxing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
Figure 28-12 Reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
Figure 29-1 Power Sequence for Normal IO Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
Figure 29-2 HFC-BGA Package Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Figure 29-3 Connecting Thermal Balls to Motherboard Ground Plane Using Thermal Vias . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Figure 29-4 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Figure 30-1 Transcede 2xxx Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

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Tables

Table 1-1 Transcede 2xxx Processor Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 1-2 Transcede 2xxx Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 1-3 CEVA Group Partition (0xF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 1-4 Ceva Group Partition (0xF3) – CRAM, FFT_TOP, CRP Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 1-5 SYS Partition Slaves (0xF4) – IRAM, FEC, DDR cfg, Semaphore Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 1-6 RAD Group – RPDIF, SGMII, PCIE, CPRI, CPDMA Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 1-7 System Partition - SPAcc, IPSec, RGMII, TDM, GPIO, UART, SPI, I2C Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 2-1 Transcede 2xxx Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 2-2 Bootstraps Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 3-1 Transcede 2xxx Pinout List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 3-2 DDR Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 3-3 MDIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 3-4 RGMII Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 3-5 Expansion Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 3-6 I2C Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 3-7 TDM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 3-8 SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 3-9 UART Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 3-10 GPIO Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 3-11 USIM Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 3-12 USB Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 3-13 RPDIF 0 (JESD207) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 3-14 RPDIF 1 (JESD207 LVDS) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 3-15 JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 3-16 SerDes0 for PCIe0 (4x) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 3-17 SerDes1 for CPRI or SGMII or PCIe Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 3-18 Test and Misc Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 3-19 Efuse Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 3-20 Radio Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 3-21 Thermal Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 3-22 Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 3-23 Unused TDM Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 3-24 Unused SPI Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 3-25 Unused Radio Timer Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

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Tables

Table 3-26 Unused SerDes Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 3-27 Unused RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 3-28 Unused TSU Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 3-29 Unused RPDIF CMOS Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 3-30 Unused RPDIF LVDS Bus Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 3-31 Unused USB Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 3-32 Unused USIM Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 3-33 Unused eFuse Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 4-1 DDR3 Access Window Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 4-2 Transcede 2xxx DDR3 SDRAM Interface AC Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Table 4-3 DDR3 SDRAM Device Interface AC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 7-1 2.5 and 5.0 Gbps PCIe Gen2 Transmitter Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 7-2 5.0 Gbps Limits for Common Refclk Rx Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 7-3 5.0 Gbps Tolerancing limits for Data Clocked Rx Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 7-4 2.5 and 5.0 Gbps Receiver Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Table 8-1 MDIO Interface Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table 8-2 RGMII Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Table 8-3 Driver DC Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Table 8-4 Receiver DC Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Table 8-5 Driver AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Table 8-6 Receiver AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Table 8-7 Example of a Sync Frame in the 1588 Version 1 Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Table 8-8 Example of a Delay Request Frame in the 1588 Version 1 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Table 8-9 Example of a Sync Frame in the 1588 Version 2 (UDP/IPv4) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 8-10 Example of a Sync Frame in the 1588 Version 2 (UDP/IPv6) Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 8-11 Example of a Sync Frame in the 1588 Version 2 (Ethernet Multicast) Format . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 8-12 Example of a Pdelay_req Frame in the 1588 Version 2 (Ethernet Multicast) Format. . . . . . . . . . . . . . . . . . . . . . .102
Table 9-1 I/O Description of External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Table 9-2 I/O Description of Slave AHB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Table 9-3 I/O Description of APB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Table 9-4 I/O Description of General Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Table 9-5 Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 9-6 Normal Mode Signals List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 9-7 ALE Mode Signals List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table 9-8 Command Strobe Mode Signals List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 9-9 NAND Mode Signals List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 9-10 AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Table 10-1 I2C Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Table 11-1 AC Timing Parameters—LS SPI (SPI_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Table 11-2 AC Timing Parameters—HS SPI (SPI_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Table 13-1 GPIO Muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 13-2 AC Timing Parameters—GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

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Table 14-1 TDM Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 14-2 TDM Loopback Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Table 17-1 RPDIF Functional Muxing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Table 17-2 RPDIF CMOS Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Table 17-3 RPDIF LVDS Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Table 19-1 Cortex-A9 MPCore Private Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Table 19-2 CoreSight Interface Muxing: 16-bit Trace Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
Table 19-3 Address Map of CSDK Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Table 21-1 Inbound (Tx) Frame and Buffer Descriptors Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Table 21-2 Outbound (Rx) Frame and Buffer Descriptors Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Table 21-3 Inbound Frame Descriptors Changed by Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Table 21-4 Outbound Frame Descriptors Changed by Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Table 22-1 FEC DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
Table 22-2 MM_RDATA[128:0] Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180
Table 22-3 MM_WDATA[128:0] Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Table 22-4 Mem2Dma (or memory to I/O) Frame and Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Table 22-5 Dma2Mem (or from I/O to memory) Frame and Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
Table 22-6 Common, or 1, Frame and Buffer Descriptor for both Mem2Dma and Dma2Mem (FCOM) . . . . . . . . . . . . . . . . .184
Table 22-7 Mem2Dma Frame Descriptors Changed by Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Table 22-8 DMA2Mem Frame Descriptors Changed by Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Table 22-9 Common Frame Descriptors Changed by Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Table 24-1 MDMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Table 24-2 Mem2Dma (or memory to I/O) Frame and Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Table 24-3 Dma2Mem (or from I/O to memory) Frame and Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
Table 24-4 Common, or 1, Frame and Buffer Descriptor for both Mem2Dma and Dma2Mem (FCOM) . . . . . . . . . . . . . . . . .204
Table 24-5 Mem2Dma Frame Descriptors Changed by Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
Table 24-6 DMA2Mem Frame Descriptors Changed by Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
Table 24-7 Common Frame Descriptors Changed by Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
Table 26-1 Mem2Dma (or memory to I/O) Frame and Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Table 26-2 Dma2Mem (or from I/O to memory) Frame and Buffer Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Table 26-3 Common, or 1, Frame and Buffer Descriptor for Both Mem2Dma and Dma2Mem (FCOM) . . . . . . . . . . . . . . . . .212
Table 26-4 Mem2Dma Frame Descriptors Changed by Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Table 26-5 DMA2Mem Frame Descriptors Changed by Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Table 26-6 Common Frame Descriptors Changed by Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
Table 27-1 Extended Boot Option Bits – Clock Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
Table 27-2 Boot Image Header Fields Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
Table 27-3 Extended Boot Option Bits – SPI Address Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Table 27-4 Extended Boot Option Bits – SPI SC Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Table 27-5 Extended Boot Option Bits – Secure Boot Opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Table 28-1 Dual ARM External IRQS Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
Table 28-2 Registers Controlling Watchdog Timer (Base Address = 0xFE05_0000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
Table 28-3 Reference Clock Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

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Table 28-4 System Clock Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239

Table 28-5 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
Table 29-1 Power Supply Voltages and Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
Table 29-2 DDR3 Mode - DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245
Table 29-3 DC Electrical Specification for 3.3V tol and non-tol IO (VDD = 1.65V~3.60V, Vext = 3.0~3.6V, TA = -40 to 85 oC) . .
245
Table 29-4 DC Electrical Specification for 5V Tolerant IO (VDD = 3.0V~3.60V, Vext = 4.5~5.5V, TA = -40 to 85 oC). . . . . . .247
Table 29-5 DC Electrical Specification for LVDS Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Table 29-6 Electrical Specification for LVDS Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Table 29-7 Typical Pull-up, Pull-down Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Table 29-8 Thermal Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

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Preface

About this Document

The Transcede 2xxx Data Sheet describes the hardware-related features and requirements of Mindspeed's
Transcede® 2xxx Wireless Base Station System on Chip (“Transcede 2xxx” or “T2xxx”).
This document is organized as follows:
Chapter 1, Introduction—presents an overview of the Transcede 2xxx device capabilities, interfaces, hardware
features, and system memories.
Chapter 2, Device Configuration Options—describes the boot source selection and device configuration options.
Chapter 3, Pinout and Signal Summary—gives a summary of device signal tables and their descriptions.
Chapter 4, DDR3 Memory Sub-system—details the DDR3 SDRAM interface and DDR3 SDRAM controller.
Chapter 5, SerDes for CPRI, PCIe or SGMII—describes features of SerDes.
Chapter 6, Common Public Radio Interface (CPRI)—introduces the features and implementation details of CPRI
for Transcede 2120, Transcede 2150, and Transcede 2200.
Chapter 7, Peripheral Component Interconnect Express (PCIe)—introduces the features and implementation
details of PCI express.
Chapter 8, 10/100/1G Ethernet Media Access Controller (GMAC)—describes the Ethernet interface capabilities
and features.
Chapter 9, Expansion Bus Interface—introduces the features and implementation details of the expansion bus
interface.
Chapter 10, Inter-IC Interface (I2C)—introduces the features, functions, and timing of the I2C interface.
Chapter 11, Serial Peripheral Interface (SPI) and High Speed SPI—describes features, functions and timing of SPI
interface.
Chapter 12, Universal Asynchronous Receiver / Transmitter (UART) Interface—introduces the features and
implementation details of the Transcede 2xxx Universal Asynchronous Receiver / Transmitter (UART) module.
Chapter 13, General Purpose Input Output (GPIO)—provides features and implementation details of GPIO.
Chapter 14, Time-Division Multiplexing (TDM) Bus Interface—provides hardware details about the TDM bus
interface.
Chapter 15, Universal Serial Bus (USB) Interface—provides hardware details about the USB bus interface.
Chapter 16, Universal Subscriber Identity Module (USIM) Interface—provides the features of the USIM.
Chapter 17, Radio Parallel Digital Interface (RPDIF)—describes the features, RPDIF variations, and RF-SPI
functional muxing of RPDIF interface.
Chapter 18, Joint Test Action Group (JTAG) Interface—provides JTAG features and implementation details.
Chapter 19, ARM Subsystem (with Dual-ARM Cores)—describes the features and implementation details of the
ARM Cortex A9.

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Chapter 20, Ceva-XC323 DSP—introduces the features of the Ceva processors.

Chapter 21, Mindspeed Advanced Processor (MAP) Array / FFT Accelerator—describes the Mindspeed Advanced
Processor (MAP) Array or FFT Accelerator implemented in the Transcede 2xxx.
Chapter 22, Forward Error Correction (FEC) Hardware Accelerator—describes the Forward Error Correction block
implemented in the Transcede 2xxx.
Chapter 23, Security Protocol Accelerator (SPA) and Security Encryption Engine—introduces the features and
implementation details of the SPA block.
Chapter 24, Chip Rate Processor (CRP) Correlator—describes the CRP correlator and sub-blocks for Transcede
2120, Transcede 2150, and Transcede 2200.
Chapter 25, Bit Processor—provides the block diagram of the bit processor and its features.
Chapter 26, Memory to Memory DMA (MDMA) Controller—describes the features and implementation of the
MDMA controller.
Chapter 27, Internal Boot ROM (IBR) Implementing Secure Boot—describes the IBR related information, for
example, boot mode and eFuse.
Chapter 28, Interrupts, Timers, Clock and Reset—describes the interrupts, timers, clocking scheme and reset
function.
Chapter 29, Electrical and Environmental Specifications—provides all electrical and environmental specifications
for the Transcede 2xxx.
Chapter 30, Package Dimensions—provides mechanical packaging information for the Transcede 2xxx.

Related Documentation
A comprehensive library of Transcede 2xxx reference and application documentation is available from Mindspeed.
Developers, applications engineers, and other personnel who are looking to implement, support, or otherwise
become familiar with the Transcede 2xxx, log on and register at: www.mindspeed.com to access the full range of
support documentation. For detailed information on specific devices and available features, always consult the
Mindspeed library of titles. The following table gives a summary of Mindspeed publications related to this
document.

Transcede 2xxx Related Documentation

Title Part Number Description
Transcede® 2xxx Product Brief 842xx-BRF-001 Provides device marketing brief.
®
Transcede 2xxxThermal Application 842xx-HWG-001 Provides board thermal design considerations.
Considerations
Transcede® 2xxx Hardware Requirements 842xx-HWG-002 Describes board design requirements specification.
Specification
Transcede® 2xxx Development Board and Design 842xx-EVMD-001 Describes layout and configurations of the development board
Kit User Guide and features and operations of the design kit.

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Preface

Transcede 2xxx Related Documentation (Continued)

Title Part Number Description
Transcede® 2xxx Porting and Implementation Guide 842xx-SWG-001 Gives an overview of the Transcede 2xxx software architecture,
highlights the differences to the Transcede 4000 software
architecture, then proposes a method for porting to the
Transcede 4000 platform that will allow minimum changes
when later running on the Transcede 2xxx device.
Transcede® 2xxx Programming Guide 842xx-SWG-002 Provides comprehensive information for engineers who
develop Transcede 2xxx applications.
Transcede® 2xxx Software Architecture 842xx-SWG-003 Provides an overview of application independent software
Specification architecture concepts, such as major functional blocks, data
flow, control flow, and so on.

Supported Devices
This following devices are included in the T2xxx family:
• T2100
• T2130
• T2120
• T2150
• T2200

Third Party Documentation

As ARM and CEVA are implemented in the Transcede 2xxx, consult respective websites for your reference:
• http://www.arm.com/
• http://www.ceva-dsp.com

Acronyms in this Document

The following table gives a summary of acronyms appearing in this document.

Acronyms in this Document

Acronyms Description
3G Generation 3
4G Generation 4
APB Advanced Peripheral Bus
API Application Programming Interface
ARM Advanced RISC Machines
BISR Built-In Self Repair
BP Break Point
CBC Cipher Block Chaining
CPDMA CPRI DMA controller

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Acronyms in this Document (Continued)

Acronyms Description
CPRI Common Public Radio Interface
CRC Cyclic Redundancy Check
CTC Convolutional Turbo Coding
CTR Counter Mode
DCT Discrete Cosine Transform
DDR Double Data Rate
DL Down Link
DMA Direct Memory Access Controller
DSP Digital Signal Processing
ECB Electronic Code Book
ECC Error Correcting Code
EXP Expansion Bus
ETB Embedded Trace Buffer
FDD Frequency Division Duplex
FEC Forward Error Correction
FFT Fast Fourier Transform
FIFO First In First Out
GIC Generic Interrupt Control
GPIO General Purpose Input Output
HS High Speed
HSPA High-Speed Packet Access
2
I C Inter-IC Interface
IBR Internal Boot ROM
IDCT Inverse Discrete Cosine Transform
IFFT Inverse Fast Fourier Transform
IMT-Advanced International Mobile Telecommunications Advanced
IP Internet Protocol
IPI Inter-Processor Interrupt
IPSec Internet Protocol Security
IRAM Internal RAM
JTAG Joint Test Action Group
LTE Long Term Evolution
MAC Media Access Controller
MAP Mindspeed Advanced Processor
MBIST Memory Built-In Self Test
MDIO Management Data Input/Output
MDMA Memory to Memory Direct Memory Access controller
MIMO Multiple Input Multiple Output

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Preface

Acronyms in this Document (Continued)

Acronyms Description
NMI Non Mask-able Interrupt
NPU Network Processing Unit
NTG Network Timing Generator
OVSF Orthogonal Variable Spreading Factor
PCIe Peripheral Component Interconnect Express, PCI Express
PCS Physical Coding Sub-layer
PFC Priority-based Flow Control
PKA Public Key Accelerator
PLE Pre-Load Engine
REC Radio Equipment Control
RGMII Reduced Gigabit Media Independent Interface
RISC Reduced Instruction Set Computer
SCL Serial Clock
SCU Snoop Control Unit
SDA Serial Data
SDRAM Synchronous Dynamic Random Access Memory
SerDes Serializer/Deserializer
SGMII Serial Gigabit Media Independent Interface
SMP Symmetric Multi-Processing
SoC System on Chip
SPA Security Protocol Accelerator
SPAcc Security Protocol Accelerator
SPI Serial Peripheral Interface
SPI Shared Peripheral Interrupt
SRIO Serial Rapid IO
SYS System Group
TCP Transmission Control Protocol
TDM Time-Division Multiplexing
TLB Translation Look-aside Buffer
TrCH Transport Channel
TRNG True Random Number Generator
TSU Time Stamp Unit
UART Universal Asynchronous Receiver/Transmitter
UL Up Link
USIM Universal Subscriber Identity Module
UDP User Datagram Protocol
USB Universal Serial Bus
WCDMA Wideband Code Division Multiple Access

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Preface

Document Conventions
The following conventions are used throughout Mindspeed documentation:

Document Conventions
Convention Description Example
Bold Text in this font denotes items that are emphasized, menu On the File menu, click Save As.
items, buttons, and dialog box options.
Italics This font is used for the names of disk drives, paths, The patch 001-uboot.patch is available under the
directories, file names, and extensions. package/mspd/u-boot/patches/ directory.
Courier Text in this font denotes code sections, programming Create a folder to unpack the filesystem:
examples, functions, arguments, threads, commands, and ~$ mkdir openwrt_fs
syntax examples.

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1 Introduction
This chapter presents an overview of the Transcede 2xxx device capabilities, applications, and interfaces. This
chapter is intended to assist system designers and architects evaluate the key features of the Transcede 2xxx
device.

1.1 Transcede 2xxx Overview

Mindspeed's single mode LTE (“Transcede 2100 and Transcede 2130” or “T2100 and T2130”) and dual-mode 3G/
LTE (“Transcede 2120, Transcede 2150, and Transcede 2200” or “T2120, T2150, and T2200”) are for residential,
SOHO and enterprise applications. Transcede solutions deliver a complete small cell base station on a chip,
supporting concurrent multi-standard operation with carrier-grade software performance (HSPA and LTE). The
newest addition to the award-winning Transcede family, T2000-series solutions handle the complete signal flow
from the radio interface to IP packets for network connectivity. The product suite builds upon the combined heritage
of Mindspeed and Picochip in designing award-winning small cell SoC solutions.
The Transcede 2xxx is a highly integrated SoC solution that includes a tightly coupled MAC and PHY on one
device, providing optimal latency and avoiding complex software portioning across multiple devices. Each can
support up to 32 simultaneous users as a complete solution, from RF interface to L1 and L2/L3 on a single device.
The integrated network processor capability, utilizing the latest high performance ARM CortexTM RISC processor
technology with high performance IP/Ethernet interfaces coupled with Metro Ethernet Forum (MEF) class of
service hardware acceleration, supports the layer 2 processing requirements for the next wave of small cell
designs.
The Transcede 2xxx portfolio is specifically designed for next generation of base stations providing optimal
performance. This is achieved by the use of the ARM CortexTM A9 technology for control and protocol processing,
CEVA DSP cores for baseband processing and specialized Mindspeed MAP DSP blocks for advanced signal
processing and encryption functions. All devices include carrier-grade, pre-integrated and pre-verified code for
PHY and stacks.
The Transcede 2100 and Transcede 2130 support either TD-LTE or LTE FDD, with 20MHz channels and 2x2
MIMO. Pre-integrated / pre-verified software is included with support for 3GPP Release 8/9 and roadmap to
Release 10.
The Transcede 2120, Transcede 2150, and Transcede 2200 have the identical LTE capability but adds
simultaneous 3G, for a single chip dual-mode solution. This is a super-set of Mindspeed’s industry-leading PC3032
PHY capability, with support for Release 9 HSPA+ including MIMO, dual carrier and soft handover.
The Transcede 2120 family is Mindspeed's answer to the market demands for next-generation residential and
SOHO small cells. Mindspeed has leveraged multi-core technology proven in its carrier-class VoIP processing
solutions to create a compelling, carrier-class solution for next-generations femtocell designs.
Transcede 2xxx devices are available with a reference design kit which provides optimized LTE and 3G (for
Transcede 2120, Transcede 2150, and Transcede 2200) software and an extensible verification environment and
board support package (BSP) using Linux. The flexible configurable software supports current and next generation
LTE and 3G small cell applications to avoid costly in-field hardware upgrades.
Integrated support for USB and PCIe enables high-performance systems to be easily developed, for example, with
integrated WiFi.

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Introduction

1.2 Transcede 2xxx Block Diagram

Figure 1-1 illustrates the top-level block diagram of the Transcede 2xxx. Functional blocks are connected through
bus matrix slice. CEVA group and FEC group are connected to the main system bus through an asynchronous
slice.

NOTE: In Figure 1-1, CRP Cluster and CPRI are for Transcede 2120, Transcede 2150, and
Transcede 2200.

Table 1-1 lists the Transcede 2xxx processor speeds.

Table 1-1 Transcede 2xxx Processor Speeds

CEVA DSP (MHz) FEC IP (MHz) MAP4 IP (MHz) ARM (MHz)
720 750/550 720 1000

1.3 Transcede 2xxx Devices

Table 1-2 lists the devices in the Transcede 2xxx family.

Table 1-2 Transcede 2xxx Devices

Transcede 2xxx Device Name Part Numbers
LTE Residential / SOHO T2100 M84210G-13
LTE Small Enterprise T2130 M84213G-13
Dual Mode Residential / SOHO T2120 M84212G-13
Dual Mode Small Enterprise T2150 M84215G-13
T2200 M84223G-12P

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Figure 1-1 Transcede 2xxx Block Diagram
842xx-DSH-001-A

MAP4
MAP4
MAP4
10kB
10kB
80kB
80kB
DRAM
DRAM
80kB
N
N
E
O
Cortex A9
T2xxx
Chip Rate MAP4 PRAM
80kB E N
DRAM Processor PRAM DRAM
10kB O
Cortex A9 32kB
10kB DRAM N 32kB
24 Correlators PRAM
PRAM ICache DCache
32kB 32kB
CRP Cluster MAP Cluster ICache DCache
DMA FIFO
BitStream DMA FIFO DMA FIFO Snoop CU
ACP
Engine 128bit Port
Addr Filter

OVSF, GoldCode, AXI

Scramblers, CRCs...

64bit

64bit
Mindspeed Proprietary and Confidential

CevaXC323
CevaXC323 256kB

256 bit wide

128bit AXI
768kB 1024 bit wide L2CC
Mindspeed Technologies®

CRAM 256 bit wide 1024 bit wide L2 USIM

256 bit wide
96kB Cache/
128bit AXI 256kB DRAM Addr Filter
Cache

128bit AXI
128bit AXI 256kB DRAM TSU NTG
96kB PRAM
Cache/
PRAM 2D DMA Dual Security

64bit AXI
UART 2X
Cache-DMA AXI-S 2D DMA
AXI-M Accelerator
FEC CTC/Viterbi Cache-DMA AXI-S AXI-M Units TDM/NTG

32bit APB
DMA FIFO X2

Accelerator Units Program 128bit DSP Data 128bit ML-AXI (IPSEC & 4G/3G-
(ULx1) (DLx1) ML-AXI
SNOW) I2C
64bit
ARM 64bit ML-AXI-Trust Zone

64bit
128bit AXI

128bit AXI

128bit AXI
3G/4G AXI DMA DMA Timers 2X
(LTE-A//HSPA+)
SPI 2X
2x JESD207

64bit AXI

64bit AXI
64bit AXI
GPIO
JEDS 256kB
12bit 207 64bit AXI
IRAM
DDR

JEDS
64bit
12bit 207 CEVA 128bit ML AXI-Trust Zone
DDR

AXI
ARM 64bit ML-AXI-Trust Zone
64/128bit AXI
Bridge

32bit AHB
PCIe x1 or PCIe x4

64bit AXI

64bit AXI

64bit AXI
64bit AXI
Serdes (4)

64bit AXI
PCIe
TBI X1 or x4 64bit AXI
PCS

32bit AHB
Quad-Port Arbitrator
CPRIv4.1 GigE
x1 64bit AXI DDR3-1600 Controller GigE MAC MAC
PCS

TBI USB2
w/1588-2008
PCS w/1588-2008 Expansion/
Mux

PCIe PCS
PHY NAND ECC
64bit AXI
PCS

32bit

x1

Introduction
TBI TBI

rGMII

Exp Bus
USB
Sel Mux 3x1
1.25GHz Serdes (1)
1.5V/1.35V DDR3 x32 sGMII or PCIe(x1) or CPRIv4.1
24
Introduction

1.4 Device Interfaces

The Transcede 2xxx provides the following device interfaces:
• DDR3 Memory Sub-system
• SerDes for CPRI, PCIe or SGMII
• Common Public Radio Interface (CPRI) (Transcede 2120/Transcede 2150/Transcede 2200)
• Peripheral Component Interconnect Express (PCIe)
• 10/100/1G Ethernet Media Access Controller (GMAC)
• Expansion Bus Interface
• Inter-IC Interface (I2C)
• Serial Peripheral Interface (SPI) and High Speed SPI
• Universal Asynchronous Receiver / Transmitter (UART) Interface
• General Purpose Input Output (GPIO)
• Time-Division Multiplexing (TDM) Bus Interface
• Universal Serial Bus (USB) Interface
• Universal Subscriber Identity Module (USIM) Interface
• Radio Parallel Digital Interface (RPDIF)
• Joint Test Action Group (JTAG) Interface

1.5 Device Features

The Transcede 2xxx has the following device features:
• ARM Subsystem (with Dual-ARM Cores)
• Ceva-XC323 DSP
• Mindspeed Advanced Processor (MAP) Array / FFT Accelerator
• Forward Error Correction (FEC) Hardware Accelerator
• Security Protocol Accelerator (SPA) and Security Encryption Engine
• Chip Rate Processor (CRP) Correlator (Transcede 2120/Transcede 2150/Transcede 2200)
• Bit Processor
• Memory to Memory DMA (MDMA) Controller
• Internal Boot ROM (IBR) Implementing Secure Boot
• 768KB CEVA Internal RAM (CRAM)
• 256KB System Internal RAM (IRAM)
• Network Timing Generator (NTG) for TDM and Network Timing Generator (NTG) for 1588
• CPRI DMA (Transcede 2120/Transcede 2150/Transcede 2200)
• Transcede 2xxx eFuse
• TrustZone Support
• Radio Frame Synchronization Timers

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Introduction

1.6 Transcede 2xxx System Memory Map

Figure 1-2 shows the Transcede 2xxx memory map.
Figure 1-2 System Memory Map

2nd CA9 IRQ Vectors

8 KB (mapped to IRAM Top) FFFF_D000h
(reserved)
FF10_0000h
1 MB Internal Boot ROM FF00_0000h

16 MB APB Top
FE00_0000h
(reserved) Top
FDE0_0000h
1 MB SPAcc/IPSec 0 FDD0_0000h

(reserved)
FA00_0000h
4 MB External PCIe x1/x4
Memory window F600_0000h
2 MB Radio
Rad Group Config Group
1 MB CPRI/JESD/CPDMA..
2 MB F5B0_0000h
(reserved)
F500_0000h
1 MB ARM Semaphores F4F0_0000h
1 MB ARM AHB F4E0_0000h
1 MB DDR & CVP L2 CFG F404_0000h

256 MB IRAM
F400_0000h
1 MB DSP ROM F3F0_0000h
2 MB Ceva GP APB FDE0_0000h
(reserved) F3B0_0000h
Ceva
8 MB CRP Group
F340_0000h
(reserved) F30C_0000h
768 KB CRAM F300_0000h

(reserved)
F100_0000h
1 MB GP Semaphores F0F0_0000h
1 MB GP AHB F0E0_0000h
(reserved)
F020_0000h
1 MB GP CevaXC Slave 1 F010_0000h
1 MB GP CevaXC Slave 0 F000_0000h
External Memory
3.75 GB ~~ Device Space / ~
~
Expansion Bus
0001_0000
64 KB tmp boot (IBR remap) 0000_0000h

NOTE: CPRI, CRP and CPDMA blocks are not included in Transcede 2100 and Transcede 2130
devices and are for Transcede 2120, Transcede 2150, and Transcede 2200.

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Introduction

1.6.1 CEVA Group Slaves

Table 1-3 CEVA Group Partition (0xF0)
Block Name Start Address End Address Access Bus Memory Size
Ceva 0 slave 0xF000_0000 0xF00F_FFFF AXI 1 MB
Ceva 1 slave 0xF010_0000 0xF01F_FFFF AXI 1 MB
Ceva GP basic cfg 0xF0D0_0000 0xF0D0_FFFF AHB 64 KB
INTC_Ceva 0xF0D2_0000 0xF0D2_FFFF AHB 64 KB
BP 0xF0D8_0000 0xF0D9_FFFF AHB 128 KB
Ceva Semaphore 0xF0F0_0000 0xF0FF_FFFF AHB 1 MB

1.6.2 CEVA Group Partition Slaves

Table 1-4 Ceva Group Partition (0xF3) – CRAM, FFT_TOP, CRP Blocks
Block Name Start Address End Address Access Bus Memory Size
CRAM 0xF300_0000 0xF30B_FFFF AXI 768 KB
CRP (Transcede 2120/2150/ 0xF340_0000 0xF3BF_FFFF AXI 8 MB
2200
CEVA Basic cfg 0xF3D0_0000 0xF3D0_FFFF AHB 64 KB
SyncNet_SPU 0xF3D1_0000 0xF3D1_FFFF APB3 64 KB
IQ_COUNTER0 0xF3D3_0000 0xF3D3_0FFF APB3 4 KB
FFT_TOP 0xF3D4_0000 0xF3D4_FFFF APB3 64 KB
MDMA_CRP0 (Transcede 0xF3D8_0000 0xF3D8_3FFF APB3 16 KB
2120/2150/2200)
MDMA_CRP1 (Transcede 0xF3D8_4000 0xF3D8_7FFF APB3 16 KB
2120/2150/2200)

1.6.3 SYS Partition Slaves

Table 1-5 SYS Partition Slaves (0xF4) – IRAM, FEC, DDR cfg, Semaphore Blocks
Block Name Start Address End Address Access Bus Memory Size
IRAM 0xF400_0000 0xF403_FFFF AXI 256 KB
SYS Basic cfg 0xF4C0_0000 0xF4C0_7FFF AHB 32 KB
Secure cfg 0xF4C0_8000 0xF4C0_FFFF AHB 32 KB
DDR Ctrl cfg 0xF4C2_0000 0xF4C3_FFFF AHB8/16 128 KB
MDMA_SYS0 0xF4C8_0000 0xF4C8_FFFF APB3 64 KB
MDMA_SYS1 0xF4C9_0000 0xF4C9_FFFF APB3 64 KB
DDR Phy 0xF4CA_0000 0xF4CA_FFFF APB3 64 KB

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Introduction

Table 1-5 SYS Partition Slaves (0xF4) – IRAM, FEC, DDR cfg, Semaphore Blocks (Continued)
Block Name Start Address End Address Access Bus Memory Size
Clock Reset + NTG 0xF4CF_0000 0xF4CF_FFFF APB3_8bit 64 KB
FEC0 DL cfg 0xF4D0_0000 0xF4D0_FFFF APB3 64 KB
FEC0 UL cfg 0xF4D1_0000 0xF4D1_FFFF APB3 64 KB
ARM CA9 & L2 APB 0xF4E0_0000 0xF4E7_FFFF APB3 512 KB
Semaphore ARM 0xF4F0_0000 0xF4FF_FFFF AHB 1 MB

1.6.4 Radio Group

Table 1-6 RAD Group – RPDIF, SGMII, PCIE, CPRI, CPDMA Blocks
Block Name Start Address End Address Access Bus Memory Size
CPRI CPU bus (Transcede 0xF5B0_0000 0xF5B0_FFFF AXI 64 KB
2120/2150/2200)
JDMA0 cfg 0xF5B8_0000 0xF5B8_7FFF APB3 32 KB
RPDIF (JESD) 0 cfg 0xF5B8_8000 0xF5B8_FFFF APB3 32 KB
JDMA1 cfg 0xF5B9_0000 0xF5B9_7FFF APB3 32 KB
RPDIF (JESD) 1 cfg 0xF5B9_8000 0xF5B9_FFFF APB3 32 KB
CPDMA cfg (Transcede 2120/ 0xF5C0_0000 0xF5C0_FFFF APB3 64 KB
2150/2200)
PCIe0 cfg 0xF5D0_0000 0xF5D0_FFFF AHB / AXI 64 KB
RAD Basic cfg 0xF5E0_0000 0xF5E0_FFFF APB3 64 KB
Radio Timer 0xF5E3_0000 0xF5E3_FFFF APB 64 KB
GEM0 Controller(SGMII) 0xF5E6_0000 0xF5E6_FFFF APB3 64 KB
SERDES0 (PCIe) 0xF5E8_0000 0xF5E8_FFFF prop 64 KB
SERDES1 (PCIe/CPRI/SGMII) 0xF5E9_0000 0xF5E9_FFFF prop 64 KB
(CPRI supported by Transcede
2120/2150/2200)
PCIe0 (Fixed slave window) 0xF600_0000 0xF9FF_FFFF AXI 64 MB
PCIe1 cfg 0xFA00_0000 0xFA1F_FFFF AXI 2 MB
PCIe1 (Fixed slave window) 0xFA20_0000 0xFCFF_FFFF AXI 46 MB

1.6.5 System Masters/Slaves Group

Table 1-7 System Partition - SPAcc, IPSec, RGMII, TDM, GPIO, UART, SPI, I2C Blocks
Block Name Start Address End Address Access Bus Memory Size
SPAcc Slave 0 0xFDE0_0000 0xFDE7_FFFF AXI32 512 KB
IPSec Slave 0 0xFDE8_0000 0xFDEB_FFFF AXI32 256 KB
SASPA_Slave0 0xFDEC_0000 0xFDEF_FFFF AXI32 256 KB
TDM 0xFE00_0000 0xFE00_7FFF APB 32 KB
TDMA 0xFE02_0000 0xFE02_FFFF APB 64 KB

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Introduction

Table 1-7 System Partition - SPAcc, IPSec, RGMII, TDM, GPIO, UART, SPI, I2C Blocks (Continued)
Block Name Start Address End Address Access Bus Memory Size
TIMER 0xFE05_0000 0xFE05_FFFF APB 64 KB
GPIO 0xFE07_0000 0xFE07_FFFF APB 64 KB
UART S1 0xFE09_0000 0xFE09_1FFF APB 8 KB
SPI S1 0xFE09_8000 0xFE09_9FFF APB 4 KB
I2C 0xFE09_C000 0xFE09_FFFF APB 8 KB
USIM 0xFE0E_0000 0xFE0E_FFFF APB 64 KB
eFuse / OTP ROM 0xFE0F_0000 0xFE0F_FFFF APB 64 KB
EXP BUS 0xFE10_0000 0xFE10_FFFF APB 64 KB
GEM1 0xFE19_0000 0xFE19_FFFF APB3 64 KB
UART0/SPI0 (HS) 0xFE80_0000 0xFE80_FFFF AHB 64 KB
USB 0xFE82_0000 0xFE86_FFFF AHB 256KB+64 KB
IBR (BootRom) 0xFF00_0000 0xFF0F_FFFF APB 1 MB

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2 Device Configuration Options
This chapter describes the boot source selection and device configuration options. The Transcede 2xxx boots into
alternative configurations based on voltage levels at specific inputs. Voltage levels are sampled at reset time.

2.1 Boot Options

Bootstraps provide boot control output to Fabric and EXP blocks, as shown in Table 2-1.

Table 2-1 Transcede 2xxx Boot Options

Boot_OP [2:0] Outcome Expansion Bus Width
000 LS SPI N/A
2
001 I C N/A
010 Fast SPI N/A
011 UART N/A
100 Reserved N/A
101 Reserved N/A
110 8-bit NOR device 8-bit mode
111 16-bit NOR device 16-bit mode

2.2 JTAG Debug Modes

The Transcede 2xxx uses two JTAG ports:
• JTAG0 Interface is dedicated for Dual Core ARM
• JTAG1 functions based on JTAG Mode selected. C_JTAG_MODE is boot controlled output provided by
Bootstrap, as shown in Table 2-2.

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Device Configuration Options

2.3 Bootstraps
Bootstraps are values latched on the following inputs pins as shown in Table 2-2 during assertion state of the
device hardware reset. Upon de-assertion of device hardware reset, their latched values are in effect and pins
directions are switched to output state according to their normal behavioral functions.

Table 2-2 Bootstraps Signals

Pin Name Bootstrap Name Description
EXP_A_0 BOOT_OP[0] Boot Option: See Table 2-1
EXP_A_1 BOOT_OP[1] Boot values should be driven during assertion state of device Hardware reset.

EXP_A_2 BOOT_OP[2]
EXP_A_3 Sync Mode Bootstrap pull-up.
EXP_A_4 RSVD This Bootstrap should be pulled high.
EXP_A_5 EPROM_N When asserted "active low", it will enable boot from external EPROM/FLASH.
EXP_A_6 RSVD This Bootstrap is not used and should be pulled high.
EXP_A_7 SRDS_MODE[0] SerDes (X1) Mode:
EXP_A_8 SRDS_MODE[1] • 00: PCIe Mode
• 01: CPRI Mode (Transcede 2120, Transcede 2150, and Transcede 2200)
• 1x: SGMII Mode (default)
EXP_A_9 CORESIGHT_SEL Bootstrap to select between : RPDIF0 (CMOS) or CoreSight interface.
• 0: RPDIF0(default)
• 1: CoreSight

EXP_A_10 C_JTAG_MODE[0] C_JTAG_MODE[1:0]: Ceva Subsystem JTAG Mode:

EXP_A_11 C_JTAG_MODE[1] • 00: CEVA JTAG
• 01: SerDes0 (X4) JTAG
EXP_A_12 C_JTAG_MODE[2]
• 10: SerDes1 (X1) JTAG
• 11: DDR JTAG
EXP_A_13 RSVD This Bootstrap is not used, should be pulled high.
EXP_A_14 RSVD This Bootstrap is not used, and should be pulled down.
EXP_A_15 SSTL_MODE[0] DDR IO testing. Should be pulled down.
EXP_A_16 SSTL_MODE[1]
EXP_A_17 SPI_ADDR_LN[0] Extended Boot Option checked by IBR - SPI Address Length:
EXP_A_18 SPI_ADDR_LN[1] • 00: RSVD
• 01: 2 Byte Address
• 10: 3 Byte Address
• 11: 4 Byte Address
EXP_A_19 SPI_SC_POLARITY Extended Boot Option checked by IBR - SPI Serial Clock Polarity:
• 0: -ve
• 1: +ve

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Device Configuration Options

Table 2-2 Bootstraps Signals (Continued)

Pin Name Bootstrap Name Description
EXP_A_20 REF_CLK_OP Extended Boot Option checked by IBR - PS_XI Reference Clock Options:
EXP_A_21 See Table 27-1.

EXP_A_22
EXP_A_23 RSVD These Bootstraps are not used, should be pulled down (low).
EXP_A_24
EXP_A_25

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3 Pinout and Signal Summary
This chapter gives a summary of device signal tables and their descriptions.

3.1 Transcede 2xxx Ball Map

Figure 3-1 illustrates the Transcede 2xxx ball map as seen when looking through the top of the package.
Table 3-1 shows the pin list.
Figure 3-1 Transcede 2xxx Ball Map

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A

AA

AB

AC

AD

AE

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Pinout and Signal Summary

Table 3-1 Transcede 2xxx Pinout List

Pin Signal Pin Signal
A1 VSS B1 S0_REFCLKP
A2 S0_RXP_0 B2 S0_RXM_0
A3 S1_RXP B3 S1_RXM
A4 PA_AVDD2 B4 VSS
A5 S0_TXP_0 B5 S0_TXM_0
A6 S1_TXP B6 S1_TXM
A7 PA_AVDD2 B7 VSS
A8 USB_DM B8 AVSS_USB
A9 USB_DP B9 USB_VBUS
A10 GEM1_RX_CTL B10 GEM1_TX_CTL
A11 GEM1_RXD[3] B11 GEM1_RXC
A12 GEM1_RXD[2] B12 GEM1_RXD[1]
A13 RGMII_REFCLK B13 EXP_WE_N
A14 EXP_NAND_CS B14 EXP_CS0_N
A15 EXP_RDY B15 EXP_RE_N
A16 EXP_DQ_1 B16 EXP_DM_0
A17 EXP_CS1_N B17 EXP_DQ_2
A18 EXP_DQ_4 B18 EXP_DQ_14
A19 EXP_DQ_5 B19 EXP_DQ_8
A20 EXP_DQ_7 B20 EXP_DQ_12
A21 EXP_A_2 B21 EXP_A_1
A22 EXP_A_0 B22 EXP_A_4
A23 EXP_A_6 B23 EXP_A_8
A24 EXP_A_7 B24 EXP_A_9
A25 VSS B25 EXP_A_14

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Pinout and Signal Summary

Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
C1 S0_REFCLKM D1 RPDIF1_TX_M2
C2 VSS D2 RPDIF1_TX_P2
C3 PA_AVDD2 D3 RPDIF1_TX_P0
C4 LVDS_EXTRES D4 RPDIF1_TX_M0
C5 PA_AVDD2 D5 S1_REFCLKP
C6 VSS D6 S1_REFCLKM
C7 UP_XO D7 VSS
C8 UP_XI D8 USB_REXT
C9 GEM1_TXD[2] D9 GEM1_TXD[1]
C10 GEM1_TXD[3] D10 GEM1_TXD[0]
C11 GEM_MDC D11 GEM1_TXC
C12 GEM1_RXD[0] D12 GEM_MDIO
C13 EXP_NAND_RDY D13 NC
C14 EXP_ALE D14 EXP_NAND_RE_N
C15 EXP_DM_1 D15 EXP_NAND_WE_N
C16 EXP_CLK D16 EXP_DQ_3
C17 EXP_CS2_N D17 EXP_DQ_0
C18 EXP_DQ_11 D18 EXP_DQ_6
C19 EXP_DQ_10 D19 EXP_DQ_13
C20 EXP_DQ_9 D20 EXP_DQ_15
C21 EXP_A_5 D21 EXP_A_11
C22 EXP_A_3 D22 EXP_A_13
C23 EXP_A_12 D23 EXP_A_10
C24 EXP_A_15 D24 EXP_A_18
C25 EXP_A_17 D25 EXP_A_20

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Pinout and Signal Summary

Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
E1 RPDIF1_TX_M4 F1 RPDIF1_FBCLK_P
E2 RPDIF1_TX_P4 F2 RPDIF1_FBCLK_M
E3 RPDIF1_TX_P1 F3 RPDIF1_TX_M3
E4 RPDIF1_TX_M1 F4 RPDIF1_TX_P3
E5 VSS F5 PA_AVDD2
E6 S0_RXM_1 F6 S0_RXM_2
E7 S0_RXP_1 F7 S0_RXP_2
E8 USB_ATEST F8 VSS
E9 VSS F9 USB_ID
E10 VDDO_2P5 F10 VSS
E11 VSS F11 VDDO_2P5
E12 VDDO_2P5 F12 NC
E13 AVDD11V F13 VSS
E14 AVDD33V F14 NC
E15 VSSA_TH F15 NC
E16 VDDO_3P3 F16 VDDA1P8_TH
E17 VSS F17 VSS
E18 VSS F18 VSS
E19 VDDO_3P3 F19 VSS
E20 VSS F20 VSS
E21 VDDO_3P3 F21 VSS
E22 EXP_A_16 F22 EXP_A_24
E23 EXP_A_19 F23 EXP_A_23
E24 EXP_A_21 F24 EXP_A_25
E25 EXP_A_22 F25 GPIO00

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Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
G1 RPDIF1_MCLK_M H1 RPDIF1_RX_P0
G2 RPDIF1_MCLK_P H2 RPDIF1_RX_M0
G3 RPDIF1_TX_M5 H3 RPDIF1_TX_FRAME_M
G4 RPDIF1_TX_P5 H4 RPDIF1_TX_FRAME_P
G5 VSS H5 APROBE
G6 S0_RXM_3 H6 VSS
G7 S0_RXP_3 H7 PA_AVDD2
G8 PA_AVDD2 H8 PA_AVDD1
G9 S0_TXM_1 H9 S0_TXM_2
G10 S0_TXP_1 H10 S0_TXP_2
G11 VSS H11 PA_AVDD1
G12 VDDP_1P8 H12 VSS
G13 NC H13 NC
G14 NC H14 NC
G15 NC H15 NC
G16 NC H16 CATHOD_TH
G17 VSS H17 VSS
G18 VDDP_1P8 H18 VSS
G19 VSS H19 VSS
G20 VSS H20 VDDO_3P3
G21 VDDO_3P3 H21 JTAG1_TRST_N
G22 GPIO03 H22 GPIO02
G23 GPIO01 H23 GPIO06
G24 GPIO04 H24 GPIO07
G25 JTAG0_TMS H25 JTAG0_TRST_N

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Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
J1 RPDIF1_RX_P1 K1 RPDIF1_RX_P3
J2 RPDIF1_RX_M1 K2 RPDIF1_RX_M3
J3 RPDIF1_RX_FRAME_M K3 RPDIF1_RX_M2
J4 RPDIF1_RX_FRAME_P K4 RPDIF1_RX_P2
J5 PA_AVDD1 K5 AVDD18V
J6 S0_TXM_3 K6 VSS
J7 S0_TXP_3 K7 PA_AVDD2
J8 PA_AVDD1 K8 VDD
J9 PA_AVDD1 K9 VSS
J10 PA_AVDD3 K10 VDD
J11 VSS K11 VSS
J12 VSS K12 VDD
J13 VSS K13 VSS
J14 VSS K14 VDD
J15 ANODE_TH K15 VSS
J16 VSS K16 VDD
J17 VSS K17 VSS
J18 VSS K18 VDD
J19 VSS K19 VSS
J20 VSS K20 VDD
J21 JTAG1_TDI K21 JTAG1_TMS
J22 GPIO05 K22 SPI0_RXD
J23 GPIO08 K23 SPI0_SS2_N
J24 GPIO09 K24 JTAG0_TCK
J25 JTAG0_TDI K25 JTAG0_TDO

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Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
L1 RPDIF1_RX_M5 M1 RPDIF0_ENABLE
L2 RPDIF1_RX_P5 M2 RPDIF0_FBCLK
L3 RPDIF1_RX_P4 M3 RPDIF0_TX_FRAME
L4 RPDIF1_RX_M4 M4 RPDIF0_MCLK
L5 AVDD18V M5 AVDD18V
L6 AVSS18V M6 AVSS18V
L7 VDD M7 VSS
L8 VSS M8 VDD
L9 VDD M9 VSS
L10 VSS M10 VDD
L11 VDD M11 VSS
L12 VSS M12 VDD
L13 VDD M13 VSS
L14 VSS M14 VDD
L15 VDD M15 VSS
L16 VSS M16 VDD
L17 VDD M17 VSS
L18 VSS M18 VDD
L19 VDD M19 VSS
L20 VDDO_3P3 M20 VDDP_1P8
L21 JTAG1_TDO M21 JTAG1_TCK
L22 SPI_S1_TXD M22 SPI0_TXD
L23 SPI_S1_SCLK M23 SPI_S1_SS1_N
L24 SPI0_SS1_N M24 I2C_SCL
L25 SPI0_SCLK M25 I2C_SDA

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Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
N1 RPDIF0_TXNRX P1 RPDIF0_DIQ0_10
N2 RPDIF0_RX_FRAME P2 RPDIF0_DIQ0_5
N3 RPDIF0_DIQ0_7 P3 RPDIF0_DIQ0_9
N4 RPDIF0_DIQ0_11 P4 RPDIF0_DIQ0_6
N5 VDDO_2P5 P5 VDDO_2P5
N6 AVSS18V P6 VDD
N7 VDD P7 VSS
N8 VSS P8 VDD
N9 VDD P9 VSS
N10 VSS P10 VDD
N11 VDD P11 VSS
N12 VSS P12 VDD
N13 VDD P13 VSS
N14 VSS P14 VDD
N15 VDD P15 VSS
N16 VSS P16 VDD
N17 VDD P17 VSS
N18 VSS P18 VDD
N19 VDD P19 VSS
N20 VSS P20 VDDO_3P3
N21 VDDO_USIM P21 TESTMODE_N
N22 SPI0_SS3_N P22 GPIO15
N23 SPI_S1_SS0_N P23 GPIO14
N24 SPI0_SS0_N P24 TDM0_DX
N25 SPI_S1_RXD P25 GPIO11

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Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
R1 RPDIF0_DIQ0_4 T1 RPDIF0_DIQ1_11
R2 RPDIF0_DIQ0_8 T2 RPDIF0_DIQ1_10
R3 RPDIF0_DIQ0_3 T3 RPDIF0_DIQ0_0
R4 RPDIF0_DIQ1_9 T4 RPDIF0_DIQ0_1
R5 VDDP_1P8 T5 VSS
R6 VSS T6 VDD
R7 VDD T7 VSS
R8 VSS T8 VDD
R9 VDD T9 VSS
R10 VSS T10 VDD
R11 VDD T11 VSS
R12 VSS T12 VDD
R13 VDD T13 VSS
R14 VSS T14 VDD
R15 VDD T15 VSS
R16 VSS T16 VDD
R17 VDD T17 VSS
R18 VSS T18 VDD
R19 VDD T19 VSS
R20 VSS T20 VDDO_3P3
R21 SCANEN T21 TM_SEC_EN
R22 TDM0_DR T22 SRDS0_REFCLK
R23 GPIO10 T23 GEM1_REFCLK
R24 TDM1_DR T24 TDM1_DX
R25 GPIO12 T25 GPIO13

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Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
U1 RPDIF0_DIQ0_2 V1 RPDIF0_DIQ1_3
U2 RPDIF0_DIQ1_8 V2 RPDIF0_DIQ1_6
U3 RPDIF0_DIQ1_1 V3 RPDIF0_DIQ1_7
U4 RPDIF0_DIQ1_5 V4 RPDIF0_DIQ1_4
U5 VDDO_2P5 V5 VDDP_1P8
U6 VSS V6 VDD
U7 VDD V7 VSS
U8 VSS V8 VDD
U9 VDD V9 VSS
U10 VSS V10 VDD
U11 VDD V11 VSS
U12 VSS V12 VDD
U13 VDD V13 VSS
U14 VSS V14 VDD
U15 VDD V15 VSS
U16 VSS V16 VDD
U17 VDD V17 AVDD_CORE_PLL
U18 VSS V18 AVSS_CORE_PLL
U19 VDD V19 DDR_ATO
U20 VDDP_1P8 V20 AVSS_CORE_PLL
U21 TRISTATE V21 BSCANMODE
U22 USIM_SCIO V22 EXP_CS3_N
U23 UART_S1_RX V23 UART0_RX
U24 UART0_TX V24 UART0_CTS_N
U25 UART_S1_TX V25 UART0_RTS_N

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Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
W1 RPDIF0_DIQ1_2 Y1 FRAME_CLK
W2 RPDIF0_DIQ1_0 Y2 DDR_VDDQ
W3 RPDIF1_TXNRX Y3 VSS
W4 RPDIF1_ENABLE Y4 FRAME_SYNC
W5 VSS Y5 DDR_VDDQ
W6 VSS Y6 VSS
W7 DDR_PLL_VDD Y7 DDR_PLL_VSS
W8 VSS Y8 DDR_VDDQ
W9 VDD Y9 VSS
W10 DDR_PLL_VDD Y10 DDR_PLL_VSS
W11 DDR_PLL_VSS Y11 DDR_VDDQ
W12 DDR_PLL_VDD Y12 VSS
W13 DDR_PLL_VSS Y13 DDR_PLL_VDD
W14 VSS Y14 DDR_VDDQ
W15 VDD Y15 VSS
W16 VSS Y16 VDDO_3P3
W17 AVDD_CORE_PLL Y17 DDR_VDDQ
W18 DDR_DTO[1] Y18 VSS
W19 DDR_DTO[0] Y19 VSS
W20 DDR_PLL_VSS Y20 DDR_PLL_VDD
W21 SCANMODE Y21 FSOURCE_MBIST
W22 PPS_CLK Y22 PS_XO
W23 GEM0_REFCLK Y23 FSOURCE_0
W24 TSU_NTG_CLKOUT Y24 PS_XI
W25 TSU_VCXO_CLK Y25 RESET_N

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Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
AA1 VSS AB1 NC
AA2 NC AB2 NC
AA3 NC AB3 NC
AA4 VSS AB4 DDR_VDDQ
AA5 DDR_DQS_N[3] AB5 DDR_DATA[24]
AA6 DDR_DQS[3] AB6 DDR_DATA[31]
AA7 VSS AB7 DDR_VDDQ
AA8 DDR_DQS_N[2] AB8 DDR_DATA[16]
AA9 DDR_DQS[2] AB9 DDR_DATA[23]
AA10 VSS AB10 DDR_VDDQ
AA11 DDR_DQS_N[1] AB11 DDR_DATA[10]
AA12 DDR_DQS[1] AB12 DDR_DATA[14]
AA13 VSS AB13 DDR_VDDQ
AA14 DDR_DQS_N[0] AB14 DDR_DATA[3]
AA15 DDR_DQS[0] AB15 DDR_DATA[6]
AA16 VSS AB16 DDR_VDDQ
AA17 DDR_A[5] AB17 DDR_BA[1]
AA18 FSOURCE_1 AB18 DDR_A[8]
AA19 DDR_VDDQ AB19 DDR_A[12]
AA20 VSS AB20 DDR_A[13]
AA21 DDR_VDDQ AB21 VSS
AA22 FSOURCE_ID AB22 DDR_CLKE[0]
AA23 DDR_CLK_N[1] AB23 DDR_CLK[1]
AA24 VSS AB24 VSS
AA25 DDR_CLK_N[0] AB25 DDR_CLK[0]

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Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal Pin Signal
AC1 VSS AD1 DDR_VDDQ
AC2 NC AD2 NC
AC3 NC AD3 NC
AC4 VSS AD4 DDR_VDDQ
AC5 DDR_DATA[25] AD5 DDR_DATA[26]
AC6 DDR_DATA[30] AD6 DDR_DATA[29]
AC7 VSS AD7 DDR_VDDQ
AC8 DDR_DATA[17] AD8 DDR_DATA[18]
AC9 DDR_DATA[22] AD9 DDR_DATA[21]
AC10 VSS AD10 DDR_VDDQ
AC11 DDR_DATA[9] AD11 DDR_DATA[8]
AC12 DDR_DATA[13] AD12 DDR_DATA[15]
AC13 VSS AD13 DDR_VDDQ
AC14 DDR_DATA[2] AD14 DDR_DATA[1]
AC15 DDR_DATA[7] AD15 DDR_DATA[5]
AC16 VSS AD16 DDR_VDDQ
AC17 DDR_BA[2] AD17 DDR_A[0]
AC18 DDR_A[2] AD18 DDR_A[1]
AC19 DDR_A[7] AD19 DDR_A[6]
AC20 DDR_A[11] AD20 DDR_A[10]
AC21 DDR_CLKE[1] AD21 DDR_ODT[1]
AC22 VSS AD22 DDR_CS_N[1]
AC23 DDR_ODT[0] AD23 DDR_CAS_N
AC24 DDR_VDDQ AD24 DDR_RAM_RST_N
AC25 DDR_ZQ AD25 DDR_WE_N

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Table 3-1 Transcede 2xxx Pinout List (Continued)

Pin Signal
AE1 VSS
AE2 NC
AE3 NC
AE4 DDR_DM[3]
AE5 DDR_DATA[27]
AE6 DDR_DATA[28]
AE7 DDR_DM[2]
AE8 DDR_DATA[19]
AE9 DDR_DATA[20]
AE10 DDR_DM[1]
AE11 DDR_DATA[11]
AE12 DDR_DATA[12]
AE13 DDR_DM[0]
AE14 DDR_DATA[0]
AE15 DDR_DATA[4]
AE16 DDR_VREF
AE17 DDR_BA[0]
AE18 DDR_A[3]
AE19 DDR_A[4]
AE20 DDR_A[9]
AE21 DDR_A[14]
AE22 DDR_A[15]
AE23 DDR_CS_N[0]
AE24 DDR_RAS_N
AE25 VSS

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3.2 Summary of Interface Signals

The Transcede 2xxx provides the following categories of signals:
• DDR Signals
• MDIO Signals
• RGMII Signals
• Expansion Bus Signals
• I2C Signals
• TDM Signals
• SPI Signals
• UART Signals
• GPIO Signals
• USIM Signals
• USB Signals
• RPDIF 0 (JESD207) Signals
• RPDIF 1 (JESD207 LVDS) Signals
• JTAG Signals
• SerDes0 for PCIe0 (4x) Signals
• SerDes1 for CPRI or SGMII or PCIe Signals
• Test and Misc Signals
• Efuse Signals
• Radio Timer Signals
• Thermal Signals

Table 3-2 DDR Signals

Signal Name Direction I/O PU/PD Strength Description
DDR_CLK[0] O 1.5 V - - Differential clock outputs
DDR_CLK[1] O 1.5 V - -
DDR_CLK_N[0] O 1.5 V - -
DDR_CLK_N[1] O 1.5 V - -
DDR_CLKE[0] O 1.5 V - - Clock Enable active high
DDR_CLKE[1] O 1.5 V - -
DDR_ODT[0] O 1.5 V - - On-Die Termination
DDR_ODT[1] O 1.5 V - -
DDR_CS_N[0] O 1.5 V - - Chip Select
DDR_CS_N[1] O 1.5 V - -
DDR_RAS_N O 1.5 V - - Memory Row address strobe
DDR_CAS_N O 1.5 V - - Memory column address strobe
DDR_WE_N O 1.5 V - - Memory Write Enable
DDR_BA[0] O 1.5 V - - Bank Address
DDR_BA[1] O 1.5 V - - Bank Address

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Table 3-2 DDR Signals (Continued)

Signal Name Direction I/O PU/PD Strength Description
DDR_BA[2] O 1.5 V - - Bank Address
DDR_A[0] O 1.5 V - - Address bus
DDR_A[1] O 1.5 V - - Address bus
DDR_A[2] O 1.5 V - - Address bus
DDR_A[3] O 1.5 V - - Address bus
DDR_A[4] O 1.5 V - - Address bus
DDR_A[5] O 1.5 V - - Address bus
DDR_A[6] O 1.5 V - - Address bus
DDR_A[7] O 1.5 V - - Address bus
DDR_A[8] O 1.5 V - - Address bus
DDR_A[9] O 1.5 V - - Address bus
DDR_A[10] O 1.5 V - - Address bus
DDR_A[11] O 1.5 V - - Address bus
DDR_A[12] O 1.5 V - - Address bus
DDR_A[13] O 1.5 V - - Address bus
DDR_A[14] O 1.5 V - - Address bus
DDR_A[15] O 1.5 V - - Address bus
DDR_RET_EN I 1.5 V - - PAD retension enable- tied high at substrait
DDR_DM[0] O 1.5 V - - Data Byte Mask
DDR_DM[1] O 1.5 V - - Data Byte Mask
DDR_DM[2] O 1.5 V - - Data Byte Mask
DDR_DM[3] O 1.5 V - - Data Byte Mask
DDR_DATA[0] I/O 1.5 V - - Data bus
DDR_DATA[1] I/O 1.5 V - - Data bus
DDR_DATA[2] I/O 1.5 V - - Data bus
DDR_DATA[3] I/O 1.5 V - - Data bus
DDR_DATA[4] I/O 1.5 V - - Data bus
DDR_DATA[5] I/O 1.5 V - - Data bus
DDR_DATA[6] I/O 1.5 V - - Data bus
DDR_DATA[7] I/O 1.5 V - - Data bus
DDR_DATA[8] I/O 1.5 V - - Data bus
DDR_DATA[9] I/O 1.5 V - - Data bus
DDR_DATA[10] I/O 1.5 V - - Data bus
DDR_DATA[11] I/O 1.5 V - - Data bus
DDR_DATA[12] I/O 1.5 V - - Data bus
DDR_DATA[13] I/O 1.5 V - - Data bus
DDR_DATA[14] I/O 1.5 V - - Data bus
DDR_DATA[15] I/O 1.5 V - - Data bus

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Table 3-2 DDR Signals (Continued)

Signal Name Direction I/O PU/PD Strength Description
DDR_DATA[16] I/O 1.5 V - - Data bus
DDR_DATA[17] I/O 1.5 V - - Data bus
DDR_DATA[18] I/O 1.5 V - - Data bus
DDR_DATA[19] I/O 1.5 V - - Data bus
DDR_DATA[20] I/O 1.5 V - - Data bus
DDR_DATA[21] I/O 1.5 V - - Data bus
DDR_DATA[22] I/O 1.5 V - - Data bus
DDR_DATA[23] I/O 1.5 V - - Data bus
DDR_DATA[24] I/O 1.5 V - - Data bus
DDR_DATA[25] I/O 1.5 V - - Data bus
DDR_DATA[26] I/O 1.5 V - - Data bus
DDR_DATA[27] I/O 1.5 V - - Data bus
DDR_DATA[28] I/O 1.5 V - - Data bus
DDR_DATA[29] I/O 1.5 V - - Data bus
DDR_DATA[30] I/O 1.5 V - - Data bus
DDR_DATA[31] I/O 1.5 V - - Data bus
DDR_DQS[0] I/O 1.5 V - - Differential Data Strobe
DDR_DQS[1] I/O 1.5 V - - Differential Data Strobe
DDR_DQS[2] I/O 1.5 V - - Differential Data Strobe
DDR_DQS[3] I/O 1.5 V - - Differential Data Strobe
DDR_DQS_N[0] I/O 1.5 V - - Differential Data Strobe
DDR_DQS_N[1] I/O 1.5 V - - Differential Data Strobe
DDR_DQS_N[2] I/O 1.5 V - - Differential Data Strobe
DDR_DQS_N[3] I/O 1.5 V - - Differential Data Strobe
DDR_DTO[0] O 1.5 V - - Differential Data Strobe
DDR_DTO[1] O 1.5 V - - Differential Data Strobe
DDR_ATO I/O 1.5 V - - Differential Data Strobe
DDR_ZQ I/O 1.5 V - - Differential Data Strobe
DDR_RAM_RST_N O 1.5 V - - Differential Data Strobe

Table 3-3 MDIO Signals

Signal Name Direction I/O PU/PD Strength Description
GEM_MDC O 2.5 V – 10 mA Serial management interface clock
GEM_MDIO I/O 2.5 V – 15 mA Serial management interface data

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Table 3-4 RGMII Signals

Ball Name RGMII Signal Direction I/O PU/PD Strength Description
GEM1_REFCLK - O 3.3 V - 18 mA PHY1 refclk output ~50 MHz
GEM1_RXC RGMII_RXC I 2.5 V - - RGMII receive clock - 125 MHz
RGMII_REFCLK RGMII_REFCLK I 2.5 V - - RGMII refclk input - 125 MHz
GEM1_RX_CTL RGMII_RX_CTL I 2.5 V - - RGMII RX Control
GEM1_RXD[0] RGMII_RXD0 I 2.5 V - - RGMII Receive data 0
GEM1_RXD[1] RGMII_RXD1 I 2.5 V - - RGMII Receive data 1
GEM1_RXD[2] RGMII_RXD2 I 2.5 V - - RGMII Receive data 2
GEM1_RXD[3] RGMII_RXD3 I 2.5 V - - RGMII Receive data 3
GEM1_TXC RGMII_TXC O 2.5 V - 15 mA RGMII Transmit Clock - 125 MHz

Use on board termination value of 390 Ω to VDD and

390 Ω to VSS
GEM1_TX_CTL RGMII_TX_CTL O 2.5 V - 10 mA RGMII TX Control

Use on board termination value of 390 Ω to VDD and

390 Ω to VSS
GEM1_TXD[0] RGMII_TXD0 O 2.5 V - 10 mA RGMII Transmit Data 0

Use on board termination value of 390 Ω to VDD and

390 Ω to VSS
GEM1_TXD[1] RGMII_TXD1 O 2.5 V - 10 mA RGMII Transmit Data 1
Use on board termination value of 390 Ω to VDD and
390 Ω to VSS
GEM1_TXD[2] RGMII_TXD2 O 2.5 V - 10 mA RGMII Transmit Data 2
Use on board termination value of 390 Ω to VDD and
390 Ω to VSS
GEM1_TXD[3] RGMII_TXD3 O 2.5 V - 10 mA RGMII Transmit Data 3
Use on board termination value of 390 Ω to VDD and
390 Ω to VSS
GEM0_REFCLK - O 3.3 V - 18 mA PHY0 refclk output ~50 MHz
TSU_VCXO_CLK - I 3.3 V PD On board jitter refined clock input to TSU block
TSU_NTG_CLKOUT - I/O 3.3 V PD 3 mA Output clock to external (on-board) VCXO for clock jetter
refine and devide.

Table 3-5 Expansion Bus Signals

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
EXP_CLK O 3.3 V Yes - 6 mA Clock out
EXP_CS0_N O 3.3 V Yes - 6 mA Chip Enable
EXP_CS1_N O 3.3 V Yes - 6 mA EXP_CS2_N muxed with GPIO24
EXP_CS3_N muxed with USIM_FCB,
EXP_CS2_N I/O 3.3 V Yes PU 6 mA
GPIO25
EXP_CS3_N I/O 3.3 V Yes PD 6 mA

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Table 3-5 Expansion Bus Signals (Continued)

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
EXP_RE_N O 3.3 V Yes - 6 mA Normal Mode: Read Enable, when
asserted, indicates a read operation from
peripheral.
Strobe Mode: command Strobe signal.
EXP_WE_N O 3.3 V Yes - 6 mA Normal Mode: Write Enable, when
asserted, indicates a write operation to
peripheral.
Strobe Mode: Read/Write Enable signal
EXP_DM_0 O 3.3 V Yes - 6 mA Data Mask
EXP_DM_1 O 3.3 V Yes - 6 mA Data Mask
EXP_RDY I/O 3.3 V Yes PU 6 mA Muxed with GPIO26
Ready Indication
EXP_A_0 I/O 3.3 V Yes PU 6 mA Address bus
EXP_A_1 I/O 3.3 V Yes PD 6 mA EXP_A_0 muxed with BOOT_OP0.
EXP_A_1 muxed with BOOT_OP1.
EXP_A_2 I/O 3.3 V Yes PD 6 mA
EXP_A_2 muxed with BOOT_OP2.
See Table 2-2, Bootstraps Signals, on
page 31 for boot options.
EXP_A_3 I/O 3.3 V Yes PU 6 mA Address bus.
EXP_A_4 I/O 3.3 V Yes PD 6 mA Address bus
(Should be set to 0)
EXP_A_5 I/O 3.3 V Yes PU 6 mA Address bus
Muxed with EPROM_N.
EXP_A_6 I/O 3.3 V Yes PU 6 mA Address bus
Muxed with IRAMBOOT_N.
EXP_A_7 I/O 3.3 V Yes PD 6 mA Address bus
EXP_A_8 I/O 3.3 V Yes PU 6 mA EXP_A_7 muxed with SRDS_MODE0.
EXP_A_8 muxed with SRDS_MODE1.
See Table 2-2, Bootstraps Signals, on
page 31 for SerDes 1 Mode options.
EXP_A_9 I/O 3.3 V Yes PD 6 mA Address bus
Muxed with CORESIGHT_SEL.
See Table 2-2, Bootstraps Signals, on
page 31 for options.
EXP_A_10 I/O 3.3 V Yes PD 6 mA Address bus
EXP_A_11 I/O 3.3 V Yes PD 6 mA EXP_A_10 muxed with
C_JTAG_MODE[0].
EXP_A_12 I/O 3.3 V Yes PD 6 mA
EXP_A_11 muxed with
C_JTAG_MODE[1].
EXP_A_12 muxed with
C_JTAG_MODE[2].
See Table 2-2, Bootstraps Signals, on
page 31 for Ceva Subsystem JTAG mode
options.
EXP_A_13 I/O 3.3 V Yes PU 6 mA Address bus
Muxed with EFUSE_ASENSE

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Table 3-5 Expansion Bus Signals (Continued)

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
EXP_A_14 I/O 3.3 V Yes PD 6 mA Address bus
EXP_A_15 I/O 3.3 V Yes PD 6 mA Address bus
Muxed with SSTL_MODE[0]
EXP_A_16 I/O 3.3 V Yes PD 6 mA Address bus
Muxed with SSTL_MODE[1]
EXP_A_17 I/O 3.3 V Yes PD 6 mA Reserved for IBR use.
EXP_A_18 I/O 3.3 V Yes PD 6 mA Reserved for IBR use.
EXP_A_19 I/O 3.3 V Yes PD 6 mA Reserved for IBR use.
EXP_A_20 I/O 3.3 V Yes PD 6 mA Reserved for IBR use.
EXP_A_21 I/O 3.3 V Yes PD 6 mA Reserved for IBR use.
EXP_A_22 I/O 3.3 V Yes PD 6 mA Reserved for IBR use.
EXP_A_23 I/O 3.3 V Yes PD 6 mA Reserved for IBR use.
EXP_A_24 I/O 3.3 V Yes PD 6 mA Reserved for IBR use.
EXP_A_25 I/O 3.3 V Yes PD 6 mA Reserved for IBR use.
EXP_ALE I/O 3.3 V Yes - 6 mA Address Latch Enable
Muxed with GPIO27
EXP_DQ_0 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_1 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_2 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_3 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_4 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_5 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_6 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_7 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_8 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_9 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_10 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_11 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_12 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_13 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_14 I/O 3.3 V Yes - 6 mA Data bus
EXP_DQ_15 I/O 3.3 V Yes - 6 mA Data bus
EXP_NAND_CS O 3.3 V Yes PD 6 mA NAND CS signal
Muxed with GPIO28
EXP_NAND_RE_N O 3.3 V Yes PD 6 mA Read Enable dedicated for NAND flash
EXP_NAND_WE_N O 3.3 V Yes PD 6 mA Write Enable dedicated for NAND flash
EXP_NAND_RDY I 3.3 V Yes PD 6 mA NAND RDY/Busy indication
Muxed with GPIO29

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Table 3-6 I2C Signals

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
2
I2C_SCL I/O - Yes - 8 mA I C serial clock.
Muxed with GPIO16.
I2C_SDA I/O - Yes - 8 mA I2C bi-directional data line.
Muxed with GPIO17.

Table 3-7 TDM Signals

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
TDM_CK I/O 3.3 V Yes - 6 mA Alternative common TDM clock for both
TDM ports.
Muxed with GPIO14, refer to muxing
Table 13-1.
TDM_FSYNC I/O 3.3 V Yes - 6 mA Alternative common TDM frame-sync for
both TDM ports. Muxed with GPIO15,
refer to muxing Table 13-1.
TDM0_CK I/O 3.3 V Yes - 12 mA Bi-directional clock for TDM port0. Muxed
with GPIO10, refer to muxing Table 13-1.
TDM0_FS I/O 3.3 V Yes - 6 mA Bi-directional Frame synchronization
signal for TDM port0. Muxed with
GPIO11, refer to muxing Table 13-1.
TDM0_DX O 3.3 V - - 6 mA Data transmit lead output from TDM
port0.
TDM0_DR I 3.3 V - PD - Data receive lead input from network into
TDM port0.
GPIO12 I/O 3.3 V Yes - 12 mA Bi-directional clock for TDM port1. Muxed
with GPIO12, refer to muxing Table 13-1.

GPIO13 I/O 3.3 V Yes - 6 mA Bi-directional Frame synchronization

signal for TDM port 1. Muxed with
GPIO13, refer to muxing Table 13-1.
TDM1_DX O 3.3 V - PD 6 mA Data transmit lead output from TDM port
1.
TDM1_DR I 3.3 V - PD - Data receive lead input from network into
TDM port 1.

Table 3-8 SPI Signals

Signal Name Direction I/O PU/PD Strength Description
SPI0 (with DMA function)
SPI0_SCLK O 3.3 V - 6 mA Muxed with JESD1_SCLK based on GPIO [0x060] misc
pin select register misc_pin_sel[9] = 1.Serial bit-rate
Clock
SPI0_RXD I 3.3 V PD - Muxed with JESD1_CMISO based on GPIO [0x060] misc
pin select register misc_pin_sel[9] = 1.Receive Data
Signal

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Table 3-8 SPI Signals (Continued)

Signal Name Direction I/O PU/PD Strength Description
SPI0_TXD O 3.3 V - 6 mA Muxed with JESD1_CMOSI based on GPIO [0x060] misc
pin select register misc_pin_sel[9] = 1.Transmit Data
Signal
SPI0_SS0_N O 3.3 V - 6 mA Slave Select Output.
Active Low. Hardware slave select signal.
SPI0_SS1_N O 3.3 V - 6 mA Slave Select Output.
Active Low. Hardware slave select signal.
SPI0_SS2_N O 3.3 V PU 6 mA Muxed with JESD1_CPCSB based on GPIO [0x060] misc
pin select register misc_pin_sel[9] = 1. Serial flash chip
select
SPI0_SS3_N O 3.3 V PU 6 mA Muxed with PLL_FD_OUT. Serial flash chip select
SPI 1 (without DMA function)
SPI_S1_SCLK O 3.3 V - 6 mA Serial flash input data
Muxed with JESD0_SCLK based on GPIO [0x060] misc
pin select register misc_pin_sel[9] = 1
SPI_S1_TXD I/O 3.3 V PU 6 mA Serial flash output data
Muxed with GPIO30 refer to Table 13-1.
Muxed with JESD0_CMOSI based on GPIO[0x060] misc
pin select register misc_pin_sel[9] = 1
SPI_S1_RXD I/O 3.3 V PU 6 mA Serial flash clock
Muxed with GPIO31 refer to Table 13-1.
Muxed with JESD0_CMISO based on GPIO[0x060] misc
pin select register misc_pin_sel[9] = 1
SPI_S1_SS0_N I/O 3.3 V PU 6 mA Serial flash chip select
SPI_S1_SS1_N I/O 3.3 V PU 6 mA SPI_S1_SS0_N muxed with GPIO18
SPI_S1_SS1_N muxed with GPIO19/JESD0_CPCSB,refer
to Table 13-1

Table 3-9 UART Signals

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
UART0 (with DMA function)
UART0_RX I 3.3 V Yes - Receive data
UART0_TX O 3.3 V Yes - 12 mA Transmit data
UART0_RTS_N I/O 3.3 V Yes PU 12 mA Muxed with GPIO20
Request To Send
UART0_CTS_N I/O 3.3 V Yes PU 12 mA Muxed with GPIO21
Clear To Send
UART1 (without DMA function)
UART_S1_RX I 3.3 V Yes PU 12 mA Muxed with GPIO22.
Receive data
UART_S1_TX O 3.3 V Yes PU 12 mA Muxed with GPIO23.
Transmit data

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Table 3-10 GPIO Signals

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
GPIO00 I/O 3.3 V Yes PU 12 mA General Purpose Input Output
GPIO01 I/O 3.3 V Yes PU 12 mA General Purpose Input Output
GPIO02 I/O 3.3 V Yes PU 12 mA General Purpose Input Output
GPIO03 I/O 3.3 V Yes PU 12 mA General Purpose Input Output
GPIO04 I/O 3.3 V Yes PU 12 mA General Purpose Input Output
GPIO05 I/O 3.3 V Yes PU 12 mA General Purpose Input Output
GPIO06 I/O 3.3 V Yes PU 12 mA General Purpose Input Output
GPIO07 I/O 3.3 V Yes PU 12 mA General Purpose Input Output
GPIO08 I/O 3.3 V Yes PU 12 mA General Purpose Input Output
GPIO09 I/O 3.3 V Yes PU 12 mA General Purpose Input Output

Table 3-11 USIM Signals

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
USIM_SCIO I/O 3.3 V – PD – Open Drain

Table 3-12 USB Signals

Signal Name Direction I/O 5V Tolerant Strength Description
USB_DP I/O - Yes – Differential data signal
USB_DM I/O - Yes –
USB_REXT I/O 3.3 V - – External resistor (REXT) 43.2 Ω (± 1%)
USB_ATEST I/O 3.3 V - – Test Point for DC Points Probes Inside the PHY (VDD_PLL
= 1.8 V)
USB_VBUS I - Yes – USB 5V Power Supply Pin
USB_ID I 3.3 V - – USB Mini-Receptacle Identifier

Table 3-13 RPDIF 0 (JESD207) Signals

Signal Name Direction I/O PU/PD Strength Description
RPDIF0_MCLK I 2.5 V PD master clock input for the Rx data path
RPDIF0_FBCLK O 2.5 V - 5 mA FCLK is a signal is a loop back version of MCLK
RPDIF0_TXNRX O 2.5 V - 5 mA The level on TXNRX controls the direction
of the transfer burst.
RPDIF0_ENABLE O 2.5 V - 5 mA Single cycle to indicate the start of each burst, and
subsequently asserted a second time for a single cycle to
indicate the end of each burst.
RPDIF0_DIQ0_0 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ0_1 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ0_2 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred

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Table 3-13 RPDIF 0 (JESD207) Signals (Continued)

Signal Name Direction I/O PU/PD Strength Description
RPDIF0_DIQ0_3 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ0_4 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ0_5 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ0_6 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ0_7 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ0_8 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ0_9 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ0_10 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ0_11 I/O 2.5 V PD 5 mA Port0 data lines that carry data samples being transferred
RPDIF0_DIQ1_0 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_1 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_2 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_3 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_4 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_5 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_6 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_7 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_8 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_9 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_10 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_DIQ1_11 I/O 2.5 V PD 5 mA Port1 data lines that carry data samples being transferred
RPDIF0_TX_FRAME O 2.5 V - 5 mA Control signal identifies framing for the TX data path
RPDIF0_RX_FRAME I 2.5 V - - Control signal identifies framing for the RX data path

Table 3-14 RPDIF 1 (JESD207 LVDS) Signals

Signal Name Direction I/O PU/PD Strength Description
RPDIF1_TXNRX O 2.5 V - 5 mA The level on TXNRX controls the direction
of the transfer burst.
RPDIF1_ENABLE O 2.5 V - 5 mA Single cycle to indicate the start of each burst, and
subsequently asserted a second time for a single cycle to
indicate the end of each burst.
RPDIF1_TX_P0 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_TX_P1 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_TX_P2 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_TX_P3 I/O - - - Differential Port0 data lines that carry data samples being
transferred

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Table 3-14 RPDIF 1 (JESD207 LVDS) Signals (Continued)

Signal Name Direction I/O PU/PD Strength Description
RPDIF1_TX_P4 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_TX_P5 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_TX_M0 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_TX_M1 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_TX_M2 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_TX_M3 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_TX_M4 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_TX_M5 I/O - - - Differential Port0 data lines that carry data samples being
transferred
RPDIF1_RX_P0 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_P1 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_P2 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_P3 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_P4 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_P5 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_M0 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_M1 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_M2 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_M3 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_M4 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_RX_M5 I/O - - - Differential Port1 data lines that carry data samples being
transferred
RPDIF1_MCLK_P I - - -
RPDIF1_MCLK_M I - - -
RPDIF1_FBCLK_P O - - -
RPDIF1_FBCLK_M O - - -
RPDIF1_TX_FRAME_P O - - -

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Table 3-14 RPDIF 1 (JESD207 LVDS) Signals (Continued)

Signal Name Direction I/O PU/PD Strength Description
RPDIF1_TX_FRAME_M O - - -
RPDIF1_RX_FRAME_P I - - -
RPDIF1_RX_FRAME_M I - - -
LVDS_EXTRES I/O - - - Pull down to Ground with external resistor 4.3 KΩ (±1%).

Table 3-15 JTAG Signals

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
ARM JTAG
JTAG0_TCK I 3.3 V Yes PU - ARM Debug JTAG clock / ATE APB
Interface clock
JTAG0_TDI I 3.3 V Yes PU - ARM Debug JTAG TDI / ATE APB Interface
Enable
JTAG0_TRST_N I 3.3 V Yes PU - ARM Debug JTAG TRSTN
JTAG0_TMS I 3.3 V Yes PU - ARM Debug JTAG TMS
JTAG0_TDO O 3.3 V Yes 6 mA ARM Debug JTAG TDO
CEVA JTAG
JTAG1_TCK I 3.3 V Yes PU - Ceva Subsystem/SerDes/DDR Debug
JTAG clock
JTAG1_TDI I 3.3 V Yes PU - Ceva/SerDes/DDR Debug JTAG TDI
JTAG1_TRST_N I 3.3 V Yes PU - Ceva/SerDes/DDR Debug JTAG TRSTN
JTAG1_TMS I 3.3 V Yes PU - Ceva/SerDes/DDR Debug JTAG TMS
JTAG1_TDO O 3.3 V Yes - 6 mA Ceva/SerDes/DDR Debug JTAG TDO

Table 3-16 SerDes0 for PCIe0 (4x) Signals

Signal Name Direction I/O PU/PD Strength Description
S0_TXP_0 O - - - Differential transmit signal
S0_TXM_0 O - - -
S0_RXP_0 I - - - Differential receive signal
S0_RXM_0 I - - -
S0_TXP_1 O - - - Differential transmit signal
S0_TXM_1 O - - -
S0_RXP_1 I - - - Differential receive signal
S0_RXM_1 I - - -
S0_TXP_2 O - - - Differential transmit signal
S0_TXM_2 O - - -
S0_RXP_2 I - - - Differential receive signal
S0_RXM_2 I - - -

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Table 3-16 SerDes0 for PCIe0 (4x) Signals (Continued)

Signal Name Direction I/O PU/PD Strength Description
S0_TXP_3 O - - - Differential receive signal
S0_TXM_3 O - - -
S0_RXP_3 I - - - Differential receive signal
S0_RXM_3 I - - -
S0_APROBE O - - - Analog DC test pad - used for bench and ATE testing
S0_REFCLKP I - - - Differential input refclk
S0_REFCLKM I - - -

Table 3-17 SerDes1 for CPRI or SGMII or PCIe Signals

Signal Name Direction I/O PU/PD Strength Description
S1_TXP O - - - Differential transmit signal
S1_TXM O - - -
S1_RXP I - - - Differential receive signal
S1_RXM I - - -
S1_APROBE O - - - Analog DC test pad - used for bench and ATE testing
S1_REFCLKP I - - - Differential input refclk
S1_REFCLKM I - - -
SRDS0_REFCLK O 3.3 V 18mA SerDes output refclk - used for synchronous SGMII

Table 3-18 Test and Misc Signals

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
UP_XI I 2.5 V - - - 12 MHz crystal In/Out or 12/19.2/24/48
MHz external clock oscillator source. (for
UP_XO I 2.5 V - - -
USB)
PS_XI I 1.8 V - - - 19.2/25/26/40 MHz Crystal In/Out (for
PCIe+system PLL)
PS_XO O 1.8 V - - -

RESET_N I 3.3 V - - - EXT HW Reset (active low)

TESTMODE_N I 3.3 V - PU -
TM_SEC_EN I 3.3 V - PU - Secure mode enable, this pin value will be
overridden by eFuse bit[31] secure enable
mode once set.

SCANMODE I 3.3 V - PD - Test pin, reserved to enable scan mode.

SCANEN I 3.3 V - PD - Test pin, reserved to enable scan-shift
BSCANMODE I 3.3 V - PD - Test pin, reserved to enable chip boundary
scan.
TRISTATE I 3.3 V - PD - Test pin, reserved to tri-state chip outputs.

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Table 3-19 Efuse Signals

Signal Name Direction I/O PU/PD Strength Description
FSOURCE_0 I 1.5 V - - Fsource Power pins max current:
FSOURCE_1 I 1.5 V - - Program current :
7mA (@nn,vdd=1.0v, 25oc)
FSOURCE_ID I 1.5 V - -
Sense current:
FSOURCE_MBIST I 1.5 V - -
4.72mA (unblown) (@nn,vdd=1.0v, 25oc)
4.03mA (blown) @nn,vdd=1.0v, 25oc)

Table 3-20 Radio Timer Signals

Signal Name Direction I/O PU/PD Strength Description
FRAME_CLK I 3.3 V - - External clock input for debugging radio frame timers.
FRAME_SYNC I 3.3 V - - External frame synchronization signal. Used as PPS input
clock to synchronize the internal radio frame timers for
TDD operation.
PPS_CLK I/O 3.3 V PD 6 mA Output 1sec clock from TSU block

Table 3-21 Thermal Signals

Signal Name Direction I/O 5V Tolerant PU/PD Strength Description
CATHOD_TH I/O 1.8 V - - - External Thermal Diode Measurement
Chip, Cathode
ANODE_TH I/O 1.8 V - - - External Thermal Diode Measurement
Chip, Anode

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3.3 Power and Ground

Table 3-22 shows the power and ground contacts.

Table 3-22 Power and Ground

Signal Name Description
VDD Core Voltage, 1.1 V
VSS Core Ground. 0V
VDDP_1P8 Pre-Driver Voltage, 1.8 V
VDDO_2P5 I/O Voltage, 2.5 V
VDDO_3P3 I/O Voltage, 3.3 V
PA_AVDD1 SerDes I/O Voltage 1, 1.1 V
PA_AVDD2 SerDes I/O Voltage 2, 1.8 V
PA_AVDD3 SerDes I/O Voltage 3, 2.5 V
VDDO_USIM USIM I/O Voltage, 1.8 V or 3.3 V
DDR_VDDQ DDR3 I/O Voltage, 1.5 V
DDR_VREF DDR3 I/O Reference Voltage, 0.75 V
AVDD33V USB Analog Voltage, 3.3 V
AVSS_USB Analog Ground, 0 V
AVDD11V USB Analog Voltage, 1.1 V
AVDD18V RPDIF1 LVDS Analog Voltage, 1.8 V
AVSS18V RPDIF1 LVDS Analog Ground, 0 V
VDDA1P8_TH Thermal Diode Voltage, 1.8 V
VSSA_TH Thermal Diode Ground, 0 V
DDR_PLL_VDD DDR PLL Voltage, 1.8 V
DDR_PLL_VSS DDR PLL Ground, 0 V
AVDD_CORE_PLL System PLL0 Analog Voltage, 1.1 V
AVSS_CORE_PLL System PLL0 Analog Ground, 0 V

3.4 Unused Interface Termination

The Transcede 2xxx has unused interface signals. This section describes how to terminate the unused interface
signals, including the following:
• Unused TDM Bus Signals
• Unused SPI Bus Signals
• Unused Radio Timer Signals
• Unused SerDes Signals
• Unused RGMII Signals
• Unused TSU Signals
• Unused RPDIF CMOS Bus Signals
• Unused RPDIF LVDS Bus Signals

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• Unused USB Signals

• Unused USIM Signals
• Unused eFuse Signals
• Unused Trace Bus Signals

3.4.1 Unused TDM Bus Signals

Table 3-23 lists the unused TDM bus signals.

Table 3-23 Unused TDM Bus Signals

Ball Name Signal Name Termination
GPIO10 TDM0_CK Can be used as GPIO10 or no connect if not used
GPIO11 TDM0_FS Can be used as GPIO11 or no connect if not used
TDM0_DX TDM0_DX no connect is OK
TDM0_DR TDM0_DR Connect to 100 Ω pull-down
GPIO12 TDM1_CK Can be used as GPIO12 or no connect if not used
GPIO13 TDM1_FS Can be used as GPIO13 or no connect if not used
TDM1_DX TDM1_DX No connect is OK
TDM1_DR TDM1_DR Connect to 100 Ω pull-down

3.4.2 Unused SPI Bus Signals

Table 3-24 lists the unused SPI bus signals.

Table 3-24 Unused SPI Bus Signals

Ball Name Signal Name Termination
SPI0_SCLK SPI0_SCLK No connect is OK
SPI0_RXD SPI0_RXD Connect to 100 Ω pull-down
SPI0_TXD SPI0_TXD No connect is OK
SPI0_SS0_N SPI0_SS0_N No connect is OK
SPI0_SS1_N SPI0_SS1_N No connect is OK
SPI0_SS2_N SPI0_SS2_N No connect is OK
SPI0_SS3_N SPI0_SS3_N No connect is OK
SPI_S1_SCLK SPI_S1_SCLK No connect is OK
SPI_S1_TXD SPI_S1_TXD Can be used as GPIO30 or No connect if not used
SPI_S1_RXD SPI_S1_RXD Can be used as GPIO31 or No connect if not used
SPI_S1_SS0_N SPI_S1_SS0_N Can be used as GPIO18 or No connect if not used
SPI_S1_SS1_N SPI_S1_SS1_N Can be used as GPIO19 or No connect if not used

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3.4.3 Unused Radio Timer Signals

Table 3-25 lists the unused radio timer signals.

Table 3-25 Unused Radio Timer Signals

Ball Name Signal Name Termination
FRAME_CLK FRAME_CLK Connect to 5K pull-up to 3.3 V (can be shared)
FRAME_SYNC FRAME_SYNC Connect to 5K pull-up to 3.3 V (can be shared)
PPS_CLK PPS_CLK No connect is OK

3.4.4 Unused SerDes Signals

Table 3-26 lists the unused SerDes signals.

Table 3-26 Unused SerDes Signals

Ball Name Signal Name Termination
S0_REFCLKP S0_REFCLKP Connect to 5K pull-up to PA_VDD2 (recommend not shared)
S0_REFCLKM S0_REFCLKM Connect to 100 Ω pull-down (recommend not shared)
S0_TXP S0_TXP No connect is OK
S0_TXM S0_TXM No connect is OK
S0_RXP S0_RXP Connect to 5K pull-up to PA_VDD2 (recommend not shared)
S0_RXM S0_RXM Connect to 100 Ω pull-down (recommend not shared)
SRDS0_REFCLK SRDS0_REFCLK No connect is OK
S1_REFCLKP S1_REFCLKP Connect to 5K pull-up to PA_VDD2 (recommend not shared)
S1_REFCLKM S1_REFCLKM Connect to 100 Ω pull-down (recommend not shared)
S1_TXP S1_TXP No connect is OK
S1_TXM S1_TXM No connect is OK
S1_RXP S1_RXP Connect to 5K pull-up to PA_VDD2 (recommend not shared)
S1_RXM S1_RXM Connect to 100 Ω pull-down (recommend not shared)
SRDS1_REFCLK SRDS1_REFCLK No connect is OK

3.4.5 Unused RGMII Signals

Table 3-27 lists the unused RGMII signals.

Table 3-27 Unused RGMII Signals

Ball Name Signal Name Termination
GEM0_REFCLK GEM0_REFCLK(SGMII) No connect is OK
GEM1_REFCLK GEM1_REFCLK No connect is OK
GEM1_RXC GEM1_RXC Connect to 5K pull-up to 2.5 V
RGMII_REFCLK RGMII_REFCLK Connect to 5K pull-up to 2.5 V
GEM1_RX_CTL GEM1_RX_CTL Connect to 100 Ω pull-down (can be shared)
GEM1_RXD0 GEM1_RXD0 Connect to 100 Ω pull-down (can be shared)

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Table 3-27 Unused RGMII Signals (Continued)

Ball Name Signal Name Termination
GEM1_RXD1 GEM1_RXD1 Connect to 100 Ω pull-down (can be shared)
GEM1_RXD2 GEM1_RXD2 Connect to 100 Ω pull-down (can be shared)
GEM1_RXD3 GEM1_RXD3 Connect to 100 Ω pull-down (can be shared)
GEM1_TXC GEM1_TXC No connect is OK
GEM1_TX_CTL GEM1_TX_CTL No connect is OK
GEM1_TXD0 GEM1_TXD0 No connect is OK
GEM1_TXD1 GEM1_TXD1 No connect is OK
GEM1_TXD2 GEM1_TXD2 No connect is OK
GEM1_TXD3 GEM1_TXD3 No connect is OK

3.4.6 Unused TSU Signals

Table 3-28 lists the unused TSU signals.

Table 3-28 Unused TSU Signals

Ball Name Signal Name Termination
TSU_VCXO_CLK TSU_VCXO_CLK Connect to 100 Ω pull-down (can be shared)
TSU_NTG_CLKOUT TSU_NTG_CLKOUT No connect is OK

3.4.7 Unused RPDIF CMOS Bus Signals

Table 3-29 lists the unused RPDIF CMOS bus signals.

Table 3-29 Unused RPDIF CMOS Bus Signals

Ball Name Signal Name Termination
RPDIF0_MCLK RPDIF0_MCLK Connect to 100 Ω pull-down
RPDIF0_FBCLK RPDIF0_FBCLK No connect is OK
RPDIF0_TXNRX RPDIF0_TXNRX No connect is OK
RPDIF0_ENABLE RPDIF0_ENABLE No connect is OK
RPDIF0_TX_FRAME RPDIF0_TX_FRAME No connect is OK
RPDIF0_RX_FRAME RPDIF0_RX_FRAME Connect to 100 Ω pull-down
RPDIF0_DIQ0_0 RPDIF0_DIQ0_0 No connect is OK
RPDIF0_DIQ0_1 RPDIF0_DIQ0_1 No connect is OK
RPDIF0_DIQ0_2 RPDIF0_DIQ0_2 No connect is OK
RPDIF0_DIQ0_3 RPDIF0_DIQ0_3 No connect is OK
RPDIF0_DIQ0_4 RPDIF0_DIQ0_4 No connect is OK
RPDIF0_DIQ0_5 RPDIF0_DIQ0_5 No connect is OK
RPDIF0_DIQ0_6 RPDIF0_DIQ0_6 No connect is OK
RPDIF0_DIQ0_7 RPDIF0_DIQ0_7 No connect is OK

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Table 3-29 Unused RPDIF CMOS Bus Signals (Continued)

Ball Name Signal Name Termination
RPDIF0_DIQ0_8 RPDIF0_DIQ0_8 No connect is OK
RPDIF0_DIQ0_9 RPDIF0_DIQ0_9 No connect is OK
RPDIF0_DIQ0_10 RPDIF0_DIQ0_10 No connect is OK
RPDIF0_DIQ0_11 RPDIF0_DIQ0_11 No connect is OK
RPDIF0_DIQ1_0 RPDIF0_DIQ1_0 No connect is OK
RPDIF0_DIQ1_1 RPDIF0_DIQ1_1 No connect is OK
RPDIF0_DIQ1_2 RPDIF0_DIQ1_2 No connect is OK
RPDIF0_DIQ1_3 RPDIF0_DIQ1_3 No connect is OK
RPDIF0_DIQ1_4 RPDIF0_DIQ1_4 No connect is OK
RPDIF0_DIQ1_5 RPDIF0_DIQ1_5 No connect is OK
RPDIF0_DIQ1_6 RPDIF0_DIQ1_6 No connect is OK
RPDIF0_DIQ1_7 RPDIF0_DIQ1_7 No connect is OK
RPDIF0_DIQ1_8 RPDIF0_DIQ1_8 No connect is OK
RPDIF0_DIQ1_9 RPDIF0_DIQ1_9 No connect is OK
RPDIF0_DIQ1_10 RPDIF0_DIQ1_10 No connect is OK
RPDIF0_DIQ1_11 RPDIF0_DIQ1_11 No connect is OK

3.4.8 Unused RPDIF LVDS Bus Signals

Table 3-30 lists the unused RPDIF LVDS bus signals.

Table 3-30 Unused RPDIF LVDS Bus Signals

Ball Name Signal Name Termination
RPDIF1_TXNRX RPDIF1_TXNRX No connect is OK
RPDIF1_ENABLE RPDIF1_ENABLE No connect is OK
RPDIF1_TX_P0 RPDIF1_TX_P0 No connect is OK
RPDIF1_TX_P1 RPDIF1_TX_P1 No connect is OK
RPDIF1_TX_P2 RPDIF1_TX_P2 No connect is OK
RPDIF1_TX_P3 RPDIF1_TX_P3 No connect is OK
RPDIF1_TX_P4 RPDIF1_TX_P4 No connect is OK
RPDIF1_TX_P5 RPDIF1_TX_P5 No connect is OK
RPDIF1_TX_M0 RPDIF1_TX_M0 No connect is OK
RPDIF1_TX_M1 RPDIF1_TX_M1 No connect is OK
RPDIF1_TX_M2 RPDIF1_TX_M2 No connect is OK
RPDIF1_TX_M3 RPDIF1_TX_M3 No connect is OK
RPDIF1_TX_M4 RPDIF1_TX_M4 No connect is OK
RPDIF1_TX_M5 RPDIF1_TX_M5 No connect is OK
RPDIF1_RX_P0 RPDIF1_RX_P0 No connect is OK
RPDIF1_RX_P1 RPDIF1_RX_P1 No connect is OK

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Table 3-30 Unused RPDIF LVDS Bus Signals (Continued)

Ball Name Signal Name Termination
RPDIF1_RX_P2 RPDIF1_RX_P2 No connect is OK
RPDIF1_RX_P3 RPDIF1_RX_P3 No connect is OK
RPDIF1_RX_P4 RPDIF1_RX_P4 No connect is OK
RPDIF1_RX_P5 RPDIF1_RX_P5 No connect is OK
RPDIF1_RX_M0 RPDIF1_RX_M0 No connect is OK
RPDIF1_RX_M1 RPDIF1_RX_M1 No connect is OK
RPDIF1_RX_M2 RPDIF1_RX_M2 No connect is OK
RPDIF1_RX_M3 RPDIF1_RX_M3 No connect is OK
RPDIF1_RX_M4 RPDIF1_RX_M4 No connect is OK
RPDIF1_RX_M5 RPDIF1_RX_M5 No connect is OK
RPDIF1_MCLK_P RPDIF1_MCLK_P Connect to 5K pull-up to 1.8 V (recommend not shared)
RPDIF1_MCLK_M RPDIF1_MCLK_M Connect to 100 Ω pull-down (recommend not shared)
RPDIF1_FBCLK_P RPDIF1_FBCLK_P No connect is OK
RPDIF1_FBCLK_M RPDIF1_FBCLK_M No connect is OK
RPDIF1_TX_FRAME_P RPDIF1_TX_FRAME_P No connect is OK
RPDIF1_TX_FRAME_M RPDIF1_TX_FRAME_M No connect is OK
RPDIF1_RX_FRAME_P RPDIF1_RX_FRAME_P Connect to 5K pull-up to 1.8 V (recommend not shared)
RPDIF1_RX_FRAME_M RPDIF1_RX_FRAME_M Connect to 100 Ω pull-down (recommend not shared)

3.4.9 Unused USB Signals

Table 3-31 lists the unused USB signals.

Table 3-31 Unused USB Signals

Ball Name Signal Name Termination
USB_DP USB_DP Connect to 5K pull-up to 3.3 V (recommend not shared)
USB_DM USB_DM Connect to 100 Ω pull-down (recommend not shared)
USB_REXT USB_REXT No connect is OK
USB_ATEST USB_ATEST No connect is OK
USB_VBUS USB_VBUS No connect is OK
USB_ID USB_ID No connect is OK

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3.4.10 Unused USIM Signals

Table 3-32 lists the unused USIM signals.

Table 3-32 Unused USIM Signals

Ball Name Signal Name Termination
USIM_SCIO USIM_SCIO No connect is OK
GPIO12 USIM_RST_N Can be used as GPIO12 or No connect if not used
GPIO13 USIM_VSEL33 Can be used as GPIO13 or No connect if not used
TDM1_DX USIM_CLK No connect is OK
TDM1_DR USIM_DETECT Connect to 100 Ω pull-down
EXP_CS3_N USIM_FCB Connect to 5K pull-up to 3.3 V (recommend not shared)

3.4.11 Unused eFuse Signals

Table 3-33 lists the unused eFuse signals.

Table 3-33 Unused eFuse Signals

Ball Name Signal Name Termination
FSOURCE_0 FSOURCE_0 VSS
FSOURCE_1 FSOURCE_1 VSS
FSOURCE_ID FSOURCE_ID VSS
FSOURCE_MBIST FSOURCE_MBIST VSS

3.4.12 Unused Trace Bus Signals

All trace bus signals are output, so no connect is OK.

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4 DDR3 Memory Sub-system
This chapter details the DDR3 SDRAM interface and DDR3 SDRAM controller.

4.1 Feature List

• One DDR3 Memory Controller.
• DDR3 Memory Controller is programmable for DDR3 Synchronous Dynamic Random Access Memory
(SDRAM) timing parameters and memory size.
• DDR3 SDRAM interface controls data flow to and from the DDR3 SDRAM memory in burst mode.
• DDR3 Memory Controller has four AXI ports:
– Port 0 connects to System Bus Matrix.
– Port 1 connects to System Bus Matrix.
– Port 2 connects to Ceva Group Bus Matrix.
– Port 3 connects directly to Cortex-A9 M1 port.
All groups have access to DDR3 controller through System Bus Matrix.
• Comply with the JESD79-3B standards.
• Support up to DDR3-1.6Gbps.
• DDR3 SDRAM Data Bus is 32 bits wide and supports two x16 DDR3 parts or four x8 DDR3 parts.
• Fly-by routing.

4.2 Implementation Details

The address space of the DDR3 memories are from 0x0000_0000 to 0xDFFF_FFFF (3.75 GByte maximum
addressable space).
In SYS Config, two registers define DDR3 access windows, as shown in Table 4-1. They need to be configured
after reset.

Table 4-1 DDR3 Access Window Control Registers

Register Location
Destination Register Name Description
(CFG_SYS)
DDR3 Controller ddr_ll_reg Low limit of the window to DDR3 controller. 0xF4C0_0010
bit [15:4]
ddr_hl_reg High limit of the window to DDR3 controller. 0xF4C0_0010
bit [31:20]

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4.3 Transcede 2xxx DDR3 SDRAM Interface Timing

Figure 4-1 and Table 4-2 present the Transcede 2xxx DDR3 SDRAM interface timing and specifications.
Figure 4-1 Transcede 2xxx DDR3 SDRAM Interface Bus Timing

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Table 4-2 Transcede 2xxx DDR3 SDRAM Interface AC Timing Specification

Symbol Parameter Min Typ Max Units Reference

CLK Clock frequency 400 — 800 MHz —

- Clock jitter –80 — +80 ps —

CH, CL Clock high-level or low-level width 0.47 — 0.53 clk CLK

ID Address and control output ready 600 — 1000 ps CLK rising

DQSS First DQS output 0.75 — 1.25 clk CLK rising

DSS DQS output falling edge setup time 0.25 — — clk CLK rising

DSH DQS output falling edge hold time 0.25 — — clk CLK rising

DQSH DQS output high pulse width 0.45 — 0.55 clk —

DQSL DQS output low pulse width 0.45 — 0.55 clk —

WPRE DQS output preamble 1 — — clk DQS rising

DS DQ and DQM output setup time 125 — 175 ps DQS rising/falling

DH DQ and DQM output hold time 125 — 175 ps DQS rising/falling

RPRE DQS input preamble 0.9 — — clk DQS rising

DQSQ DQ input setup time — — 120 ps DQS rising/falling

QH DQ input hold time 0.38 — — clk DQS rising/falling

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4.4 DDR3 SDRAM Device Interface Timing

The timing requirements in Figure 4-2 and Table 4-3 fit the standard DDR3 SDRAM devices with clock rates of 800
MHz.
Figure 4-2 DDR3 SDRAM Device Interface Bus Timing

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Table 4-3 DDR3 SDRAM Device Interface AC Timing Requirements

Symbol Parameter Min Typ Max Units Reference

CLK Clock frequency 400 — 800 MHz —

CH, CL Clock high-level or low-level width 0.47 — 0.53 CLK CLK

IS Address and control input setup time 170 — — ps CLK rising

IH Address and control input hold time 120 — — ps CLK rising

DQSS First DQS input 0.75 — 1.25 clk CLK rising

DSS DQS input falling edge setup time 0.18 — — clk CLK rising

DSH DQS input falling edge hold time 0.18 — — clk CLK rising

DQSH DQS input high pulse width 0.45 — 0.55 clk —

DQSL DQS input low pulse width 0.45 — 0.55 clk —

WPRE DQS input write preamble 0.9 — — clk DQS rising

DS DQ and DQM input setup time 10 — — ps DQS rising/falling

DH DQ and DQM input hold time 45 — — ps DQS rising/falling

RPRE DQS output preamble 0.9 — — clk DQS rising

DQSQ DQS-DQ output skew — — 100 ps DQS rising/falling

QH DQS-DQ output hold time 0.38 — — clk DQS rising/falling

Notes:
1. Test Conditions: VDD = 1.1 VDC± 5%
2. Output load: The maximum capacitive load to meet SDRAM timing requirements is 30pF.

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5 SerDes for CPRI, PCIe or SGMII
This chapter describes features of SerDes.

5.1 Feature List

The Transcede 2xxx device provides support for CPRI, PCIe or SGMII through a SerDes interface, configurable
through bootstraps.

NOTE: SerDes for CPRI is supported for Transcede 2120, Transcede 2150, and Transcede
2200.
See Section 2.3, Bootstraps, on page 31 for the configuration.

• 1- 6.1 Gbps Multi-Standard 1-lane SerDes

– PCIe: support 1.1 and 2.0
– CPRI: support for CPRI 4.1
– SGMII: support only 1Gbs
• Include Physical Coding Sub-layer (PCS) layer which is not used (controller PCS is used)
• Support various test mode options

5.2 Supported Standards

The PHY Layer IP supports the following list of serial standards.
Level 1 Standards- Fully Supported:
• PCI Express Gen1/Gen2 Electrical compliance for PCI Express® Base Specification Revision 2.0, December
20, 2006.XFI (INF-8077i, Revision 4.5, 31/August/2005)
• SGMII (1.25 Gbps)
• CPRI Specification Version 4.1 (TX 10G-Base-KR electrical interface, IEEE 802.3[22])

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6 Common Public Radio Interface
(CPRI)
This chapter introduces the features and implementation details of CPRI for Transcede 2120, Transcede 2150, and
Transcede 2200.

NOTE: CPRI is for Transcede 2120, Transcede 2150, and Transcede 2200.

6.1 Feature List

The CPRI functions as an open standard of digital interface between the baseband processing and radio
transceiver in the base station.

6.1.1 General Features

• Compliant to Common Public Radio Interface Version 4.1
– UTRA-FDD Support (UMTS/WCDMA)
– E-UTRA Support (3GPP LTE)
• Support for REC only
• One full duplex interface
• CPRI interface supports up to 8 AxC containers: two for Tx/Rx, two for Multiple Input Multiple Output (MIMO),
two for 3G/LTE.
• CPRI Local or Remote configuration
• Operates in all of the following Baseband-to-RF interconnect topologies:
– Local interconnect using a central combiner/distributor topology
– Local interconnect using a full mesh topology
– Remote interconnect using a point-to-point (P2P) star topology
– Remote interconnect using a tree and branch topology
– Remote interconnect using a chain topology
– Remote interconnect using a ring topology
• Each design instance supports one Serial link at any of he following rates:
– 614.4 Mbit/s
– 1228.8 Mbit/s
– 2457.6 Mbit/s
– 3.072 Gbit/s
– 4.9152 Gbit/s with scrambling
– 6.144 Gbit/s with scrambling
• Supports the following features on a per instance base:
– Configuration and Control and Monitoring

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– Delay Measurement and Control

– Test capability
– Supports CPRI Basic Frame and Hyper frame structures
– Supports multiplexing of the following Hyper frame in-band sub-channels:
• Radio Frame Synchronization data
• L1 In-band Protocol data
• Slow Control and Management (C&M) HDLC data
• Fast Control and Management (C&M) Ethernet data
• Reserved fields
• Vendor-Specific Sub channels (VSS) data
• The 32-bits data path enables low rate core clock

6.1.2 AxC Mapping

• Application IQ mapping block supports buffering and mapping of IQ radio data into payloads for transport over
the links.
• Supports application mapping of user data to the CPRI payload using programmable sample widths of 15bits
or 16 bits for both uplink and downlink. Other sample sizes are not currently supported as direct mapping into
the basic frame. However any sample width of 16 bits or lower is supported and transported the 16-bits
envelope.
• Link capacity in terms of maximum AxC carriers based on 16-bits/15-bits sample width.

6.1.3 Control and Management (C&M) Channel Processing

• Supports on-chip termination of the CPRI Slow Control and Management (C&M) channels using an embedded
HDLC controller.
• Supports mapping of Ethernet frame-encapsulated Control and Management (C&M) information into a Fast
C&M Channel as per the CPRI specification. Ethernet frames are 4B/5B encoded and decoded as specified in
IEEE 802.3-2002.
• Integrates IEEE 802.3 standardized external Ethernet Media Access Controller (MAC) 10/100 block with MII
interface.
• Integrates access to the Vendor Specific Sub-channel (VSS) and L1 Inband Sub-channel.

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6.2 CPRI System Block Diagram

Figure 6-1 shows an example of integrating one CPRI, CPDMA and AX12CPUIF. The AXI2CPUIF block transfers
requests from AXI format to CPUIF format of CPRI controller for register access.
Figure 6-1 CPRI System Block Diagram

external
clk2x calib clk Serdes TX Serdes RX

Clock
Divider

clkx clk2x

cpri clk cpri clk2x calib clk serdes rx clk

CPRI 4.1 Core

MAP Frame Timing CPU

APB Slave cpri clk cpri clk

CPDMA
AXI2CPUIF
(n AxC)
axi clk cpri clk

AXI Master To MDMA AXI Slave

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6.3 CPRI DMA

6.3.1 Feature List

• Supports for LTE Cyclic prefix
• Supports up to 8 TX and 8 RX AxC channels
• Template based DMA engine which supports symbol transfers

6.3.2 Functional Description

The CPDMA transfers data between system memory and MAP interface of the CPRI controller. On one side, the
CPDMA interfaces with AXI bus while on the other side, it interfaces with the 8 map channels of the CPRI
controller.
The map channels consist of both transmit (TX) and receive (RX) channels. The data for 8 TX channels is supplied
by an AXI read master with access controlled through a read arbiter. The data received through 8 RX channels is
transferred by an AXI write master with AXI access controlled through a write arbiter.
Each TX/RX channel consists of a MAP interface, four templates and a TX/RX FIFO. The control flow is handled by
a template control state machine on a per channel basis.

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Figure 6-2 shows the CPDMA block diagram.

Figure 6-2 CPDMA Block Diagram

TX DMA engines (8)

TX DMA engines (8)
Read TX DMA engines (8)
Channel TX DMA engines (8)
Arbiter TX DMA engines (8)
TX DMA engines (8)
TX DMA engines (8) 8 TX MAP
TX DMA engines (8)

Read
Request
Queue
(8)
AXI RD
AXI_GM_64

AXI WR
AXI_GM_64 Write
Request
Queue
(8)

TX DMA engines (8)

TX DMA engines (8)
Write TX DMA engines (8)
Channel TX DMA engines (8)
Arbiter TX DMA engines (8)
TX DMA engines (8)
TX DMA engines (8) 8 RX MAP
RX DMA engines (8)

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6.3.3 Template Based Control

The CPDMA control is based on the use of templates. Each TX or RX channel data flow is controlled by a Template
Sequence List (TSL) which specifies the template among the four templates to execute. Two of these four
templates are specific to that channel while two of these are common to a group. Each template consists of 4
descriptors. The CPDMA control flow is shown in Figure 6-3.
Figure 6-3 CPDMA AxC - Control Flow

Template 2 Template 3

Template 0
Template Reg 0
Template 1
Template Reg 1
Templates 2 and 3
4 Desc 4 Desc 4 Desc 4 Desc are common to 8
AxC

Template Mux

Template Sequence 4 Desc

List (TSL)
8 bit per entry
Current Template (D3, D2, D1, D0)

TSL entry 0
TSL entry 1 DMA data transfer
TSL entry 2 size
TSL entry 3 Desc 0
TSL entry 4 Descriptor symbol offset (16b)
TSL entry 5 Desc 1
TSL entry 6 Template exec. flow
TSL entry 7 exec. flow Desc 2 DMA data fetch
TSL entry 8 Desc 3 address
TSL entry 9 +
TSL entry 10
TSL entry 11
TSL entry 12 Base Pointer - Word aligned
TSL entry 13 (30b) + 2'b00
TSL entry 14
TSL entry 15 current symbol
Current Symbol Buffer Pointer buffer pointer
(CSBP)
(30b) + 2'b00

Short stride (16b)

Long stride (32b)

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6.3.3.1 TSL Entry Format

The template selection field selects the template to be executed among four possible templates. The Repeat bit
when set directs the control to loop back to the first entry. While the Move Current Symbol Buffer Pointer (CSBP) bit
indicates that the CSBP should be updated at the end of execution of the current template, the Stride Select
indicates whether to use long stride or the short stride register. The IRQEN bit specifies (when set to 1) whether to
generate an interrupt after the execution of this template entry. The TSL entry format is shown as in Figure 6-4.
Figure 6-4 TSL Entry Format (8 bit)

Template Next Stride Move Next

IRQEN Reserved (set to 0) Reserved Repeat
Selection Select CSBP
(1 bit) (1 bit) (1 bit) (1 bit)
(2 bit) (1 bit) (1 bit)

6.3.3.2 Template Format

Each template consists of 4 descriptors as shown below.
Figure 6-5 Template Format (128 bit)

Descriptor 3 Descriptor 2 Descriptor 1 Descriptor 0

6.3.3.3 Descriptor Format

Each descriptor consists of a 14 bit symbol offset and a 14 bit transfer size. Each of these fields are specified in
terms of words (4 bytes). The transfer control bit when set directs the transmit transfer source from a register and
makes the receiver discard the specified transfer size. The symbol offset is ignored when the transfer control bit is
set. Figure 6-6 shows the format of the descriptor.
Figure 6-6 Descriptor Format (32 bit)

Symbol Offset (14 bit) Transfer Transfer Size (14 bit)

in word (4B) resolution Control bit in word (4B) resolution

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6.3.4 Cyclic Prefix Support

Cyclic prefix is supported through the use of (offset, size) pairs within the descriptor in addition to the current
symbol pointer. The starting point of a transfer slice is the current symbol pointer plus the offset. The size specifies
the amount of data to be transferred for that particular slice. Figure 6-7 shows the cyclic prefix concept.
Figure 6-7 Cyclic Prefix Concept

symbol
pointer

Symbol

Pre

Pre Symbol

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6.3.5 Synchronized DMA Mode

Handshaking with the FFT/Ceva is used for transferring data without the involvement of ARM. Normally, the DMA
engine is started by ARM when it writes the start bit. Similarly, when the DMA completes, it sends an interrupt to
the ARM and sets the write bit. Instead of this, the FFT/Ceva would handshake with the CPDMA directly to initiate
data transfers. The synchronized DMA mode can be selected by configuring registers. The handshake is done on a
per symbol basis. Figure 6-8 shows the synchronized DMA mode.
Figure 6-8 Synchronized DMA Mode

Transmit (Downlink)
One signal group per AxC port
req (in)

ack (out)

Receive (Uplink) One signal group per AxC port

req (out)

ack (in)

6.3.5.1 Sync Mode in Downlink

The FFT/Ceva asserts req when it has a symbol ready to be transferred. The CPDMA waits until the req has been
asserted, then asserts the ack and begins data transfer. After the CPDMA has completed transferring the current
symbol, it samples the req to see it has been de-asserted. Once the req has been de-asserted, the CPDMA de-
asserts the ack and waits for the req to be asserted again to begin the next symbol transfer.

6.3.5.2 Sync Mode in Uplink

The CPDMA asserts the req when sync mode has been selected. The FFT/Ceva should assert the ack when it is
ready to receive the symbol. Then the CPDMA de-asserts the req and begins data transfer. At the end of the
transfer, the CPDMA waits until the ack has been de-asserted. Then CPDMA re-asserts the req again, waits for the
req to be asserted before transferring the next symbol.

6.3.5.3 Data Offset

The IQ data can be offset with respect to Radio Frame Sync on both the TX and RX directions by programming the
CPRI_MAP_OFFSET_TX / CPRI_MAP_OFFSET_RX registers inside the CPRI IP.

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6.3.5.4 MAP Interface

The CPDMA interfaces with the CPRI MAP interface in the synchronous mode in which the CPDMA and CPRI run
with the same CPRI clock. The TX and RX interface waveforms are shown in Figure 6-9.
Figure 6-9 Synchronous TX and RX MAP Interfaces

Synchronous TX MAP Interface

clk

cpri_map_tx_ready

cpri_map_tx_data

d0 d1 d2 d3

Synchronous RX MAP Interface

clk

cpri_map_rx_ready

cpri_map_rx_data

d0 d1 d2 d3

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6.3.6 CPDMA Usage Scenarios

Figure 6-10 and Figure 6-11 describes the CPDMA usage scenarios.
Figure 6-10 Symbols in CRAM

Base Pointer (BP)

Desc 0 -
Symbol 0- LCP
Desc 1 -
Symbol 0
Desc 2 - stride
Symbol 0
send const. data
Desc 3 -
NULL LCP
TSL entry 0 R=0 CSBP
R=0
TSL entry 1 R=1
Desc 0 -
Symbol 1- SCP Symbol 1
Desc 1 -
Symbol 1
Desc 2 - SCP
send const. data
Desc 3 -
NULL
R=1
LCP - Long Cyclic Prefix
SCP - Short Cyclic Prefix
CSBP - Current Symbol Buffer
Pointer
Figure 6-11 Symbols in DDR

Base Pointer (BP)

Desc 0 -
Symbol 0- LCP
Desc 1 -
Symbol 0
Desc 2 -
Symbol 0 stride
NULL
Desc 3 -
TSL entry 0 R=0 NULL LCP
TSL entry 1 R=0 R=0
TSL entry 2 R=0
TSL entry 3 R=0 Desc 0 -
Symbol 1- SCP Symbol 1
TSL entry 4 R=0 Desc 1 -
TSL entry 5 R=0 Symbol 1
TSL entry 6 R=1 Desc 2 - SCP
NULL
Desc 3 -
NULL
R=0

CSBP
R=0
Desc 0 - Symbol 6
Symbol 6- SCP
Desc 1 -
Symbol 6 SCP
Desc 2 -
NULL
Desc 3 -
NULL

R=1

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7 Peripheral Component
Interconnect Express (PCIe)
This chapter introduces the features and implementation details of PCI express.
The PCIe interface consists of two PCIe controllers supporting high speed data transfers through 4 or 1 lane. The
controller implements an AXI bridge that can initiate transactions as an AXI bus master or translate transactions as
an AXI slave on the PCIe bus.

7.1 Feature list

• PCI-SIG version 2.0
• Gen 2 link rates - 5.0 Gbps
• Root complex mode supported with direct connection to an end point (switch is not supported)
• End point mode supported
• Two PCIe controllers:
– One controller supports 4 or 1 lane.
– The second controller supports 1 lane only.

7.2 Channel AC Coupling Capacitors

Each Lane of a PCI Express Link must be AC coupled. Capacitors must be placed on the Transmitter side of an
interface that permits adapters to be plugged and unplugged. In a topology where everything is located on a single
substrate, the capacitors may be located anywhere along the channel. External capacitors are assumed.

7.3 Transmitter Specification

Table 7-1 defines the parameters for Transmitters. Parameters are defined separately for 2.5 Gbps and 5.0 Gbps
implementations.

Table 7-1 2.5 and 5.0 Gbps PCIe Gen2 Transmitter Specifications
Symbol Parameter 2.5 Gbps 5.0 Gbps Units Comments
Ul Unit Interval 399.88 (min) 199.94 (min) ps The specified Ul is equivalent to a tolerance of ±300
400.12 (max) 200.06 (max) ppm for each Refclk source. Period does not
account for SSC induced variations.
VTX-DIFF-PP Differential p-p Tx voltage 0.8 (min) 0.8 (min) V As measured with compliance test load. Defined as
swing 1.2 (max) 1.2 (max) 2*|VtXD+-- Vtxd- |.

VTX-DIFF-PP Low power differential p-p 0.4 (min) 0.4 (min) V As measured with compliance test load. Defined as
Tx voltage swing 1.2 (max) 1.2 (max) 2*|VtXD+-- Vtxd- |.

VTX-DE-RATIO-3.5dB Tx de-emphasis level ratio 3.0 (min) 3.0 (min) dB -

4.0 (max) 4.0 (max)

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Table 7-1 2.5 and 5.0 Gbps PCIe Gen2 Transmitter Specifications (Continued)
Symbol Parameter 2.5 Gbps 5.0 Gbps Units Comments
VTX-DE-RATIO-6dB Tx de-emphasis level N/A 5.5 (min) dB -
6.5 (max)
TMIN-PULSE Instantaneous lone pulse Not specified 0.9 (min) Ul Measured relative to rising/falling pulse.
width
TTX-EYE Transmitter Eye including 0.75 (min) 0.75 (min) Ul Does not include SSC or Refclk jitter. Includes Rj at
all jitter sources 10-12.
See Notes 2. 3, 4, and 10.
Note that 2.5 Gbps and 5.0 Gbps use different jitter
determination methods.
TTX-EYE-MEDIAN-to- Maximum time between 0 125 (max) Not specified Ul Measured differentially at zero crossing points after
MAX-JITTER the jitter median and max applying the 2.5 Gbps clock recovery function.
deviation from the median
TTX-HF-DJ-DD Tx deterministic jitter > 1.5 Not specified 0.15 (max) Ul Deterministic jitter only.
MHz
TTX-LF-RMS Tx RMS jitter< 1.5 MHz Not specified 3.0 ps Total energy measured over a 10 kHz-1.5 MHz
RMS range.

TTX-RISE-FALL Transmitter rise and fall 0 125 (min) 0.15 (min) Ul Measured differentially from 20% to 80% of swing.
time
TRF-MISMATCH Tx rise/fall mismatch Not specified 0.1 (max) Ul Measured from 20% to 80% differentially.
BWTX-PLL Maximum Tx PLL 22 (max) 16 (max) MHz Second order PLL jitter transfer bounding function.
bandwidth
BWTX-PLL-LO-3DB Minimum Tx PLL BW for 3 1.5 (min) 8 (min) MHz Second order PLL jitter transfer bounding function.
dB peaking
BWTX-PLL-LO-1DB Minimum Tx PLL BW for 1 Not specified 5 (min) MHz Second order PLL jitter transfer bounding function.
dB peaking
PKGTX-PLL1 Tx PLL peaking with 8 MHz Not specified 3.0 (max) dB Second order PLL jitter rransfer bounding function.
min BW
PKGTX-PLL2 Tx PLL peaking with 5 MHz Not specified 1.0 (max) dB -
min BW
RLTX-DIFF Tx package plus Si 10 (min) 10 (min) for dB -
differential return loss 0.05 -1.25 GHz
8 (min) for
1.25-2.5 GHz
RLTX-CM Tx package plus Si 6 (min) 6 (min) dB Measured over 0.05 — 1.25 GHz range for 2.5 Gbps
common mode return loss and 0.05 - 2.5 GHz range for 5.0 Gbps. (S11
parameter)
ZTX-DIFF-DC DC differential Tx 80 (min) 120 (max) (] Low impedance defined during signaling. Parameter
impedance 120 (max) is captured for 5.0 GHz by RLTX-DIFF.

VTX-CMA-C-PP Tx AC common mode Not specified 100 (max) mVPP -

voltage (5.0 Gbps)
VTX-CM-AC-P Tx AC common mode 20 Not specified mV -
voltage (2.5 Gbps)
ITX-SHORT Transmitter short-circuit 90 (max) 90 (max) mA The total current Transmitter can supply when
current limit shorted to ground.
VTX-DC-CM Transmitter DC common- 0 (min) 0 (min) V The allowed DC common-mode voltage at the
mode voltage 3.6 (max) 3.6 (max) Transmitter pins under any conditions

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Table 7-1 2.5 and 5.0 Gbps PCIe Gen2 Transmitter Specifications (Continued)
Symbol Parameter 2.5 Gbps 5.0 Gbps Units Comments
VTX-CM-DC-ACTIVE- Absolute Delta of DC 0 (min) 0 (min) mV |VTX-CM-DC-[during l0] - VTX-CM-Idle-DC[during Electrical
IDLE-DELTA Common Mode Voltage 100 (max) 100 (max) Idle]
during LO and Electrical
<= 100 mV
Idle.
VTX-CM-DC=DC(avg) of |VTX-D++VTX-D-|/2
VTX-CM--Idle-DC=DC(avg) of |VTX-D++VTX-D-|/2
VTX-CM-DC-LINE-DELTA Absolute Delta of DC 0 (min) 0 (min) mV |VTX-CM-DC-D+[during l0] - VTX-CM-DC-D[during l0]<= 25
Common Mode Voltage 25 (max) 25 (max) mV
between D+ and D- VTX-CM-DC-D+=DC(avg) of |VTX-D+| [during L0] VTX-CM-
DC-D-=DC(avg) of |VTX-D+| [during L0]

VTX-IDLE-DIFF-AC-p Electrical Idle Differential 0 (min) 0 (min) mV VTX-IDLE-DIFFp = | VTX-IDLE-D+ - VTX-IDLE-D-| <= 20 mV.
Peak Output Voltage 20 (max) 20 (max) Voltage must be high pass filtered to remove any DC
component.
VTX-IDLE-DIFF-DC DC Electrical Idle Not specified 0 (min) mV VTX-IDLE-DIFF-DC = | VTX-IDLE-D+ - VTX-IDLE-D-| <= 5
Differential Output Voltage 5 (max) mV.
Voltage must be low pass filtered to remove any AC
component. Filler characteristics complementary to
above.
VTX-RCV-DETECT The amount of voltage 600 (max) 600 (max) mV The total amount of voltage change in a positive
change allowed during direction that a Transmitter can apply to sense
Receiver Defection whether a low impedance Receiver is present.
Note: Receivers display substantially different
impedance for Vin <0 vs Vin > 0.
TTX-IDLE-MIN Minimum time spent in 20 (min) 20 (min) ns Minimum time a Transmitter must be in Electrical
Electrical Idle Idle.
TTX-IDLE-SET-TO-IDLE Maximum time to 8 (max) 8 (max) ns After sending the required number of ElOSs, the
transition to a valid Transmitter must meet all Electrical Idle
Electrical Idle after sending specifications within this time. This is measured
an EIOS from the end of the last UI of the last EIOS to the
Transmitter in Electrical Idle.
TTX-IDLE-TO-DIFF-DATA Maximum time to 8 (max) 8 (max) ns Maximum time to transition to valid diff signaling
transition to valid diff after leaving Electrical Idle. This is considered a
signaling after leaving debounce time to the Tx.
Electrical Idle
TCROSSLINK Crosslink random timeout 1.0 (max) 1.0 (max) ms This random timeout helps resolve potential
conflicts in the crosslink configuration.
LTX-SKEW Lane-to-Lane Output Skew 500 ps + 2 UI 500 ps + 4 UI PS Between any two Lanes within a single Transmitter.
(max) (max)

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Table 7-1 2.5 and 5.0 Gbps PCIe Gen2 Transmitter Specifications (Continued)
Symbol Parameter 2.5 Gbps 5.0 Gbps Units Comments
CTX AC Coupling Capacitor 75 (min) 75 (min) nF All Transmitters should be AC coupled. The AC
200 (max) 200 (max) coupling is required either within the media or
within the transmitting component itself.
Notes:
1. SSC permits a +0. - 5000 ppm modulation of the clock frequency at the modulation rate does not exceed 33 kHz.
2. Measurements at 5.0 Gbps require an oscilloscope with at least 12.5 GHz bandwidth, or equivalent, while measurements made at 2.5 Gbps
require a scope with at least 6.2 GHz bandwidth. Measurement at 5.0 Gbps must deconvolve effects of compliance test board to yield an effective
measurement at Tx pins. 2.5 Gbps may be measured within 200 mils of Tx device's pins, although deconvolution is recommended. At least 106
Ul of data must be acquired.
3. Transmitter jitter is measured by driving the Transmitter under test with a low jitter "ideal" clock and connecting the DUT to a reference load.
4. Transmitter raw jitter data must be convolved with a filtering function that represents the worst case CDR tracking BW. 2.5 Gbps and 5.0 Gbps
use different filter functions. After the convolution process has been applied, the center of the resulting eye must be determined and used as a
reference point for obtaining eye voltage and margins.
5. Measurement is made over at least 106 UI.
6. Tx PLL Bandwidth must lie between the min and max ranges given in the above table. PLL peaking must lie below the value listed above. Note
that PLL B/W extends from zero up to the value(s) specified in the above table.
7. Measurements are made for both common mode and differential return loss. The DUT must be powered up and DC isolated, and Ms data+/data-
outputs must be in the low-Z state at a static value.
8. A single combination of PLL BW and peaking is specified for 2.5 Gbps implementations. For 5.O Gbps, two combinations of PLL BW and peaking
are specified to permit designers to make a tradeoff between the two parameters. If the PLL's min BW is >=8 MHz, the up to 3.0 dB of peaking is
permitted. If the PLL's min BW is relaxed to >= 5.0 MHz, then a tighter peaking value of 1.0 dB must be met. In both cases, the max PLL BW is
16 MHz.
9. Low swing output, defined by VTX-DIFF-PP-LOW must be implemented with no de-emphasis.
10. For 5.0 Gbps, de-emphasis timing jitter must be removed. This parameter is measured by accumulating a record length of 106 Ul while the DUT
outputs a compliance pattern. TMIN-PULSE is defined to be nominally 1 Ul wide and is bordered on both sides by pulses of the opposite polarity.
11. Root complex Tx de-emphasis is configured from Upstream controller. Downstream Tx de-emphasis is set via a command, issued at 2.5 Gbps.

Table 7-2 5.0 Gbps Limits for Common Refclk Rx Architecture

Parameter Description Min Max. Units Comments
Ul Unit interval without 200.06 199.94 ps Over 106 Ul
including of SSC
TRX-HF-RMS 1.5- 100 MHz RMS jitter - 3.4 ps Spectrally flat
RMS
TRX-HF-DJ-DD Max: Dj impinging on Rx - B8 ps 1, 3
under test
TRX-SSC-RMS 33 kHz Refclk residual -- 75 ps -
TRX-LF-RMS < 1.5 MHz RMS jitter -- 4.2 ps Spectrally flat
RMS
TRX-MIN-PULSE Minimum single pulse 120 ps 1
applied at Rx
VRX-MIN-MAX-RATIO Min/max pulse voltage -- 5 1
ratio seen over a time
interval of 2 Ul.
VRX-EYE Receive eye voltage 120 - mVPP 2
opening diff

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Table 7-2 5.0 Gbps Limits for Common Refclk Rx Architecture (Continued)
Parameter Description Min Max. Units Comments
VRX-CM-CH-BRC Common mode noise from -- 300 mVPP 1
Rx
Notes:
1. Accumulated over 106 UI.
2. Minimum eye is obtained by first injecting maximum Dj and then adjusting Rj until a minimum eye (defined by TRX-EYE) is reached. Rj is filtered
with a BPF having FC-LOW and FC-HIGH of 1.5 MHz and 100 MHz, respectively with step rolloff at 1.5 MHz and a 20 dB/decade rolloff on the high
side. Minimum eye width is defined for a sample size equivalent to a BER of 10-12.
3. Different combinations of TRX-HF-DJ-DD and TRX-HF-RMS are needed to measure TRX-TJ-CC. and TRX-DJ-DD-CC.

Table 7-3 5.0 Gbps Tolerancing limits for Data Clocked Rx Architecture
Parameter Description Min Max Units Comments
Ul Unit interval without 200.06 ppm 199.94 ppm ps Over 106 Ul
including SSC
TRX-HF-RMS 1.5-100 MHz RMS jitter - 4.2 ps Spectrally flat, Note 1
RMS
TRX-HF-DJ-DD Max Dj impinging on Rx - 88 ps 1, 3
under tolerancing
TRX-LF-SSC-FULL Full 33 kHz SSC - 20 ns 1
TRX-LF-RMS 10 kHz to 1.5 MHz RMS - 8.0 ps Spectrally flat
jitter RMS
TRX-MIN-PULSE Minimum single pulse 120 - ps 1
applied at Rx
VRX-MIN-MAX-RATIO Min/max pulse voltage — 5 - 1
ratio seen over a time
interval of 2 Ul.
VRX-EYE Receive eye voltage 100 - mVPP 2
opening diff
VRX-CM-CH-BRC Common mode noise from - 300 mVPP 1
Rx
Notes:
1. Accumulated for 106 UI.
2. Minimum eye is obtained by first injecting maximum Dj and then adjusting Rj until a minimum eye (defined by TRX-EYE is reached. Rj is filtered
with a BPF having FC-LOW and FC-HIGH of 1.5 MHz and 100 MHz, respectively with step rolloff at 1.5 MHz and a 20 dB/decade rolloff on the high
side. Minimum eye width is defined for a sample size equivalent to a BER of 10-12.
3. Different combinations of TRX-HF-DJ-DD and TRX-HF-RMS are needed to measure TRX-TJ-DC and TRX-DJ-DD-DC.

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Table 7-4 defines the parameters for 2.5 and 5.0 Gbps Receivers.

Table 7-4 2.5 and 5.0 Gbps Receiver Specifications

Symbol Parameter 2.5 Gbps 5.0 Gbps Units Comments
Ul Unit Interval 399.88 (min) 199.94 (min) ps UI does not account for SSC caused variations.
400.12 (max) 200.06 (max)
VRX-DIFF-PP-CC Differential Rx peak-peak 0.175 (min) D.120 (min) V -
voltage fnr common 1.2 (max) 1.2 (max)
Refclk. Rx architecture
VRX-DIFF-PP-DC Differential Rx peak-peak 0.175 (min) 0.100 (min) V -
voltage for data clocked Rx 1.2 (max) 1.2 (max)
architecture
TRX-EYE Receiver eye time opening 0.40 (min) N/A Ul Minimum eye time at Rx pins to yield a 10-12 BER.
See Note 1.
TRX-TJ-CC Max Rx inherent timing N/A 0.40 (max) Ul Max Rx inherent total timing error for common
error Refclk Rx architecture. See Note 2.
TRX-TJ-DC Max Rx inherent timing N/A 0.34 (max) Ul Max Rx inherent total timing error for data clocked
error Rx architecture. See Note 2.
TRX-DJ-DD-CC Max Rx inherent N/A 0.30 (max) Ul Max Rx inherent deterministic timing error for
deterministic timing error common Refclk Rx architecture. See Note 2.
TRX-DJ-DD-DC Max Rx inherent N/A 0.24 (max) Ul Max Rx inherent deterministic timing Error for data
deterministic timing error clocked Rx architecture. See Note 2.
TRX-MEDIAN-to-MAX- Maximum delta between 0.3 (max) Not specified Ul Only specified for 2.5 Gbps.
JITTER median and deviation from
median
TRX-MIN-PULSE Minimum width pulse at Rx Not specified 0.6 (min) Ul Measured to account for worst Tj at 10-12 BER.
VRX-MAX-MIN-RATIO min/max pulse voltage on Not specified 5 (max) Rx eye must simultaneously meet VRx_EYE limits.
consecutive Ul
BWRX-PLL-HI Maximum Rx PLL 22 (max) 16 (max) MHz Second order PLL jitter transfer bounding function.
bandwidth See Note 3.
BWRX-PLL-LO-3DB Minimum Rx PLL BW for 3 1.5 (min) 8 (min) MHz Second order PLL jitter transfer bounding function.
dB peaking See Note 3.
BWRX-PLL-LO-1DB Minimum Rx PLL BW for 1 Not specified 5 (min) MHz Second order PLL jitter transfer bounding function.
dB peaking See Note 3.
PKGRX-PLL1 Rx PLL peaking with 8 MHz Not specified 3.0 dB Second order PLL jitter transfer bounding function.
min BW See Note 3.
PKGRX-PLL2 Rx PLL peaking with 5 MHz Not specified 1.0 dB Second order PLL jitter transfer bounding function.
min BW See Note 3.
RLRX-DIFF Rx package plus Si 10 (min) 10 (min) for dB See Note 4.
differential return loss 0.05-1.26 GHz
8 (min) for
1.25-2.5 GHz
RLRX-CM Common mode Rx return 6 (min) 6 (min) dB See Note 4.
loss
ZRX-DC Receiver DC common 40 (min) 40 (min} Ci DC impedance limits are needed to guarantee
mode impedance 60 (max) 60 (max) Receiver detect. See Note 5.

ZRX-DIFF-DC DC differential impedance 80 (min) Not specified C. For 5.0 Gbps covered under RLRX-DIFF parameter.
120 (max) See Note 5.

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Table 7-4 2.5 and 5.0 Gbps Receiver Specifications (Continued)

Symbol Parameter 2.5 Gbps 5.0 Gbps Units Comments
ZRX-HIGH-IMP-DC-POS DC Input CM Input 50 k (min} 50 k (min) a Rx DC CM impedancE with the Rx terminations not
Impedance far V>D during powered, measured over the range 0 - 200 mV with
Reset or power down respect to ground. See Note 7.
ZRX-HIGH-IMP-DC-NEG DC Input CM Input 1.0 k (min} 1.0 k (min) a Rx DC CM impedancE with the Rx terminations not
Impedance for V<0 during powered, measured over the range -150 - 0 mV with
Reset or power down respect to ground. See Note 7.
VRX-IDLE-DET-DIFFp-p Electrical Idle Detect 65 (min) 95 (min) mV VRX-IDLE-DET-DIFFp-p= 2*/VRX-D+-VRX-D-/-
Threshold 175 (max) 175 (max) Measured at the package pins of the Receiver.
TRX-IDLE-DET-DIFF- Unexpected Electrical Idle 10 (max) 10 (max) ms An unexpected Electrical Idle (VRX-IDLE -DIFFp-p< VRX-
ENTERTIME Enter Detect Threshold IDLE-DET-DIFFp-p) must be recognized no longer than
Integration Time TRX-IDLE-DET-DIFF-ENTERTIME to signal an unExpected
idle condition.
Lrx-SKEW Lane to Lane skew 20 (max) 8 (max) ns Across all Lanes on a Port. This includes variation in
the length of a SKP Ordered Set at the Rx as well as
any delay differences arising from the interconnect
itself. See Note 8.
VRX-CM-AC-P Rx AC common mode 150 (max) 150 (max} mVP Measured at Rx pins into a pair of 50 Q terminations
voltage into ground. See Note 6.
Notes:
1. Receiver eye margins are defined into a 2 x 50 Q. reference load. A Receiver is characterized by driving it with a signal whose characteristics are
defined by the parameters.
2. The four inherent liming error parameters are defined for the convenience of Rx designers, and they are measured during Receiver tolerancing.
3. Two combinations of PLL BW and peaking are specified at 5.0 Gbps to permit designers to make trade-offs between the two parameters. If the
PLL's min BW is >= 8MHz. then up to 3.0 dB of peaking is permitted. If the PLL's min BW is relaxed to >=5.0 MHz, then a tighter peaking value
of 1.0 dB must be me. Note: a PLL BW extends from zero up to the value(s) defined as the min or max in the above table. For 2.5 Gbps a single
PLL bandwidth and peaking value of 1.5-22 MHz and 3.0 dB are defined.
4. Measurements must be made for both common mode and differential return loss. In both cases the DUT must be powered up and DC isolated,
and its D+/D- inputs must be in the low-Z state.
5. The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect
occurs properly. Compensation of impedance can start immediately and the Rx Common Mode Impedance (constrained by RLRX-CM to 50- Q
±20%) must be within the specified range by the time Delect is entered.
6. Common mode peak voltage is defined by the expression: max{|(Vd+ - Vd-} - Vcmdc}.
7. ZRX-HIGH-IMP-DC-NEG and ZRX-HIGH-IMP-DC-POS are defined respectively for negative and positive voltages at the input of the Receiver. Transmitter
designers need to comprehend the large difference between >0 and <0 Rx impedances when designing Receiver detect circuits.
8. The LRX-SKEW parameter exists to handle repeaters that regenerate Refclk and introduce differing numbers of skips on different Lanes.

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8 10/100/1G Ethernet Media Access
Controller (GMAC)
This chapter describes the Ethernet interface capabilities and features.
The Transcede 2xxx device has two AXI 64-bit GMAC blocks. One GMAC block is configured for SGMII mode,
while the other is configured for RGMII mode.
• SGMII (Serial Gigabit Media Independent Interface)
• RGMII (Reduced Gigabit Media Independent Interface)

8.1 Feature List

The feature list in this section applies equally to each MAC block.
• Compatible with IEEE Standard 802.3.
• SGMII only supports 1000 Mbps operation speeds; RGMII can support 10/100/1000 Mbps operation speeds.
• Only for SGMII: Integrated Physical Coding Sub-layer (PCS) with auto-negotiation.
• Statistics counter registers for RMON/MIB.
• Embedded DMA.
• MDIO interface provided to control external phys from the Embedded RISC processor.
• Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames.
• Automatic discard of frames received with errors.
• Receive and transmit IP, TCP and UDP checksum offload (UDP checksum offload is only supported by RGMII.
SGMII does not support UDP checksum offload). Both IPv4 and IPv6 packet types supported.
• Address checking logic for four specific 48-bit addresses, four types of Ids, promiscuous mode, external
address checking, hash matching for unicast and multicast destination addresses and Wake-on-LAN.
• Programmable IPG stretch.
• Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames.
• Support for 802.1Qbb priority-based flow control – PFC Negotiation mode.
• Full utilization of the Tx 1 Gbps line.
• Provides sufficient buffer 16KB to support lossless reception of maximum length (jumbo-type) up to
10,240Bytes Ethernet frames.
• For RGMII only: RGMII electrical characteristics compliant with RGMII v1.3 (thus based upon 2.5V CMOS
interface voltages as defined by JEDEC EIA/JESD8-5), and are not compliant with RGMII v2.0.
• Support for 1588 V1/V2.
• Support for 802.3az Energy Efficient Ethernet.

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8.2 Management Data Input/Output (MDIO) Interface Timing

Figure 8-1 and Table 8-1 give the MDIO interface timing parameter details.
Figure 8-1 MDIO Interface Timing

MDC

Tis Tih
MDIO
( input)

MDC

Tod

MDIO
( output)

Table 8-1 MDIO Interface Timing Parameters

Symbol Parameter Min. Typ. Max. Units

- Clock edge rate (All Clocks) 0.25 - 2 V/ns
- MDC Frequency - - 2.5 MHz
- MDC Duty Cycle 40 - 60 %
Tis MDIO Input Setup Time 20 - - ns
Tih MDIO Input Hold Time 0 - - ns
Tod MDIO Output Delay Time -10 - 10 ns
Notes:
For the clock edge rate (all clocks), the rise and fall times are determined by the edge rate in V/ns. A “Max” edge rate is the fastest rate at which a clock
transitions.

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8.3 RGMII Interface Timing

Figure 8-2 and Table 8-2 give the RGMII interface timing parameter details.
Figure 8-2 RGMII Interface Timing Diagram

TXC (at Transmitter)

TskewT
TXD [8:5][3:0] TXD[8:5]
TXD [7:4][3:0] TXD[3:0] TXD[7:4]

TXD[4] TXD[9]
TX_CTL TXEN TXERR
TskewR

TXC (at Receiver)

RXC (at Transmitter)

TskewT
RXD [8:5][3:0] RXD[8:5]
RXD[3:0] RXD[7:4]
RXD [7:4][3:0]

RXD[4] RXD[9]
RX_CTL RXDV RXERR
TskewR

RXC (at Receiver)

Table 8-2 RGMII Interface Timing Parameters

Symbol Parameter Min. Typ. Max. Units Comments

TskewT Data to Clock Output Skew (at -500 0 500 ps 1,2,7
Transmitter)
TskewR Data to Clock Input Skew (at 1 - 2.6 ns 1,3,7
Receiver)
Tclkd Tx clock delay 1.5 - 2 ns 4
Rclkd Rx clock delay 1.5 - 2 ns 4
Tcyc Clock Cycle Duration (1000 Mbps) 7.2 8 8.8 ns 7
- Clock Accuracy -50 - 50 ppm 7
Duty_G Duty Cycle for Gigabit 45 50 55 % 5,6,7
Tr / Tf Rise / Fall Time (20-80%) - - .75 ns 7

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Table 8-2 RGMII Interface Timing Parameters (Continued)

Symbol Parameter Min. Typ. Max. Units Comments

Notes:
1. Applies to cases where internal delay on TXC/RXC is not enabled.
2. The skew at the transmitter is specified for 15pF clock and data loads. If the load is significantly different on the board, the board designer is
responsible for characterizing and accounting for the output skew. Parallel and serial terminations are required and circuit simulation is highly
recommended.
3. It is recommended that the PHY/switch, connected to over this interface, should include internal clock delays (for both receive and transmit
directions), to overcome the difference introduced between TskewT and TskewR. An alternative option of additional trace delay on the board is
not recommended due to additional load it introduces.
4. Optionally enabled/disabled through register configuration.
5. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long as minimum duty
cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned between.
6. Cycle values are defined in percentages of the nominal clock period so to make this table speed independent.
7. Needs to be compliant with RGMII v1.3 (thus based upon 2.5v CMOS interface voltages as defined by JEDEC EIA/JESD8-5), and not compliant
with RGMII v2.0 (specifically, not based upon 1.5v HSTL interface voltages as defined by JEDEC EIA/JESD8-6).

NOTE: The TXC signal requires a typical delay of 1 to 1.5 ns. Use the PHY or switch
specification to determine the required delay.

8.4 SGMII (SerDes) Mode

The basis of the LVDS and termination scheme can be found in IEEE1596.3-1996. Some parameters have been
modified to accommodate the 1.25Gb/s requirements. SGMII consists of the most lenient DC parameters between
the general purpose and reduced range LVDS. Up to two SGMII interface may be configured.
Both the data and clock signals are DC balanced; therefore, implementations that meet the AC parameters but fail
to meet the DC parameters may be AC coupled.
Figure 8-3 shows the DDR circuit at the source of the LVDS. The circuit passes data and clock with a 90 degree
phase difference. The receiver samples data on both edges of the clock.
Figure 8-3 Reference Data and Clock Circuit

Data RX

RXCLK
1.25 GHz 625 MHz DDR Clock
Clock

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Figure 8-4 Driver Clock and Data Alignment

RXCLK
(single ended)

RXCLK
(differential)

RX
(single ended)
RX
(differential)
tclock2q (min)
tclock2q (max)

Table 8-3 Driver DC Specification

Symbol1 Parameter2 Min Max Units

Voh Output voltage high 1525 mV

Vol Output voltage low 875 mV
Vring Output ringing 10 %
|Vod| Output Differential Voltage 150 400 mV
Vos Output Offset Voltage 1075 1325 mV
Ro Output impedance (single ended) 40 140 Ω
ΔRo Mismatch in a pair 10 %
Δ|Vod| Change in Vod between “0” and “1” 25 mV
ΔVos Change in Vos between “0” and “1” 25 mV
Isa, Isb Output current on Short to GND 40 mA
Isab Output current when a, b are shorted 12 mA
Ixa, Ixb Power off leakage current 10 mA
Notes:
1. For a detailed description of the symbols see the IEEE1596.3-1996 standard.
2. All parameters measured at Rload = 100 Ω ±% load

Table 8-4 Receiver DC Specification

Symbol Parameter Min Max Units

Vi Input Voltage range a or b 675 1725 mV
Vidth Input differential threshold -50 +50 mV
Vhyst Input differential hysteresis 25 mv
Rin Receiver differential input impedance 80 120 Ω

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Table 8-5 Driver AC Specification

Symbol1 Parameter Min Max Units

clock Clock signal duty cycle @ 625MHz 48 52 %

tfall Vod fall time (20%-80%) 100 200 pSec
trise Vod rise time (20%-80%) 100 200 pSec
2
tskew1 Skew between two members of a differential pair 20 pSec
- |tpHLA - tpLHB| or |tpLHA - tpHLB|
tclock2q3 Clock to Data relationship: from either edges of 250 550 pSec
the clock to valid data
Notes:
1. For a detailed description of the symbols see the IEEE1596.3-1996 standard
2. Skew measured at 50% of the transition
3. Skew measured at 0v differential

Table 8-6 Receiver AC Specification

Symbol Parameter Min Max Units

tsetup1 setup time 100 pSec
thold hold time 100 pSec

Note:
1. Measured at 50% of the transition

8.5 MAC Transmitter

The MAC transmitter can operate in full duplex and transmits frames in accordance with the Ethernet IEEE 802.3
standard.

A small input buffer receives data through the external FIFO interface from the DMA module which will extract data
in 64-bit form. All subsequent processing prior to the final output is performed in bytes.

Transmit data can be output using the GMII/MII interface or through the TBI. If the TBI is selected (gigabit and
SGMII modes only), then the MAC transmitter passes 8-bitdata to the PCS sub-layer for further processing prior to
output on the TBI.

Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO
interface a word at a time.

If necessary, padding is added to take the frame length to 60 bytes. CRC is calculated using an order 32 bit
polynomial. This is inverted and appended to the end of the frame taking the frame length to a minimum of 64
bytes. If the no CRC bit is set in the second word of the last buffer descriptor of a transmit frame neither pad nor
CRC are appended. The no CRC bit can also be set through the FIFO interface.

In full duplex mode, frames are transmitted immediately. Back to back frames are transmitted at least 96 bit times
apart to guarantee the inter frame gap. When operating in gigabit mode, late collisions are treated as an exception
and transmission is aborted, without retry. This condition is reported in the transmit buffer descriptor word 1 (late
collision, bit 26) and also in the transmit status register (late collision, bit 7). An interrupt can also be generated (if
enabled) when this exception occurs, and bit 5 in the interrupt status register will be set.

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Several frames may be transmitted up to the burst limit of 65,536 bytes. The transmitter relinquishes control of the
medium when there are no more frames queued for transmission or the burst limit is exceeded.

In gigabit mode any collisions occurring after the minimum slot time for the first frame within a burst are treated as
a late collision. The burst is terminated upon this event.

In all modes of operation, if the transmit DMA under runs, a bad CRC is automatically appended using the same
mechanism as jam insertion and the tx_er signal is asserted. For a properly configured system this should never
happen and also it is impossible if configured to use the DMA with packet buffers, as the complete frame is
buffered in local packet buffer memory. By setting when bit 28 is set in the network configuration register the IPG
may be stretched beyond 96 bits depending on the length of the previously transmitted frame and the value written
to the IPG_STRETCH register. The least significant 8 bits of the IPG_STRETCH register multiply the previous
frame length (including preamble) the next significant 8 bits (+1so as not to get a divide by zero) divide the frame
length to generate the IPG. IPG stretch only works in full duplex mode and when bit 28 is set in the network
configuration register.

The IPG_STRETCH register cannot be used to shrink the IPG below 96 bits.

If the back pressure bit is set in the network control register, the transmit block transmits 64 bits of data, which can
consist of 16 nibbles of 1011 or in bit rate mode 641s, whenever it sees an incoming frame to force a collision.

8.6 MAC Receiver

All processing within the MAC receive block is implemented using 16 bit data path. The MAC receive block checks
for valid preamble, FCS, alignment and length, DMA received frames with FCS to an external memory and stores
the frames destination address for use by the address checking block. The receive block monitors for CRC (FCS)
errors, short frame, long frame, jabber or receive symbol errors. When operating in gigabit mode (half duplex), the
receiver will discard frames which do not meet the minimal slot time of 512 bytes. If a burst is detected, the first
frame is checked to ensure it meets the slot time, but all subsequent frames of the burst are checked to ensure they
meet the minimum frame size of 64 bytes.
In gigabit mode (half duplex), carrier extension errors are detected by the receiver during the minimum slot time,
and the frame discarded. Carrier extension errors occurring during the inter packet gap period are ignored and
have no effect on the statistics.
The GEM can be configured to perform IP, TCP and UDP checksum offloading in the receive direction. This is done
with certain restrictions. UDP checksum offload is only supported by RGMII. SGMII does not support UDP
checksum offload.
The receiver implements a filtering mechanism. The GEM supports recognition of four specific addresses. The
addresses stored can be specific, group, local or universal. If a receive frame address matches an active address,
the frame is passed. Frames may also be filtered using the type ID field for matching. Four type ID registers exist in
the register address space. Frames with the broadcast address of 0xFFFFFFFFFFFF are optionally passed. Hash
indexing is also possible. Promiscuous mode is an option where all frames (except those that are too long, too
short, have FCS errors or have rx_er asserted during reception) will be passed.
The receive block supports Wake on LAN by detecting the following events on incoming receive frames:
• Magic packet
• ARP request to the device IP address
• Specific address 1 filter match
• Multicast hash filter match

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If one of these events occurs, Wake on LAN detection is indicated. These events can be individually enabled. For
Wake on LAN detection to occur receive enable must be set in the network control register, however a receive
buffer does not have to be available.

8.7 IEEE 1588 Support

IEEE 1588 is a standard for precision time synchronization in local area networks. It works using exchange of
special Precision Time Protocol (PTP) frames. The PTP messages can be transported over IEEE 802.3/Ethernet,
over Internet Protocol Version 4 or over Internet Protocol Version 6. For greatest accuracy hardware assist is
required to detect when PTP transmit or receive event messages are sent or received.

The GEM has the ability to be programmed to detect when the PTP event messages (Sync, Delay Request,
PDelay Request and PDelay response) are transmitted and received and to measure the hardware timestamp
when those messages are sent or received.

The time-stamp is taken when the message time-stamp point passes the clock time-stamp point. In the case of the
GEM device this measurement is taken when a transmit or receive PTP Event message is processed at the rGMII
or sGMII interface depending on which interface the GEM is programmed for.

The GEM recognizes four different encapsulations for PTP event messages:
• 1588 version 1 (UDP/IPv4 multicast)
• 1588 version 2 (UDP/IPv4 multicast)
• 1588 version 2 (UDP/IPv6 multicast)
• 1588 version 2 (Ethernet multicast)
Table 8-7 to Table 8-8 are examples of 1588 frames in the 1588 version 1 format.

Table 8-7 Example of a Sync Frame in the 1588 Version 1 Format

Field Octets Example

Preamble/SFD 555555555555555D5
DA Octets 0 - 5
SA Octets 6 - 11
Type Octets 12 - 13 0800
IP stuff Octets 14 - 22
UDP Octet 23 11
IP stuff Octets 24 - 29
IP DA Octets 30 - 32 E00001
IP DA Octet 33 81
source IP port Octets 34 - 35
dest IP port Octets 36 - 37 013F
other stuff Octets 38 - 42
version PTP Octet 43 01
IP stuff Octets 44 - 69
UUID Octets 70 - 71

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Table 8-7 Example of a Sync Frame in the 1588 Version 1 Format (Continued)

Field Octets Example

sequenceID Octets 72 - 73
control Octet 74 00
other stuff Octets 75 - 168

Table 8-8 Example of a Delay Request Frame in the 1588 Version 1 Format

Field Octets Example

Preamble/SFD 555555555555555D5
DA Octets 0 - 5
SA Octets 6 - 11
Type Octets 12 - 13 0800
IP stuff Octets 14 - 22
UDP Octet 23 11
IP stuff Octets 24 - 29
IP DA Octets 30 - 32 E00001
IP DA Octet 33 81
source IP port Octets 34 - 35
dest IP port Octets 36 - 37 013F
other stuff Octets 38 - 42
technology (version PTP) Octet 43 01
subdomain Octets 44 - 69
UUID Octets 70 - 71
sequenceID Octets 72 - 73
control Octet 74 01
other stuff Octets 75 - 168

For 1588 version 1 messages sync and delay request frames are indicated by the GEM if the type field of the frame
indicates TCP/IP, UDP protocol is indicated, the destination IP address is 224.0.1.129/130/131 or 132, the
destination UDP port is 319 and the control field is correct. The control field is 0xX0 for sync frames and 0xX1 for
delay request frames.

For 1588 version 2 messages the type of frame is determined by looking at the low nibble of the messagetype field
of the PTP frame. Whether a frame is version 1 or version 2 can be determined by looking at the version PTP field
of both version 1 and version 2 PTP frames.

In version 2 messages, sync frames have a message type value of 0xX0, delay_req have 0xX1, pdelay_req have
0xX2 and pdelay_resp have 0xX3.

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Table 8-9 to Table 8-12 are examples of 1588 frames in the 1588 version 2 formats.

Table 8-9 Example of a Sync Frame in the 1588 Version 2 (UDP/IPv4) Format

Field Octets Example

Preamble/SFD 555555555555555D5
DA Octets 0 - 5
SA Octets 6 - 11
Type Octets 12 - 13 0800
IP stuff Octets 14 - 22
UDP Octet 23 11
IP stuff Octets 24 - 29
IP DA Octets 30 - 32 E00001
IP DA Octet 33 81
source IP port Octets 34 - 35
dest IP port Octets 36 - 37 013F
other stuff Octets 38 - 41
messagetype Octet 42 00
version PTP Octet 43 02

Table 8-10 Example of a Sync Frame in the 1588 Version 2 (UDP/IPv6) Format

Field Octets Example

Preamble/SFD 555555555555555D5
DA Octets 0 - 5
SA Octets 6 - 11
Type Octets 12 - 13 86dd
IP stuff Octets 14 - 19
UDP Octet 20 11
IP stuff Octets 24 - 29
IP DA Octets 38 - 41 FF0X0000
IP DA 2nd Octets 42 - 45
IP DA 3rd Octets 46 - 49
IP DA 4th Octets 50 - 53
source IP port Octets 54 - 55
dest IP port Octets 56 - 57 013F
other stuff Octets 58 - 61
messagetype Octet 62 00

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Table 8-11 Example of a Sync Frame in the 1588 Version 2 (Ethernet Multicast) Format

Field Octets Example

Preamble/SFD 555555555555555D5
DA Octets 0 - 5 011B19000000
SA Octets 6 - 11
Type Octets 12 - 13 88F7
messagetype Octet 14 00
version PTP Octet 15 02
Note: For the multicast address 011B19000000 sync and delay request frames are recognized depending on the message type field, 00 for sync and
01 for delay request.

Table 8-12 Example of a Pdelay_req Frame in the 1588 Version 2 (Ethernet Multicast) Format

Field Octets Example

Preamble/SFD 555555555555555D5
DA Octets 0 - 5 0180C200000E
SA Octets 6 - 11
Type Octets 12 - 13 88F7
messagetype Octet 14 02
version PTP Octet 15 02
Note: These need a special multicast address so they can get through ports blocked by the spanning tree protocol. For the multicast address
0180C200000E sync, pdelay request and pdelay response frames are recognized depending on the message type field, 00 for sync, 02 for pdelay
request and 03 for pdelay response.

The GEM contains an optional time stamp unit (TSU) selectable with a tick define. The TSU consists of a timer and
registers to capture the time at which PTP event frames cross the message time-stamp point. An optional interrupt
can be issued when a capture register is updated.

The timer is implemented as a 64 bit register with the upper 32 bits counting seconds and the lower 32 bits
counting nanoseconds. The lower 32 bits rolls over when they have counted to one second. An optional interrupt
can be generated when the seconds increment. The timer value can be read, written and adjusted by software as
needed to implement timer adjustment algorithms as needed by IEEE 1588 clock synchronization algorithms.

The amount by which the timer increments each input reference clocking source cycle is controlled by the timer
increment register.
• Bits 7:0 are the default increment value in nanoseconds. If the rest of the register is written with zero the timer
increments by the value in 7:0 each clock cycle.
• Bits 15:8 of the increment register are the alternative increment value in nanoseconds
• Bits 23:16 are the number of increments after which the alternative increment value is used. If 23:16 are zero
then the alternative increment value will never be used.

An alternative way of adjusting time in the timer is to use the timer adjustment register. This allows for small
adjustments in time without the need to adjust frequency.

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Using all of the above options in addition to any frequency adjustments (example, if the Network Timing Generator
is used to source the 1588 timing reference) allows the 1588 clock synchronization algorithms to chose when and
how to either adjust time, adjust reference frequency or both.

8.8 Network Timing Generator (NTG) for 1588

See Section 14.6, Network Timing Generator (NTG) for TDM, on page 140 for details.

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9 Expansion Bus Interface
This chapter introduces the features and implementation details of the expansion bus interface.

9.1 Feature List

• Support for up to 5 peripheral devices—NAND flash with Hardware Error Correcting Code (ECC) and 4
general-purpose devices interface, that is, NOR flash devices. NAND flash chip-select is controlled by software
and driven on a GPIO pin. When NAND flash is not used, a 5th generic device can be supported.
• Support for 8, 16, and 32-bit AHB transactions.
• Support for 8 and 16-bit data bus interfaces; configurable per chip select.
• AHB transaction size that is larger than the external bus width, will be split into separate transactions by the
expansion block, meanwhile halting the AHB interface.
• Programmable chip select level, configurable per chip select.
• Configurable memory-address space. Each Chip-Select is allocated two configurations register to define its
address space delineation.
• Chip-select 0 is dedicated for external boot flash when used, enabled by default. Otherwise, can be configured
to support any generic peripheral device.
• 2 input strap pins are used to set the default bus size of chip-select 0 device, 8 or 16-bit data bus can be
selected. This bus size may be overwritten by software.
• Provides support for multiplexed address-data mode with address latch enable.
• Programmable timings per chip select; counts in terms of expansion clock cycles.
• Support for byte-enable writes, up to 4 bytes on the expansion interface.
• Provides support for Ready/busy# acknowledge signal for terminating transactions. Detecting the de-assertion
of Read/Busy# signal will override the Chip-Select and Write Enable/ Read Enable to be de-asserted for the
current transaction. Detection of Ready signal on rising/falling edge is configurable.
• Synchronous interface. The AHB clock can be a divide down by 3-7. The divide integer is configurable by
software, default is set to 7.
• External expansion clock is provided and maybe suppressed by software, when not used by any of the
peripherals. All programmable timing parameters are synchronized to this expansion clock.
• Two separate sets of read/write controls are provided; one set is dedicated for NAND flash: WE_NAND#/
RE_NAND#, and the other set is for the generic devices: EXP_RE/ EXP_WE.
• Two command modes are supported. Signals assertion level is configurable.
– Provides support for separate EXP_RE and EXP_WE signals.
– Provides support for EXP_RW and EXP_STRB signals. The EXP_RW signal will be driven on the
EXP_WE pin, and the EXP_STRB signal will be driven on the EXP_RE pin.
• Extended support for External flash devices are provided through GPIO pins when enabled:
– EXP_WP# and EXP_RP# (optional).
– Peripheral interrupt support.
– NAND Flash controls and chip select support: CS and RDY.

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– NAND Flash controls: ALE and CLE will be assigned to upper expansion address bus.
• Supports hardware acceleration of multi-bit ECC for NAND, with the following features:
– BCH IP encodes data into a 16383-bit codeword (214 Galois Field)
– 2-32 bit error correction
– 2-1800 data bytes per block
– Pass through flow (no data FIFO)
– Hamming

9.2 Expansion Bus Block Diagram

Figure 9-1 illustrates the Expansion bus block diagram.
Figure 9-1 Expansion Bus Block Diagram

Chip

APB Bus
GPIO
APB I/F

NAND Strobes Generic

NAND CS# Peripheral
Device
#4
or
CS# 4 NAND Flash

CS# 1 Ͳ 3
Generic
Data & Strobes
Peripheral
Device
Addr & Control #1Ͳ 3
Expansion Bus
Controller
AHB Bus

Block
AHB I/F Generic
Peripheral
Device
#0
or
Boot Flash
CS# 0

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9.3 I/O Description

The expansion block of the Transcede 2xxx supports signals through the following interfaces:
• External Interface
• Slave AHB Interface
• Configuration APB Interface
• General Interface

9.3.1 External Interface

Table 9-1 shows the In/Out description of the external interface.

Table 9-1 I/O Description of External Interface

Port Name In/Out Clock Bus Width Description
Exp_clk O hclk 1 Expansion clock to the peripheral devices. This clock is generated in the
Expansion block by dividing down the AHB clock by any of the following integers:
3 to 7.
This clock is gated-off when accessing asynchronous devices by setting
EXP_CLK_EN to 0.
Exp_cs0 O hclk 1 Chip Select 0, with programmable active level, enables and disables selection of
the targeted peripheral devices. This generic chip-select will be dedicated to
select external boot flash when used.
Exp_cs1 O hclk 1 Chip Select 1, with programmable active level, enables and disables selection of
the targeted peripheral devices.
Exp_cs2 O hclk 1 Chip Select 2, with programmable active level, enables and disables selection of
the targeted peripheral devices.
Exp_cs3 O hclk 1 Chip Select 3, with programmable active level, enables and disables selection of
the targeted peripheral devices.
Exp_we_n / Exp_rw_n O hclk 1 Normal Mode: Write Enable, when asserted, indicates a write operation to
peripheral.
Strobe Mode: Read/Write Enable signal.
Assertion level of this signal is configurable.
Exp_re_n / Exp_strb_n O hclk 1 Normal Mode: Read Enable, when asserted, indicates a read operation from
peripheral.
Strobe Mode: command Strobe signal.
Assertion level of this signal is configurable.
Exp_nand_re_n O hclk 1 Read Enable dedicated for NAND flash, when asserted low, indicates a read
operation from flash device. Assertion level of this signal is configurable.
NAND flash chip-select is driven by software through GPIO pin.
Exp_nand_we_n / O hclk 1 Write Enable dedicated for NAND flash, when asserted low, indicates a write
Exp_cs4 operation to the flash device. When NAND flash is not used, this pin can be used
as a chip-select and can be configured to support generic peripheral device.
Assertion level of this signal is configurable.
NAND flash chip-select is driven by software through GPIO pin.
Exp_dm O hclk 4 Data Byte Mask. Input data byte to the peripheral device is masked when DM is
sampled high during a write access. One DM pin per data byte.

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Table 9-1 I/O Description of External Interface (Continued)

Port Name In/Out Clock Bus Width Description
Exp_rdy I hclk 1 Peripheral device ready/busy status. When set low indicates that the current
transaction is in progress. Set high when the device is ready for a new
transaction. Detection edge of this signal is configurable (high->low) or (low-
>high). When Detected will cause de-assertion of the CS and RE/WE for the
current transaction.
Exp_addr O hclk 25 Expansion Address Bus. Specifies one Memory location along with the DM[1:0]
(Byte-Enable) when supported.
Exp_ale O hclk 1 Address Latch Enable. The ALE, active high output, controls address latching to
the peripheral device when multiplexed address/data bus mode is used.
Exp_wdata O hclk 16 Write data bus. Will be configured to support 8 or 16 active bits. For 8-bit,
exp_wdata[7:0] and for 16-bit exp_wdata[15:0] are active.
Exp_rdata I hclk 16 Read data bus. Will be configured to support 8 or 16 on the package mode
selected. For 8-bit, exp_rdata[7:0] and for 16-bit exp_rdata[15:0] are latched.
Exp_data_oen O hclk 2 Expansion data bus output enable. Asserted low for read transaction and high for
write transactions. 1 output enable signal per data byte.

9.3.2 Slave AHB Interface

This interface is compliant to AHB slave protocol. Split/Retry response is not supported. AHB bursts are not
supported.
Table 9-2 shows the In/Out description of the slave AHB interface.

Table 9-2 I/O Description of Slave AHB Interface

Port Name In/Out Clock Bus Width Description
hreset_n I hclk 1 System reset, ACTIVE LOW.
hclk I hclk 1 AMBA Bus Clock (HClk).
refclk I refclk 1 Refclk input to the expclk gen block, during reset refclk is output on expclk line.
hselect_exp I hclk 1 Expansion block select provided by host decoding logic.
hwrite I hclk 1 AMBA Read/Write signal. Active high for Write commands and low for Reads.
Driven by Master.
hsize I hclk 2 Size of data.
• 00: byte access,
• 01: half-words,
• 10: 32-bit words,
• 11: 64-bits double-words access,
• ….
htrans I hclk 2 Transfer type going to expansion bus slave
hburst I hclk 3 Burst type indication. Bursts are considered single transactions to the expansion.
haddr I hclk 32 AMBA Address Bus. Driven by Master.
hwdata I hclk 64 Write address buss going to the expansion bus.
hrdata O hclk 64 Read data bus

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Table 9-2 I/O Description of Slave AHB Interface (Continued)

Port Name In/Out Clock Bus Width Description
hready O hclk 1 When HIGH the HREADY signal indicates that a transfer has finished on the
expansion bus.
hready_in I hclk 1 Feeds back the hready generated by the expansion bus.
hresp O hclk 1 The transfer response from the expansion bus. The Split and Retry response is
not supported. Only Okay and Error response is supported.

9.3.3 Configuration APB Interface

Table 9-3 shows the In/Out description of the APB interface.

Table 9-3 I/O Description of APB Interface

Port Name In/Out Clock Bus Width Description
paddr[15:2] I hclk 14 APB configuration address bus.
psel_exp I hclk 1 Peripheral Select to the Expansion bus
pstbl I hclk 1 Peripheral strobe active high
pwdata I hclk 32 Peripheral write data bus
pwrite I hclk 1 Peripheral write/read signal
prdata O hclk 32 Peripheral read data bus from the Expansion bus

9.3.4 General Interface

Table 9-4 shows the In/Out description of the general interface.

Table 9-4 I/O Description of General Interface

Port Name In/Out Clock Bus Width Description
Boot_bus_size I hclk 2 Used to initialize Chip-select 0 data bus size. When external boot device is used,
the bus width of this device is decoded from these two HW pins 8 or 16-bit bus.
• 00: 8-bit bus.
• 01: 16-bit bus.
• 10: not supported in the Transcede 2xxx.
• 11: not supported.

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9.4 Block Functional Description

The Expansion Interface controls data flow to/from up to 4 generic memories and 1 dedicated NAND Flash device.
When NAND Flash is not used, a fifth generic memory device may be used. Initially CS0, which is part of the
generic interface, can be configured to be used for the external boot flash, occupying address space zero of the
expansion memory map; two pins will determine the external boot flash bus size.

When the Expansion block is accessed by the system, the Expansion controller will fetch/store data from/to these
memory flash like devices until de-selected. Depending on the memory device type being accessed, the required
timing parameters are configured to comply with the device timing-requirements, before initiating any transactions.
RDY pulse sampling, when supported, will be synchronized to AHB clock (Hclk) before casing the de-assertion of
the CS and the RE or WE control signals. The read data will be latched upon de-assertion of the CS or RE signal,
whichever comes first. A configuration bit per chip-select is provided to enable/disable detection of the RDY signal
and should be disabled for the devices that do not provide the RDY signals. If RDY signal, when enabled, is not
detected, will cause an error response on the AHB interface.

As for the NAND Flash, when accessed (an AHB access to its space), the software will control the CLE and ALE
signals as well as the device Chip-select through a GPIO dedicated pins. The expansion controller will provide the
flash address/data/command and drive the NAND_WE # \NAND_RE# signals. Each NAND flash access phase will
be considered a full expansion bus access cycle.

Some peripherals may require the support for a single command signal to be used for Read/Write indication, along
with the command-strobing signal. A special configuration bit STRB_MODE is used to select the type of the
provided command signals: separate command signals: 1 for read and 1 for write, or 1 signal to be used for read/
write indications and the other signal to be used as the strobe signal. The active level of these 2 signals is
configurable.

Accesses to the expansion block are decoded internally to assert the appropriate chip-select of the targeted
device. 32-bit AHB input data will be latched in case of write operations. Depending on the peripheral bus size
used, the latched data will be transferred over decoded number of expansion cycles.

The maximum number of expansion cycles to write 32-bit data over an 8-bit bus peripheral will be 4 cycles,
meanwhile the AHB bus is halted until all data bytes are transferred. In case of read operations, the input data from
the peripheral device is latched and formatted over a 32-bit AHB bus according to the peripheral bus size selected.
The read data is duplicated over the 32-bit AHB data bus, that is, if MEM_SIZE is set to 8, the read byte will be
latched over all bytes of AHB data bus.

This block is highly configurable per chip select to accommodate for most common types of memory/flash in the
industry.

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9.4.1 AHB Address Decoding

Depending on the memory size and the access size, the expansion address bus is decoded from the internal AHB
address bus. The lowest bit of the AHB bus is dropped when a half word access is performed, and the lowest two
bits are dropped when a word access is performed. Hence, word accesses are always aligned to word boundaries
in memory. Depending on the memory size, the interface will complete the Expansion bus address with the
Expansion cycle count bits, and decode the DM signals according to Table 9-5.

Table 9-5 Address Decoding

Write Data Mask
Exp. Bus Size AHB Access Size AHB Address Used Bits Exp. Cycle Count Bits
Decoded Bits
Byte Byte haddr [24:0] - -
Half haddr [24:1] Cycle_cnt [0] -
Word haddr [24:2] Cycle_cnt [1:0] -
Half Byte haddr [25:1] - haddr [0]
Half haddr [25:1] - -
Word haddr [25:2] Cycle_cnt [0] -

Expansion 25-bit generated address to the peripheral = {AHB Address Used Bits, Exp. Cycle Count Bits};
Expansion cycle counter increments on every complete expansion peripheral access cycle.

NOTE: AHB accesses outside the expansion chip-selects allocated memory segments will
cause an AHB Error response. Each chip select address map is configurable. CS0
boundary address map is defined by the CS0 memory base address register and the
CS0 memory segment address register.

9.4.2 Modes of Operation

This block is highly configurable per chip select to accommodate for most common types of memory/flash in the
industry. Four modes of operation can be configured to support the targeted peripheral timings as follows:
• Normal Mode
• ALE Mode
• Strobe Mode
• NAND Mode

NOTE: EXP_CS4 is muxed with the EXP_NAND_WE_N. Chip-select 4 address space will be
used by the NAND chip-select (GPIO pin) when NAND_MODE is enabled (default).
Setting NAND_MODE to 0 and CS4_EN to 1 will disable NAND support, and CS4 pin will
be used to access generic peripheral.

These modes support both synchronous and asynchronous devices. By default, synchronous support is set and
the output expansion clock is provided by setting EXP_CLK_EN global bit to 1 (high). When a asynchronous device
is accessed, EXP_CLK_EN global bit should be set to 0 (low) which will suppress expansion clock output.

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9.4.2.1 Normal Mode

This mode is supported by all chip selects, and is set by programming the following configuration bits:
• ALE_MODE = 0
• STRB_MODE = 0
• NAND_MODE = 0 (CS4 will be used as the 5th chip-delect)
Normal Mode is the default mode for all chip selects except for 5th chip-select which requires NAND_MODE to be
set to 0. Table 9-6 depicts the list of external pins that are valid when the Normal mode is set:

Table 9-6 Normal Mode Signals List

Port Name In/Out Clock Bus Width Description
EXP_CLK O hclk 1 Expansion clock to the peripheral devices. This clock is generated in the
Expansion block by dividing down the AHB clock by any of the following integers:
3, 4, 5, 6 or 7.
This clock is suppressed when EXP_CLK_EN is set to 0.
EXP_CSx O exp_clk 4 Chip Selects #0-3 are supported by default. enables and disables selection of the
targeted peripheral devices. Active level is configurable by software.
EXP_CS4 / O exp_clk 1 Chip Select #4. NAND_MODE configuration bit must be set low to access the 5th
EXP_NAND_WE_N peripheral. By default this pin is used as NAND flash write enable pin
(Exp_nand_we_n) when NAND_MODE is set high. The active level is configurable
by software.
EXP_RE O exp_clk 1 Read Enable. When asserted indicates a read operation from peripheral. Active
level is configurable by software.
EXP_WE O exp_clk 1 Write Enable. When asserted, indicates a write operation to peripheral. Active
level is configurable by software.
EXP_DM O exp_clk 2 Data Byte Mask. Input data byte to the peripheral device is masked when
EXP_DM is sampled high during a write access. One EXP_DM pin per data byte.
The timing of these signal is configurable by writing to DM_MODE field:
• 0: DM timing will mimic the EXP_CS.
• 1: DM timing will mimic the EXP_WE command.
EXP_RDY I exp_clk 1 Peripheral device ready/busy status. When set low indicates that the current
transaction is in progress. Set high when the device is ready for a new
transaction. Detection edge of this signal is configurable (high->low) or (low-
>high). When Detected will cause de-assertion of the CS and RE/WE for the
current transaction.
EXP_ADDR O exp_clk 25 Expansion Address Bus. Specifies one Memory location along with the DM[1:0]
when supported.
EXP_DATA B exp_clk 16 Data bus. MEM_BUS_SIZE is used to configure the peripheral interface width:
• 00: Peripheral has an 8 bits data bus interface.
• 01: Peripheral has a 16 bits data bus interface.
• 10: Not used in the Transcede 2xxx.
• 11: Reserved.

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Figure 9-2 shows the Normal Mode relative signals and their programmable fields.
Figure 9-2 Normal Mode Timing Diagram (RDY_EN = 0)

CS and the RE or WE command will be asserted, depend on the access type, after a programmed number of
expansion clock cycles from the active address. The expansion clock is a divide down frequency from the AHB
clock, it is generated from dividing down hclk by one of the configured divide integers (3, 4, 5, 6, or 7).
In the read cycle, the data bus is tri-stated and data is expected to be ready sometime after the assertion of the RE
command. The expansion controller will latch the data upon de-assertion of either the RE command or the CS
signal, whichever comes first. The CS is terminated after the expiration of the CS width count or upon detection of
the de-assertion of the RDY signal provided by the device (when enabled by setting EXP_RDY_EN to 1).
During the Write cycle, CS and WE command are asserted some programmable cycles after the valid address.
The external device is expected to latch the data by the de-assertion of the WE command. The data will be held
valid for some programmable cycles after the de-assertion of the CS.
Next Read/Write transaction can only be started after the expiration of the Data-hold time count.
When EXP_RDY_EN bit is set high, detected RDY pulse will be synchronized to AHB clock (HClk) before causing
the de-assertion of the CS and the RE or WE control signals. As was mentioned above, that the read data will be
latched upon de-assertion of the CS or RE signal, whichever comes first. A configuration bit per chip-select is
provided to enable/disable detection of the RDY signal and should be disabled for devices that do not provide the
RDY signals. If case of RDY is enabled and was not detected by the expansion controller before the de-assertion of
the CS, an error response will be indicated on the AHB interface for this transaction.
In Figure 9-3 in regards of the read and write commands, when a read access is being performed, only RE signal
will toggle. Also, when a write command is being performed, only WE command will toggle, not both.

NOTE: Depending on the synchronization timing of the assertion of EXP_RDY signal, it is

possible that the termination of CS/RE/WE will occur at the same cycle in which
EXP_RDY was asserted.

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Figure 9-3 Normal Mode Timing Diagram (RDY_EN = 1)

9.4.2.2 ALE Mode

This mode is supported by all chip selects, and is set by programming the following configuration bits:
• ALE_MODE = 1
• STRB_MODE = 0
• NAND_MODE = 0 (CS4 will be used)
ALE Mode can be supported by chip selects 0-3 by setting ALE_MODE bit to 1. Also chip select 4 shall support this
mode when ALE_MODE is set to 1 and NAND_MODE is set to 0. In this mode, the data bus will be used to transfer
both the valid address and valid data, Active high EXP_ALE will be used by the peripheral device to latch the valid
address. The valid address should be stable for the configured address hold time before placing valid data on the
bus in case of writes. Read data will be latched by the Expansion controller upon de-assertion of the EXP_RE
signal or EXP_CS, whichever comes first. Valid address will also be driven on the address bus, to provide support
for devices that may require it.

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Table 9-7 depicts the list of signals that are valid when the Synchronous mode is set:

Table 9-7 ALE Mode Signals List

Port Name In/Out Clock Bus Width Description
EXP_CLK O hclk 1 Expansion clock to the peripheral devices. This clock is generated in the
Expansion block by dividing down the AHB clock by any of the following integers:
3, 4, 5, 6 or 7.
This clock is suppressed when EXP_CLK_EN is set to 0.
EXP_CSx O Exp_clk 4 Chip Selects #0-3 are supported by default. enables and disables selection of the
targeted peripheral devices. Active level is configurable by software.
EXP_CS4 / O Exp_clk 1 Chip Select #4. CS4_EN configuration bit must be set high to support the 5th
EXP_NAND_WE_N peripheral. By default this pin is used as NAND flash write enable pin
(Exp_nand_we_n) when CS4_EN is set low. Active level is configurable by
software.
EXP_RE O Exp_clk 1 Read Enable. When asserted indicates a read operation from peripheral. Active
level is configurable by software.
EXP_WE O Exp_clk 1 Write Enable. When asserted, indicates a write operation to peripheral. Active
level is configurable by software.
EXP_DM O Exp_clk 2 Data Byte Mask. Input data byte to the peripheral device is masked when
EXP_DM is sampled high during a write access. One EXP_DM pin per data byte.
The timing of these signal is configurable by writing to DM_MODE field:
• 00: Disabled. DM signals will be masked.
• 01: DM timing will mimic the EXP_CS.
• 10: DM timing will mimic the EXP_WE command.
EXP_RDY I Exp_clk 1 Peripheral device ready/busy status. When set low indicates that the current
transaction is in progress. Set high when the device is ready for a new
transaction. Detection edge of this signal is configurable (high->low) or (low-
>high). When Detected will cause de-assertion of the CS and RE/WE for the
current transaction.
EXP_DATA B Exp_clk 16 Expansion multiplexed Address/Data Bus. During the address phase, EXP_ALE
pulse is used by the peripheral to latch the address. After address hold-time the
data will be valid on the bus.
MEM_BUS_SIZE is used to configure the peripheral interface width:
• 00: Peripheral has an 8 bits data bus interface.
• 01: Peripheral has a 16 bits data bus interface.
• 10: Not supported by the Transcede 2xxx.
• 11: Reserved.
EXP_ALE O Exp_clk 1 Address latch enable pulse, used by the peripheral device to latch the valid
address.
EXP_ADDR O Exp_clk 25 Expansion Address Bus.

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Figure 9-4 shows the ALE Mode relative signals and their programmable fields.
Figure 9-4 ALE Mode Timing Diagram

9.4.2.3 Strobe Mode

This mode is supported by all chip selects, and is set by programming the following configuration bits:
• ALE_MODE = 0
• STRB_MODE = 1
• NAND_MODE = 0 (will use CS4)
This mode can be supported by chip selects 0 to 3 by setting STRB_MODE bit to 1. Also chip select 4 shall support
this mode when STRB_MODE is set to 1 and NAND_MODE is set to 0. In this mode, EXP_WE# pin will be used by
the peripheral device as EXP_RW# command signal. Also, EXP_RE# pin will be used by the peripheral as the
EXP_STRB command strobe signal. The active level of these two signals is configurable, depending on the polarity
supported by the peripheral device.
Table 9-8 depicts the list of signals that are valid when the Command Strobe mode is set:

Table 9-8 Command Strobe Mode Signals List

Port Name In/Out Clock Bus Width Description
EXP_CLK O hclk 1 Expansion clock to the peripheral devices. This clock is generated in the
Expansion block by dividing down the AHB clock by any of the following integers:
3, 4, 5, 6 or 7.
This clock is suppressed when EXP_CLK_EN is set to 0.
EXP_CSx O Exp_clk 4 Chip Selects #0-3 are supported by default. enables and disables selection of the
targeted peripheral devices. Active level is configurable by software.
EXP_CS4 / O Exp_clk 1 Chip Select #4. CS4_EN configuration bit must be set high and NAND_MODE
EXP_NAND_WE_N must be low, to support the 5th peripheral. By default this pin is used as NAND
flash write enable pin (Exp_nand_we_n) when NAND_MODE is set high. Active
level is configurable by software.

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Table 9-8 Command Strobe Mode Signals List (Continued)

Port Name In/Out Clock Bus Width Description
EXP_RE / EXP_STRB O Exp_clk 1 Command Strobe. By default, when set low, This signal is used by the peripheral
for command strobing. Active level is configurable by software.
EXP_WE / EXP_RW O Exp_clk 1 Read/Write Enable. By default, When set high, indicates a read operation from
peripheral. When asserted low, indicates a write transaction to the peripheral.
Active level is configurable by software.
EXP_DM O Exp_clk 2 Data Byte Mask. Input data byte to the peripheral device is masked when
EXP_DM is sampled high during a write access. One EXP_DM pin per data byte.
The timing of these signal is configurable by writing to DM_MODE configuration
bit:
• 0: DM timing will mimic the EXP_CS timing. (Default)
• 1: DM timing will mimic the EXP_WE command timing.
EXP_RDY I Exp_clk 1 Peripheral device ready/busy status. When set low indicates that the current
transaction is in progress. Set high when the device is ready for a new
transaction. Detection edge of this signal is configurable (high->low) or (low-
>high). When Detected will cause de-assertion of the CS and RE/WE for the
current transaction.
EXP_ADDR O Exp_clk 25 Expansion Address Bus. Specifies one Memory location along with the DM[1:0]
when supported.
EXP_DATA B Exp_clk 16 Data bus. MEM_BUS_SIZE is used to configure the peripheral interface width:
• 00: Peripheral has an 8 bits data bus interface.
• 01: Peripheral has a 16 bits data bus interface.
• 10: Not supported by the Transcede 2xxx.
• 11: Reserved.

Figure 9-5 shows the Strobe Mode relative signals and their programmable fields.
Figure 9-5 Strobe Mode Timing Diagram

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NOTE: In this mode, both EXP_RW# and EXP_STRB# signals shall be switching within read
and write transactions. The read data will be sampled by the expansion block upon de-
assertion of the EXP_CS or EXP_STRB, whichever comes first.

9.4.2.4 NAND Mode

This mode is relevant for CS4 only, chip select #4 will be used as the NAND write enable signal (Exp_nand_we_n).
Not supported by the chip selects #0-3. This mode is set by programming the following configuration bits (set by
default):
• ALE_MODE = 0
• STRB_MODE = 0
• NAND_MODE = 1 (disables CS4)

NOTE: For NAND mode, chip select will be used from a GPIO pin. In the Transcede 2xxx
GPIO28 is used to drive nand_cs when in NAND mode.
When NAND mode is disabled, NAND_MODE=0, then exp_nand_we_n can be used as
a generic Flash chip select.

The chip select and latch controls for this mode are provided by a dedicated GPIO pin. NAND_RE/NAND_WE
commands, address and data are initiated by the expansion block as an expansion cycle. Each NAND transaction
should be broken up into several expansion (Normal Mode type) transactions. The software has the ultimate
control over NAND transactions. NAND ECC support is also provided by software only.
Table 9-9 depicts the list of signals that are valid when the NAND mode is set:

Table 9-9 NAND Mode Signals List

Port Name In/Out Clock Bus Width Description
NAND_CS_N (GPIO) O hclk 1 Chip Selects. Enables and disables selection of the targeted NAND peripheral
device. Driven by software.
NAND_RE_N O Exp_clk 1 Read Enable dedicated for NAND flash, when asserted low, indicates a read
operation from flash device. Assertion level of this signal is configurable.
NAND_WE_N O Exp_clk 1 Write Enable dedicated for NAND flash, when asserted low, indicates a write
operation to the flash device. When NAND is not used, this pin can be configured
as a peripheral chip-select. Assertion level of this signal is configurable.
NAND_RDY (GPIO) I hclk 1 NAND operating condition Ready/Busy#. When high indicates that the device is
ready for access. When set low indicates no access will be granted.
NAND_ALE (GPIO) O hclk 1 NAND Address Latch Enable. The NAND_ALE output controls writing to the
address register. When ALE is high, the address is loaded on the rising edge of
WE#. NAND_ALE must remain high during the entire address sequence.
NAND_CLE (GPIO) O hclk 1 NAND Command Latch Enable. The CLE output controls writing to the command
register. When CLE is high, the command is loaded on the rising edge of WE#.
EXP_DATA B Exp_clk 16 Expansion multiplexed Address/Data Bus. During the address phase, NAND_ALE
pulse is used by the peripheral to latch the address. After address hold-time the
data will be valid on the bus.
MEM_BUS_SIZE is used to configure the peripheral interface width:
• 00: Peripheral has an 8 bits data bus interface.
• 01: Peripheral has a 16 bits data bus interface.
• 10: Not supported by the Transcede 2xxx.
• 11: Reserved.

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Figure 9-6, Figure 9-7, and Figure 9-8 show the timing diagrams respectively for command latch, address latch,
and data latch in the NAND mode.
Figure 9-6 NAND Command Latch Timing Diagram

NAND_CLE (GPIO)

NAND_CS (GPIO)

NAND_WE

NAND_ALE (GPIO)

EXP_Data Command

Figure 9-7 NAND Address Latch Timing Diagram

NAND_CLE (GPIO)

NAND_CS (GPIO)

NAND_WE

NAND_ALE (GPIO)

EXP_Data Addr1 Addr2 Addr3

Figure 9-8 NAND Data Latch Timing Diagram

NAND_CLE (GPIO)

NAND_CS (GPIO)

NAND_ALE (GPIO)

NAND_WE

EXP_Data Data1 Data2 DataN

Each toggle of WE or RE to access the NAND flash will be executed over a full expansion cycle, from the point view
of the expansion bus, it is an expansion cycle in normal mode. The software initiates a transaction in the NAND
allocated address space, which will cause an expansion cycle to be started. During the NAND Address cycle or the
NAND Command cycle, the software will initiate the write transaction to the NAND address space placing the
NAND address or command type value on the data bus. The expansion controller will issue a write access to the
NAND flash, as if accessing a generic device. The software at the meantime will drive the NAND chip-select and
the controls (CLE/ALE) through dedicated GPIO pins.

NOTE: NAND_RE and NAND_WE will not be toggled when there is an access to CS#0-3.

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9.5 External Boot

Chip-select 0 is dedicated for external boot when used. By default, EXP_CS0 is enabled and configured to operate
in the Normal Mode. The External flash bus width is determined by the two input pins to the expansion block. Mode
fields are configured as the following:
• ALE_MODE = 0
• STRB_MODE = 0

9.6 Clocks
One clock is input to the expansion block running at AHB clock rate (150 MHz). The expansion block has a built in
ExpClk Generator, which is responsible of generating a divided synchronous clock to the external peripherals with
a maximum of 50 MHz. A clock switch selects, glitch-free, between AHB clock and the divider output, and shall
default to AHB Clock upon reset and will switch to the divided AHB clock right after reset ends.
Power down logic shall be default to activate the clock. When reset is asserted, output clock might have glitches
when switching to reference clock.
This clock generator circuitry can be configured to divide the AHB clock with the following divide values: 3-6 and 7.
The internal logic of the expansion bus will be running at AHB clock speed, and the generated synchronous clock
(EXPCLK) will be treated as a synchronizing pulse enable for the programmable timing counters.
Figure 9-9 shows the expansion bus clock generation.
Figure 9-9 Expansion Bus Clock Generation

Divide Ratio
clk
ratio [4:0] switch

AHBCLK Clock sel

Divider 0 Clock
Switch PWR EXPCLK
1
REFCLK DWN
expclk pwr dwn

9.7 Reset
Asynchronous reset will be used to reset the block’s internal logic. This reset may be a combination of the HW and
SW resets provided by the chip and is synchronized externally to the AHB clock. A self-clear soft reset can be
generated by the block’s internal configuration logic when asserted by software. This self-clear reset will reset the
entire block’s logic synchronously. Configuration registers are not affected by the block’s soft-reset.

9.8 Enable /Disable Mechanism

This block will not have an enable/disable signal. It will be either selected of de-selected by the external AHB
decoding logic. When a transaction is being performed to this block’s allocated address space, this block will be
selected to complete the requested transaction. Otherwise, this block will be de-selected.

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9.9 Memories
No memories are instantiated in this block.

9.10 Expansion Interface AC Timing

Figure 9-10 shows the expansion interface AC timing diagram.
Figure 9-10 AC Timing Diagram

Table 9-10 describes the AC timing parameters.

Table 9-10 AC Timing Parameters

Max.
Symbol Parameter Min. Unit Comments
Load 50pf
- EXP_CLK (Frequency) 35.7 50 MHz -
- EXP_CLK Duty cycle 40 60 % -
Tod Expansion Outputs relative the rising edge of the EXP_CLK 0 11 ns 1
(Output Delay Time)
Tis Expansion Inputs Setup Time for read data with respect to the rising edge 1 - Cycle 2
(When Trdy is not used)
Tih Expansion Inputs Hold Time for read data with respect to the rising edge 0 - ns 3
(When Trdy is not used)
Trdy Ready Input required pulse width 9 - ns 4
Tvd Expected valid data after the rising/falling edge of the RDY Pulse. Since - 0 ns 5
the active low RDY edge detection is configurable.

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Table 9-10 AC Timing Parameters (Continued)

Max.
Symbol Parameter Min. Unit Comments
Load 50pf
Notes:
1. Test Load 50pF.
2. Tis (min) value should be configured to be at least 1 EXP_CLK cycle.
3. Tih timing is relevant to the cycle in which CS and/or RE is de-asserted.
4. RDY is sampled and synchronized by HCLK (150 MHz).
5. Due to RDY synchronization logic before valid input data latching.

Pay attention to the following points regarding the asynchronous interface:

• When Expansion output signals are changing on the same clock edge, the delay between these signals is
considered to be between 0 and 11 (ns).
• When Expansion output signals are changing on different clock cycles, the maximum delay between these
signals is considered to be: Nx(Period of EXP_CLK)-11 (ns) to Nx(Period of EXP_CLK)+11 (ns) where N
depends on the configured parameters.
• The read data (if exp_rdy is not used) relative to rising edge of CS or RE (whichever de-asserted first) should
be at least (EXP_CLK Period)+11 (ns).
• Upon EXP_RDY de-assertion state, expansion transaction may be completed within two EXP_CLK cycles
when relative configuration parameters are set to minimum values.
• The cycle in the figure in which the read data is sampled upon de-assertion of RE and/or CS whichever comes
first.
• While in Asynchronous mode (when RDY is used), the design does not guarantee the relationship between the
CS and RE/WE signals. Since the detection of RDY pulse will cause the de-assertion of the CS and RE/WE
signals simultaneously.

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10 Inter-IC Interface (I2C)
This chapter introduces the features, functions, and timing of the I2C interface.

10.1 Feature List

• Conforms to V2.1 of the I2C specification.
• Master or slave operation
• Multi-master systems supported
• Supports both 7-bit and 10-bit addressing on the I2C bus
• Own address and General Call (data broadcast) address detection
• Performs arbitration and clock synchronization
• Interrupt on address detection
• Supports High Speed (HS), Fast and Standard transfer rates
• Bus isolation support
• Allows operations from a wide range on input clock frequencies

10.2 Implementation Details

I2C is an industry-standard, low-bandwidth, short distance protocol for on-board communications. All devices are
connected through two wires: serial data (SDA) and serial clock (SCL).

All I2C devices must have a unique address to identify it on the bus. Slave devices have a predefined address, but
the lower bits of the address can be assigned to allow for multiples of the same devices on the bus.

The Transcede 2xxx device operates as a master, a slave, or in multi-master mode. It supports all I2C speeds:
standard (100 kbps), fast (400 kbps) and high speed (3.4 Mbps). The Transcede 2xxx I2C interface includes a
programmable clock divider to allow adjustment of data speed over a wide range. However, the Transcede 2xxx
I2C interface does not include an output signal for direct control of a bridge between fast/standard and high-speed
bus segments. Thus, the Transcede 2xxx I2C interface is typically configured to accommodate the slowest device
on the bus.

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10.3 I2C Timing

Figure 10-1 shows the I2C timing waveform. Table 10-1 lists the values of I2C setup and hold time.
Figure 10-1 I2C Timing Waveform

I2C_SCL

Tsu;sta Thd;sta Tsu;sto

I2C_SDA

I2C_SCL

Tis Tih

I2C_SDA
(input)

Tod Toh

I2C_SDA
(output)

Table 10-1 I2C Setup and Hold Time

Symbol Parameter Minimum Maximum Units Comments

- Clock Frequency - 3.4 - -

- Clock Duty Cycle Low period High period 160, 60 - ns -

Tsu;sta (Repeated) START condition setup time 160 - ns See note 1 and 2

Thd;sta (Repeated) START condition hold time 160 - ns See note 1 and 2

Tsu;sto STOP condition setup time 160 - ns See note 1 and 2

Tis Input Setup Time 10 - ns -

Tih Input Hold Time 0 - ns -

Tod Output Delay Time - 60 ns See note 3 and 4

Toh Output Hold Time 0 - ns -

Notes:
1. These numbers can be extended when using a slower output clock (master mode).
2. This number increases as clock frequency slows down, according to the formula: Tsu;Tsta(min) = Thd;sta(min) = Tsu;sto(min) = 2N x TAXI
where TAXI is the AXI clock period, and N is a parameter that is used to set the I2C clock frequency according to the AXI clock frequency.
3. Output delay time is not defined in standard. The Transcede 2xxx value should guarantee meeting the timing at the receiver.
4. This number increases as clock frequency is slower, according to the following formula: Tod(max) = 2N+1 x (M+1) x TAXI
where TAXI is the AXI clock period, and N and M are parameters that are used to set the I2C clock frequency according to the AXI clock frequency

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11 Serial Peripheral Interface (SPI)
and High Speed SPI
This chapter describes features, functions and timing of SPI interface.
The Transcede 2xxx device has a Serial Peripheral Interface (SPI) and an extra SPI interface called High Speed
(HS) SPI interface with Direct Memory Access (DMA) capability.

11.1 Feature List—SPI

• Serial interface operation – Motorola SPI.
• Clock bit-rate – User can dynamically control the serial bit rate of the data transfer.
• Serial Master – Enables serial communication with serial slave peripheral devices.
• Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive
FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.
• Data frame size (4 to 16 bits) – The frame size of each data transfer is under the control of the programmer.
• FIFO depth – The depth of the transmit and receive FIFO buffers is 128 words. The FIFO width is fixed at 16
bits.
• Number of slave select outputs – 4 serial slave select output signals can be generated.
• Hardware/software slave-select – Dedicated hardware slave-select lines can be used or software control can
be used to target the serial slave device.
• Max Clock frequency–16 MHz

11.2 Feature List—High Speed SPI

A multi-chain SPI provides a common interface mechanism for controlling peripheral devices. For example, SLICs
from multiple vendors can be controlled on the SPI Bus. The DMA is added so that the interface can work at a
higher frequency than LS-SPI and support data transfer speed upto 50MHz.
• Serial interface operation - Motorola SPI
• Can be controlled by the DMA unit or directly by CPU via the DMA slave port
• Support for clock rates up to 50 MHz
• Clock bit-rate - user can dynamically control the serial bit rate of the data transfer
• Data frame size (4 to 16 bits) - The frame size of each data transfer is under the control of the programmer
• Depth of transmit and receive FIFO buffers is 32 words deep. The FIFO width is fixed at 16 bits.
• 2 serial slave select output
• Master only without multi-master support
• Includes logic to allow a programmable delay on the sample time of the rxd input signal - up-to 10 AHB clock
cycles

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11.3 Functional Description

The SPI interface includes the following blocks:
• APB Interface: provides standard data and control paths to the ARM processors
• Register Block: includes ARM-addressable registers.
• Transmit and Receive FIFO Control: Includes FIFO overflow, underflow, and interrupt logic generating FIFO
overflow, full, underflow and empty interrupts.
• Transmit and Receive FIFO Memory: flow buffers of 8 16-bit words.
• Interrupt Logic: Generates interrupts due to SPI bus master contention and masking of interrupts and
consolidation into a single interrupt.

11.4 Implementation Details

Figure 11-1 Hardware/Software Slave Selection

Master Slave Master Slave

Data Bus Data Bus

ss_o ss ss
ss

ss_x
.
.
.

Slave Slave

ss ss
A B

ss = slave select line

The SPI Controller can connect to any serial slave peripheral device that supports the Motorola Serial Peripheral
Interface (SPI) – a four-wire, full-duplex serial protocol. There are four possible combinations for the serial clock’s
phase and polarity. The clock phase (SCPH) determines whether the serial transfer begins with the falling edge of
the slave select signal or the first edge of the serial clock. The slave select line is held high when the SPI controller
is idle or disabled.

The serial protocols supported by the SPI controller allow for serial slaves to be selected/addressed using either
hardware or software. When implemented in hardware, serial slaves are selected under the control of dedicated
hardware select lines. The number of select lines generated from the serial master is equal to the number of serial
slaves present on the bus. The serial master device asserts the select line of the target serial slave before data
transfer begins. When implemented in software, the input select line of each serial slave can either originate from a
single slave select output pin on the serial master (user must configure the master to have one slave select output)

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or be permanently grounded. The main program in the software domain controls the selection of the target slave
device.

The SPI controller does not enforce hardware or software control for serial slave device selection. The user can
configure the SPI controller for either implementation.

11.5 SPI Timing

Figure 11-2 and give the SPI timing details.
Figure 11-2 SPI Timing Waveforms

SPI_SCLK

Tis Tih

SPI_RXD

Tod Toh

SPI_TXD

Table 11-1 AC Timing Parameters—LS SPI (SPI_1)

Symbol Parameter Min. Max. Units Comments

Clock edge rate (all clocks) 0.25 2 V/ns 5
SPI_SCLK Frequency 16 MHz
14 MHz 3,6
Clock Duty Cycle (all clocks) 40 60 %
Tis Input Setup Time 11 ns 1
12.5 3,6
Tih Input Hold Time 2 ns 1

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Table 11-1 AC Timing Parameters—LS SPI (SPI_1) (Continued)

Symbol Parameter Min. Max. Units Comments

Tod Data Output Delay 5 ns 1,2,3
Toh Data Output Hold -5 ns 1,2,4
Notes:
1. Input can be referenced to either rising or falling edge of the clock. Output is always referenced to the opposite edge than that of the input.
2. SPI_SS# signals can be configured when output clock is not active. Hence, AC requirements are not applied. In STA we need to verify that its
output delay is ±5ns of delay of other output signals.
3. Max load is 50 pF
4. Min load is 5 pF
5. Values guaranteed by characterization; not 100% tested in production.
6. The maximum frequency is lower frequency than 16 MHz when max load is used.
7. In order to use the interface at max frequency with max load, the IO pads should be configured to max during strength (for example, x4).

Table 11-2 AC Timing Parameters—HS SPI (SPI_0)

Symbol Parameter Min. Max. Units Comments

Clock edge rate (all clocks) 0.1 2 V/ns 6
SPI0_SCLK Frequency MHz
50
Clock Duty Cycle (all clocks) 46 53 %
Tis Input Setup Time ** ns 1,5
Tih Input Hold Time ** ns 1,5
Tod Data Output Delay 1.5 ns 1,2,3
Toh Data Output Hold -0.5 ns 1,2,4
Notes:
1. Input can be referenced to either rising or falling edge of the clock. Output is always reference to the opposite edge than that of the input.
2. SPI_SS# signals are configured when output clock is not active, thus have no AC requirements.
3. Max load is 15pF
4. Min load is 5pF
5. During board design, it needs to take into account the output delay of external device (because it is based on input clock) and the round trip
delay. Logically the Transcede 2xxx SPI module allows a programmable delay on the sample time of the rxd input signal - up-to 10 AHB clock
cycles
6. Values guaranteed by characterization; not 100% tested in production
7. **A training sequence is needed in order to select the right delay element should be used. In order to have a reliable operation the training
sequence would need to have at least 3 good sampling points so mid point can be selected. For 250MHz AXI clock that means a valid window of
at least 13ns.

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11.6 High Speed SPI DMA

DMA provides the following features:
• AHB-Central DMA Controller core that transfers data from/to HS SPI and UART peripheral blocks from/to DDR,
IRAM or CRAM
• AHB master interface for data transfer
• AHB slave interface is used to configure the DMA and also provide a direct access the peripheral registers as
well
• Up to eight channels, one per source and destination pair
– Unidirectional channels - data transfers in one direction only
– Programmable channel priority
• Hardware handshaking interfaces for source and destination peripherals
• Enabling and disabling of individual DMA handshaking interfaces
• Programmable flow control at block transfer level

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12 Universal Asynchronous Receiver /
Transmitter (UART) Interface
This chapter introduces the features and implementation details of the Transcede 2xxx Universal Asynchronous
Receiver / Transmitter (UART) module.
The Transcede 2xxx features two UART interfaces, of which one is the independent high speed UART (HS-UART)
interface.

12.1 Feature List—UART

• Transmit and receive FIFOs
• Modeled after industry standard 16550
• Asynchronous mode
• The receiver is normally programmed to automatically determine the baud rate of the transmitter. The receiver
relocates the center of the start bit of each new word or byte. This feature enables the asynchronous mode to
operate without sharing the actual baud rate clock
• Transmitter adds start, stop, parity bits to the serial data
• Receiver rejects false start bits
• 5, 6, 7 or 8 bit characters
• Even, odd, or no parity bit generation or detection
• 1 or 2 stop bit generation, programmable short stop bit control
• Transmitter buffer empty flag or under-run status generation
• Receiver buffer full detection
• Receiver status error flags: over-run, parity, frame and break interrupt
• FIFO depth is a synthesis parameter and can be NONE, 16, 32, …, 2048. A 16 deep FIFO will be used in the
Transcede 2xxx.

12.2 Feature List—HS-UART

The Transcede 2xxx device provides one independent high speed UART interface. The Rx and Tx signals are used
to be connected to an RS232 driver for standard serial port operation. The UART interfaces provide a useful
console port and can also be used as a software debug port. It is recommended to connect the UART pins to
standard connectors such as RJ45, 9-pin DIN for easy access.
• Can be controlled by the DMA unit or directly by CPU via the DMA slave port
• Programmable character properties, such as number of data bits per character (5-8), optional parity bit (with
odd or even select) and number of stop bits (1, 1.5 or 2) Line break generation and detection
• DMA signaling with two programmable modes
• Transmit and receive FIFO
• Transmitter adds start, stop, parity bits to the serial data
• Programmable serial data baud rate

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• HS-UART port includes flow control signaling (RTS and CTS)

• HS-UART port can support up to 3 Mbps throughput
• HS-UART RTS and CTS signals are muxed with GPIOs and are selected by default

12.3 Implementation Details

The UART is used to serially receive and transmit data to a peripheral. The transmitter performs the parallel to
serial conversion adding start, stop, and parity bits to the serial data. The receiver uses the stop/start transition to
approximate the center of the data, parity, and stop bits that follows.

In the asynchronous mode, the transmitter and receiver are set to operate at a given baud rate from a table of
standard baud rates. Other than the baud information, no clock is passed between them. The receiver is normally
programmed to automatically determine the baud rate of the transmitter. Absolute baud rate accuracy is not
required because the receiver relocates the center of the start bit of each new word or byte. It is this feature that
enables the asynchronous mode to operate without sharing the actual baud rate clock. The receiver rejects false
bits.

On the Rx direction, there is a read-only register (called RBR) contains the data byte (data character) received on
the serial input port (sin). There are also FIFOs on the receive side and the FIFOs can be enabled or disabled by
software. When FIFOs are disabled, the data in RBR must be read before the next data arrives, otherwise it will be
overwritten, resulting in an overrun error. When FIFOs are enabled, RBR accesses the head of the receive FIFO. If
the receive FIFO is full and RBR is not read before the next data character arrives, then the data already in the
FIFO will be preserved but any incoming data will be lost. An overrun error will also occur.

On the Tx direction, there is a transmit holding register (called THR) that contains the data to be transmitted on the
serial output port (sout). There are also FIFOs on the transmit side and FIFOs can be enabled or disabled by
software. When FIFOs are disabled, a single character can be written to THR when THR is empty. Any additional
writes to the THR before it is empty again causes the previous data in THR to be overwritten. When FIFOs are
enabled, data character can be written to the transmit FIFO when it is not full. Any attempt to write data when FIFO
is full results in the write data being lost.

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13 General Purpose Input Output
(GPIO)
This chapter provides features and implementation details of GPIO.

13.1 Feature List

• Up to 32 General Purpose Input Output interface signals for specific control, monitoring signaling purpose.
• Each GPIO pin has output current capability to drive an external LED.
• Eight GPIO input pins [07:00] can be programmed to generate interrupts to the ARM MPCores with rising or
falling or both edges of input signals by setting the corresponding GPIO interrupt enable register bits. Input
signals are synchronized before the generation of the interrupts.

13.2 GPIO Muxing

The Transcede 2xxx provides up to 32 GPIO signals. 10 GPIO signals are dedicated and 22 GPIO signals are
muxed with other functional pins where by default the GPIO function is not selected.
Table 13-1 listed the GPIO muxing information.

Table 13-1 GPIO Muxing

Mux Options

Option 1 (Default) Option 2 Option 3

Signal Name
misc_pin_sel[9]=1 (for JESD
FUNC pin_sel_1/2 [x:y]=11 select) misc_pin_sel[8]=1 (for
USIM select)
GPIO00 GPIO00 — —
GPIO01 GPIO01 — —
GPIO02 GPIO02 — —
GPIO03 GPIO03 — —
GPIO04 GPIO04 — —
GPIO05 GPIO05 — —
GPIO06 GPIO06 — —
GPIO07 GPIO07 — —
GPIO08 GPIO08 — —
GPIO09 GPIO09 — —
GPIO10 GPIO10 TDM0_CK —
GPIO11 GPIO11 TDM0_FS —
GPIO12 GPIO12 TDM1_CK USIM_RST_N

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Table 13-1 GPIO Muxing (Continued)

Mux Options

Option 1 (Default) Option 2 Option 3

Signal Name
misc_pin_sel[9]=1 (for JESD
FUNC pin_sel_1/2 [x:y]=11 select) misc_pin_sel[8]=1 (for
USIM select)
GPIO13 GPIO13 TDM1_FS USIM_VSEL33
GPIO14 GPIO14 TDM_CLK —
GPIO15 GPIO15 TDM_FSYNC —
I2C_SCL I2C_SCL GPIO16 —
I2C_SDA I2C_SDA GPIO17 —
SPI_S1_SS0_N SPI_S1_SS0_N GPIO18 —
SPI_S1_SS1_N SPI_S1_SS1_N GPIO19 JESD0_CPCSB
UART0_RTS_N UART0_RTS_N GPIO20 —
UART0_CTS_N UART0_CTS_N GPIO21 —
UART_S1_RX UART_S1_RX GPIO22 —
UART_S1_TX UART_S1_TX GPIO23 —
EXP_CS2_N EXP_CS2_N GPIO24 —
EXP_CS3_N EXP_CS3_N GPIO25 USIM_FCB
EXP_RDY EXP_RDY GPIO26 —
EXP_ALE EXP_ALE GPIO27 —
EXP_NAND_CS EXP_NAND_CS GPIO28 —
EXP_NAND_RDY EXP_NAND_RDY GPIO29 —
SPI_S1_TXD SPI_S1_TXD GPIO30 JESD0_CMOS
SPI_S1_RXD SPI_S1_RXD GPIO31 JESD0_CMISO
Note: The option mode is set independently in the GPIO register for each GPIO bit.

13.3 GPIO Timing

Figure 13-1 shows the GPIO timing diagram.
Figure 13-1 GPIO Timing Diagram

Thgp

GPIO
(input)

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Table 13-2 AC Timing Parameters—GPIO

Symbol Description Min Max Units
Thgp GPIO pulse duration 10 ns
Note:
This is the minimal pulse width time for a GPIO (such as an input) that is guaranteed to internally register a change. The minimum width must be
larger than Fabric clock period. The 10ns is for the case a 125 MHz clock is the slowest Fabric clock frequency.

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14 Time-Division Multiplexing (TDM)
Bus Interface
This chapter provides hardware details about the TDM bus interface.

14.1 Feature List

• Provides up to four full-duplex, serial Time-Division Multiplexing (TDM) buses for digital data transfer between
a Network Interface Device (for example, T1/E1 Framer, Time Slot Interchanger, SLIC, and so on) and the
Transcede 2xxx device.
• TDM interface timing parameters are programmable, and can be configured for H.100, H.110, and H-MVIP bus
standards.
• The Transcede 2xxx provides a maximum of 512 timeslots. The TDM interface configurations for different
timeslot options are as follows:
– Two TDM buses running at 16.384 MHz (2 x 256 timeslots)
– One TDM bus running at 32.768 MHz (1 x 512 timeslots)

NOTE: The support for 512 timeslots is enabled as a separate mode by software configuration.
When the mode is enabled, only TDM0 interfaces will be active.

NOTE: Slower CLK frequencies can be used for fewer timeslots. For example:
• 32.768 MHz for 512 timeslots per bus.
• 16.384 MHz for 256 timeslots per bus.
• 8.192 MHz for 128 timeslots per bus.

14.2 Functional Description

The TDM bus supports speeds of 1.536 MHz to 32.768 MHz, allowing between 24 and 512 timeslots. Dual-rate
clock, up to 32.768 MHz, is also supported, where data is held for two clock cycles. In x2 mode, data is sampled
every two clock cycles.

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14.3 TDM Bus Cycle Timing

Figure 14-1 through Figure 14-8 show the TDM Bus timing and how clock edges are counted in cycles. Cycles are
defined as always beginning (with cycle 0) on the rising TDM_CK edge relative to the clock edge on which
TDM_FS is sampled. Data transmission can begin on any clock cycle relative to cycle 0 by programming the
appropriate cycle value in the CYCX parameter in the Transmitter Operating Configuration Register and the CYCR
parameter in the Receiver Operating Configuration Register. Each TDM Bus interface can operate in the single-
clock or double-clock mode. One data bit is transmitted or received every TDM_CK period or every two TDM_CK
periods as programmed by the CMSX bit in the Transmitter Operating Configuration Register and the CMSR bit in
the Receiver Operating Configuration Register.
Figure 14-1 Transmit Timing (FE = 1, CMSX = 0)

Figure 14-2 Transmit Timing (FE = 0, CMSX = 0)

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Figure 14-3 Received Timing (FE = 1, CMSR = 0)

Figure 14-4 Received Timing (FE = 0, CMSR = 0)

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Figure 14-5 Transmit Timing (FE = 1, CMSX = 1)

Figure 14-6 Transmit Timing (FE = 0, CMSX = 1)

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Figure 14-7 Received Timing (FE = 1, CMSR = 1)

Figure 14-8 Received Timing (FE = 0, CMSR = 1)

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14.4 TDM Interface AC Characteristics

The TDM interface timing parameters are programmable, and can be configured for H.100, H110, and H-MVIP bus
standards.
Figure 14-9 TDM Bus Timing

TDM_CK

Tfs Tfh
TDM_FS
(input)

Tdis Tdih

TDM_DR

Tdod Tdoh
TDM_DX
TDM_FS
(output)
Tdoz

Table 14-1 TDM Bus Timing

Symbo Parameter Min Typ Max Units Notes
Clock edge rate (All Clocks) 0.25 2 V/ns 1
Tcp Clock TDMCK Period 31 ns
Tch Clock TDMCK High Time 0.4xTcp 0.6xTcp ns
Tel Clock TDMCK Low Time 0.4xTcp 0.6xTcp ns
Tfs Frame Synch Setup Time 0.5xTcp ns 4,5,6
Tfh Frame Synch Hold Time 0.5xTcp + 2.5 ns 4,5,6
Tdis Data Input Setup Time 0.5xTcp ns 3,4
Tdih Data Input Hold Time 2.5 ns 2,4
Tdod Data Output Delay Time 0.5xTcp ns 2,4,6
Tdoh Data Output Hold Time 2 ns 2,4,6
Tdoz Data Output Hi Z Time 0.5xTcp ns 2,4,6

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Table 14-1 TDM Bus Timing (Continued)

Symbo Parameter Min Typ Max Units Notes
Notes:
1. The rise and fall times are determined by the edge rate in V/ns. A “Max” edge rate is the fastest rate at which a clock transitions.
2. Test Load = 50 pF.
3. Test Load = 5.0 pF
4. Measured at the transmitter.
5. Measured at the receiver.
6. Test Conditions:
• VCORE = +1.1 + 0.03 VDC, -.03 VDC
7. Tj = -25°C to 110°C
8. Please note that all inputs can be programmed to be sampled at either rising or falling edge of the clock. All outputs can be programmed to be
generated at either rising or falling edge of the clock.
9. Please note that the Frame Synch can be programmed as either active low or active high.

14.5 TDM Input-to-Output Loopback Timing

When this external and remote loopback is enabled, TDM_DR is looped back to TDM_DX without any sampling.
Figure 14-10 TDM Loopback Timing Diagram

Table 14-2 TDM Loopback Timing Parameters

Symbol Description Min Max Units Comments

Tdel Input to output delay 2 20 ns —

14.6 Network Timing Generator (NTG) for TDM

The Transcede 2xxx device features two Network Timing Generator (NTG) instances:
• One NTG block to support generation of TDM Clocks and Frame-Syncs.
• One NTG block to support GEMAC 1588 network clock.
The NTG block has the following features:
• Supports 1...216 division of high-speed clock source
• Supports accuracy to 2-32 fraction of the high-speed clock period
• Uses both rising and falling high-speed clock edges for reduced jitter

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• Hardware support for software phase adjustment

• Secondary integer divider extends division to 232
• Secondary integer divider provides control of duty cycle
The NTG block consists of a primary real number divider and a secondary integer divider. No analog components
are used in this circuit. The programmability of the NTG allows it to satisfy the requirements of many clock
generation applications.
One application of the NTG is to provide a bit clock and frame sync pulse for a TDM interface based on software
programmability. The bit clock is generated by the primary divider. The fractional term of the primary divider
provides high frequency accuracy. The frame sync pulse is generated by the secondary divider. The secondary
divider has programmability to control the pulse width and polarity. The frame pulse may also be made to occur on
the rising or falling bit clock edge.
Another application of the NTG is to provide a bit clock and frame sync pulse for a TDM interface based on a frame
reference input. A phase detector compares the frame reference to the generated frame sync pulse and provides
feedback to the primary divider. This feedback determines the primary divide ratio and can be generated using a
choice of algorithms. One feedback algorithm is modeled after a second order PID loop filter equation (RLC circuit)
using the phase error as a stimulus waveform. Another feedback algorithm computes the ideal divide ratio based
on the measured phase error.
Also the NTG may be configured to provide a general purpose clock with programmable frequency and duty cycle.
The primary and secondary dividers work together in series to produce the desired output waveform. Software
determines the divider ratio and duty cycle.

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15 Universal Serial Bus (USB) Interface
This chapter provides hardware details about the USB bus interface.

15.1 Feature List

• One USB 2.0 controller and PHY interface
• USB 2.0 and USB 1.1 compliance
• Can be configurable to act as host-only or device-only
• LS is not supported in Device mode
• OTG mode is not supported
• Number of device mode endpoints is 6 (in addition to control endpoint 0)– 2 for Isochronous, 2 for Interrupt and
2 for Bulk
• Number of Host Mode Channels is 14
• Total Data FIFO is 4KB
• Supports a generic root hub
• USB supports suspend mode
• AHB master
• Internal DMA with scatter/gather option
• Max packet size is: 1024B for ISOCHRONOUS and Interrupt; 512B for Bulk
• Link Power Management is supported
• Controller - PHY interface is 8/16 bits (software-selectable for flexibility) UTMI + Level3

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16 Universal Subscriber Identity
Module (USIM) Interface
This chapter provides the features of the USIM.

16.1 Feature List—Electrical

• One Universal Subscriber Identity Module (USIM) interface
• The USIM module supports Class B (operating mode of 3V) and Class C (operating mode of 1.8V) of
Smartcard technology.
• All Contacts are in L State (ground) when the USIM module is in inactive mode.
• Contacts as follows:
– Contact C1: Supply Voltage to UICC, 3V or 1.8V
– Contact C2: RST: Active low reset
– Contact C3: CLK: Clock 1-5MHz, Duty Cycle between 40% to 60%
– Contact C5: Ground
– Contact C7: Data IO. A pull-up resistor should be used (recommended value of 20K) and a series resistor
of 47 to 100 Ω to reduce short circuit current when using low impedance drivers
– Contacts C4, C6, C8 are not used.

16.2 Feature List—Functional

• Supports the ISO/IEC 7816-3:1997(E) and EMV2000 (4.0) specifications
• Performs functions needed for complete smart card sessions, including:
– Card activation and deactivation
– Cold/warm reset
– Answer to Reset (ATR) response reception
– Data transfers to and from the card
• Extensive interrupt support system
• Adjustable clock rate and bit (baud) rate
• Configurable automatic byte repetition
• Handles commonly used communication protocols:
– T=0 for asynchronous half-duplex character transmission
– T=1 for asynchronous half-duplex block transmission
• Automatic convention detection
• Configurable timing functions:
– Smart card activation time
– Smart card reset time

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– Guard time
– Timeout timers
• Automatic operating voltage class selection
Figure 16-1 USIM Block

16.3 Smart Card Session Description

A Smart Card session consists of the following stages:
1. Smart Card Insertion
2. Activation of Contacts and Cold Reset Sequence
3. Answer to Reset (ATR) Sequence
4. Execution of Transaction
5. Deactivation of Contacts
6. Smart Card removal
7. Warm Reset

16.3.1 Smart Card Insertion

A Smart Card session starts with the insertion of the Smart Card. This event is signaled to the SCR_CORE using
the SCDETECT input. The active state of the SCDETECT input is defined using the SCDETECTACTIVE constant,
which is defined in the SCR parameters file. The SCDETECT input is additionally filtered using the
SCDETECTTIME constant from the SCR parameters file. If the SCDETECT input is in the active state during the
SCDETECTTIME, the Smart Card insertion is propagated higher to the SCR_CORE. The SCPRESENT bit is set
and also the SCINS interrupt is asserted (if enabled).

16.3.2 Automatic Operating Voltage Class Selection

There are three operating classes (1.8V - class C, 3V - class B and 5V - class A) defined in ISO/IEC 7816-3(2006)
specification. Only one of the output pins SCVCC18, SCVCC33 or SCVCC50 is active at a time. Before the
activation of contacts, operating classes have to be enabled via bits VCC18, VCC33 and VCC50 in CTRL2 register.

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In case that no operating class is enabled, the controller performs activation for all three voltage classes (1.8V, 3V
and 5V) in sequence.
When Smart Card Reader performs activation of contacts the lowest enabled voltage class is automatically applied
first. When the ATR sequence is received, the selected voltage class is correct. When the ATR sequence reception
fails, ATRFAIL interrupt is not activated, deactivation is performed and next higher enabled voltage class is applied.
If the ATR sequence reception fails and no other higher class is enabled or the highest Class A was already applied
the ATRFAIL interrupt is activated and the last applied voltage class remains active.
After the automatic voltage class selection is finished the selected class can be read from bits VCC18, VCC33 and
VCC50 in CTRL2 register. If the automatic voltage class selection fails, these bits remain untouched.
There is a delay applied between deactivation of contacts with lower voltage class and activation of contacts with
higher voltage class. This delay should be at least 10 ms. This delay is realized by running of N-bit timer until it is
full. Width of the timer is given by parameter CLASSDELAYWIDTH in SCR parameters file.

16.3.3 Activation of Contacts and Cold Reset Sequence

When the Smart Card is properly inserted and the ACT bit in CTRL2 register is asserted, the activation of contacts
can be started. The duration of each part of the activation is the time (Ta), which is equal to the ADEATIME register
value. If no Vpp is necessary, the activation and deactivation part of Vpp can be omitted by clearing the
AUTOADEAVPP bit in SCPADS register.
The Cold Reset sequence follows immediately after the activation. Time (Tc) is the duration of the Reset. It is
defined in the LOWRSTTIME register. The EMV specification recommends that this value should be between
40000 and 45000 card clock cycles. The activation of contacts and cold reset sequence is shown in Figure 6-1.

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16.3.4 Answer to Reset (ATR) Sequence

The Smart Card transmits the ATR sequence to inform the Smart Card Reader about subsequent data transfer
requirements.
The ATR response on SCIO should begin between 400 and 40000 clock cycles (Td) after the rising edge of the
SCRSTN signal. If the ATR response does not begin, the ATRFAIL interrupt will be activated. The maximum ATR
waiting time is limited by the ATRSTARTLIMIT register value. This is shown in Figure 16-2.
Figure 16-2 Activation, Cold Reset and ATR

Waiting
Activation Cold reset for ATR ATR response

SCVCC

SCVPPEN

SCVPPPP Pause State

Tc
SCRSTN

SCCLK
Td

Reception
ATR response
SCIO mode – Hi-Z

Ta Ta Ta

The first character of the ATR sequence is the TS character which defines the coding convention used by the card.
The TS information is decoded and stored as bits INVLEV and INVORD in the CTRL1 register. Therefore, storing
the TS character in the RX FIFO is not necessary. You can disable it by clearing the TS2FIFO bit in the CTRL1
register. The convention defined in the TS character is used for all transfers after the TS character reception. You
can modify the INVLEV and INVORD values after the ATR sequence reception, when needed.
After the ATR sequence is received, the superior system reads the ATR from the RX FIFO and programs the Smart
Card Reader according to extracted ATR values.

16.3.5 Execution of Transaction

All transfers between the Smart Card Reader and a Smart Card are under the control of the superior system. It
controls the number of characters sent to the Smart Card and it knows the number of characters expected to be
returned from the Smart Card.

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16.3.6 Deactivation of Contacts

After the smart card reader detects the removal of the smart card (SCREM interrupt) or the superior system
initiates deactivation by setting the DEACT bit in the CTRL2 register to '1,' the deactivation is performed
immediately as shown in Figure 16-3. The duration time (Ta), of each part of the deactivation sequence time is
defined in the ADEATIME register.
Figure 16-3 Deactivation Sequence

Deactivation
SCVCC

SCVPPEN

SCVPPPP

SCRSTN

SCCLK

SCIO

Ta Ta Ta Ta Ta

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16.3.7 Warm Reset

The Warm Reset sequence is initialized by setting the WRST bit in the CTRL2 register to '1.' According to
Figure 16-4, the Smart Card Reader drives the SCRSTN signal to '0' to perform the Warm Reset. After the
SCRSTN assertion, the Warm Reset sequence then continues the same way as the Cold Reset sequence.
Figure 16-4 Warm Reset and ATR

Warm reset Waiting for ATR ATR response

SCVCC

Tc
SCRSTN

SCCLK
Td

Reception mode – Hi-Z ATR response

SCIO

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17 Radio Parallel Digital Interface
(RPDIF)
This chapter describes the features, RPDIF variations, and RF-SPI functional muxing of RPDIF interface.

17.1 Features List

• Two Radio Parallel Digital Interfaces (RPDIF)
• Complies with JESD-207 standard.
• Supports Frequency Division Duplex (FDD) mode.
• Supports Time Division Duplex (TDD) mode.
• Interfaces with the AD936x and Maxim MAX259x devices.
• Supports up to 2 antennas, 20 MHz.
Two main modes of operations:
– JESD207 mode - Follows JEDEC Standard JESD207 on RBDP Interface, March 2007.
– ADI mode - Supports the following AD936x signaling types -
• Single Port TDD mode
• Single Port Full Duplex mode
• Dual Port TDD mode
• Dual Port FDD mode
• SPI Interface for ADI serial control is supported through the Transcede 2xxx SPI block.

17.2 RPDIF Control Plane Variations

• RPDIF control plane interface is an SPI interface which is similar to JESD207 control plane interface.
• RPDIF supports 16 bit control word mode of operation.
• RPDIF supports multi byte transactions.
• RPDIF to AD936x write and read command interpretation is opposite with respect to JESD207 standard.
Figure 17-1 SPI Control Word Format

MSB D14 D13 D12 D11 D10 D9:D0

W/Rb NB2 NB1 NB0 X X A<9:0>

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17.3 RPDIF Data Plane Variations

Figure 17-2 Interfacing with AD936x in Single Port Full Duplex Mode

RPDIF1_MCLK
RPDIF1_RX_FRAME
6 P0_D[0:5]
RF RFIC
Front T2xxx
End AD936x RPDIF1_FBCLK
RPDIF1_TX_FRAME
6 P0_D[6:11]

Figure 17-3 Interfacing with AD936x in Dual Port Full Duplex - CMOS Mode

RPDIF1_MCLK
RPDIF1_RX_FRAME
6 P0_D[0:5]
6 P0_D[6:11]
RF RFIC
Front T2xxx
End AD936x RPDIF1_FBCLK
RPDIF1_TX_FRAME
6 P1_D[0:5]
6 P1_D[6:11]

• RPDIF has two mandatory ports namely TX_FRAME and RX_FRAME which are used to indicate the valid
data in transmission and reception operation respectively.
• RPDIF11_TX_FRAME and RPDIF1_RX_FRAME signals can operate in two modes. Level mode and Pulse
mode.
• RPDIF has two data ports of 12 bit P0 and P1 which enable to operate both in SDR (Single Data Rate) mode
and DDR (Dual Data Rate) mode. Also allows differential signaling in a different mode.
• RPDIF supports two IO types:
– CMOS (single ended signaling)
– LVDS (Differential signaling)
• CMOS IOs support the following modes:
– Single port TDD Mode
– Single port Full Duplex Mode
– Dual port TDD Mode
– Dual bus Full Duplex Mode
• LVDS IOs support FDD and TDD using differential signals..

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Figure 17-4 Interfacing with AD936x in LVDS Mode

RPDIF1_MCLK_P
RPDIF1_MCLK_M

RPDIF1_RX_FRAME_P
RPDIF1_RX_FRAME_M

12 RPDIF1_RX_P[5:0], RPDIF1_RX_M[5:0]

RF AD936x T2xxx
Front RPDIF1_FBCLK_P
End RPDIF1_FBCLK_M

RPDIF1_TX_FRAME_P
RPDIF1_TX_FRAME_M

12 RPDIF1_TX_P[5:0], RPDIF1_TX_M[5:0]

Figure 17-5 Data Path 2T2R RX LVDS

RPDIF1_MCLK

RPDIF1_RX
2T2R Timing Shown
_FRAME

P1 D[5:0] Q I Q I Q I Q I Q I Q

Figure 17-6 Data Path 2T2R TX LVDS

RPDIF1_
FBCLK

RPDIF1_TX
2T2R Timing Shown
_FRAME

P0 D[5:0] Q I Q I Q I Q I Q I Q

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17.4 RPDIF Functional Muxing

The Transcede 2xxx device supports two radio SPI interfaces. Each RF_SPI interface is muxed with one of the
generic SPI interfaces. Figure 17-7 illustrates the function muxing of RPDIF SPI interfaces:
• RF-SPI0 is muxed with GENERIC-SPI1;
• RF-SPI1 is muxed with GENERIC-SPI0;

Table 17-1 RPDIF Functional Muxing Table

Func Mux options based on gpio [0x060] Misc Pin Select Register

Signal Name Option 1 (default) Option 2 Option 3

gpio_set_2=0 gpio_set_2=1 misc_pin_sel[9]=1

Muxing of Generic SPI interface with JESD SPI interface

SPI_S1_SCLK SPI_S1_SCLK JESD0_SCLK
SPI_S1_SS1_N SPI_S1_SS1_N GPIO_19 JESD0_CPCSB
SPI_S1_TXD SPI_S1_TXD GPIO_30 JESD0_CMOSI
SPI_S1_RXD SPI_S1_RXD GPIO_31 JESD0_CMISO
gpio_set_2=0 gpio_set_2=1 misc_pin_sel[10]=1
SPI0_SCLK SPI0_SCLK JESD1_SCLK
SPI0_SS2_N SPI0_SS2_N JESD1_CPCSB
SPI0_TXD SPI0_TXD JESD1_CMOSI
SPI0_RXD SPI0_RXD JESD1_CMISO

Figure 17-7 Functional Muxing of RPDIF SPI Interfaces

APB Bus SW Control #1

RPDIF 1 RFIC #1
4
RF-SPI 1 4
MUX

4
SPI 0 SPI0_SS0/1/3 SPI Devices
3
SW Control #2

RPDIF 0
4 RFIC #2
MUX

RF-SPI 0 4
4
SPI 1 SPI1_SS1 SPI Device

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17.5 RPDIF Timing Parameters

• RPDIF CMOS Interface
• RPFIF LVDS Interface

17.5.1 RPDIF CMOS Interface

Table 17-2 lists the RPDIF CMOS parameters. Table 17-8 shows the RPDIF CMOS timing.

Table 17-2 RPDIF CMOS Parameters

Parameter Min Max Description

tCP 16.276 ns RPDIF_MCLK and RPDIF_FBCLK period

tMP 45% of tCP 55% of tCP RPDIF_MCLK and RPDIF_FBCLK high or low minimum pulse width
tSRD 2.3 ns RX data setup w.r.t. RPDIF_MCLK
tHRD 0 ns RX data hold w.r.t. RPDIF_MCLK
tSRC 2.3 ns RX control setup w.r.t. RPDIF_MCLK
tHRC 0 ns RX control hold w.r.t. RPDIF_MCLK
tDDTD 0 ns 5.7 ns TX data delay w.r.t. RPDIF_FBCLK (with DLL calibrated to 4 ns)
tDDTC 0 ns 5.7 ns TX control delay w.r.t. RPDIF_FBCLK (with DLL calibrated to 4 ns)
tDDTXNRX2ENA 8.138 ns Delay of RPDIF_ENABLE w.r.t. RPDIF_TXNRX

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Figure 17-8 RPDIF CMOS Timing

tSRD/tSRC

tHRD/tHRC

RPDIF_MCLK
tDDTD/tDDTC

RPDIF_FBCLK

RPDIF_RX_FRAME

RPDIF_DIQ0/1 TI TQ
TI TQ RI RQ RI RQ
[11:0]

RPDIF_TX_FRAME

RPDIF_ENABLE

tDDTXNRX2ENA tDDTXNRX2ENA

RPDIF_TXNRX

17.5.2 RPFIF LVDS Interface

Table 17-3 lists the RPDIF LVDS parameters. Figure 17-9 shows the RPDIF LVDS timing.

Table 17-3 RPDIF LVDS Parameters

Parameter Min Max Description

tCP 4.069 ns RPDIF_MCLK and RPDIF_FBCLK period

tMP 45% of tCP 55% of tCP RPDIF_MCLK and RPDIF_FBCLK high or low minimum pulse width
tSRD 0.75 ns RX data setup w.r.t. RPDIF_MCLK
tHRD 0.25 ns RX data hold w.r.t. RPDIF_MCLK
tSRC 0.75 ns RX control setup w.r.t. RPDIF_MCLK
tHRC 0.25 ns RX control hold w.r.t. RPDIF_MCLK
tDDTD 0 ns 0.9 ns TX data delay w.r.t. RPDIF_FBCLK (with DLL calibrated to 1 ns)
tDDTC 0 ns 0.9 ns TX control delay w.r.t. RPDIF_FBCLK (with DLL calibrated to 1 ns)
tDDTXNRX2ENA 2.0345 ns Delay of RPDIF_ENABLE w.r.t. RPDIF_TXNRX

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Figure 17-9 RPDIF LVDS Timing

tCP tMP

RPDIF_MCLK_P

RPDIF_MCLK_M

RX_FRAME_P

RX_FRAME_M

tSRD/tSRC
RPDIF_RX_P/M IL QL IM IL QL
IM QM QM
[5:0]

tHRD/tHRC

tCP tMP
RPDIF_FBCLK_P

RPDIF_FBCLK_M

tDDTC
RPDIF_TX_FRAME_P

RPDIF_TX_FRAME_M

tDDTD
RPDIF_TX_P/M IL QL IM IL QL
IM QM QM
[5:0]

RPDIF_ENABLE

tDDTXNRX2ENA tDDTXNRX2ENA
RPDIF_TXNRX

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18 Joint Test Action Group (JTAG)
Interface
This chapter provides JTAG features and implementation details.

18.1 Feature List

• Two Joint Test Action Group (JTAG) interfaces
• TAP generated with Synopsys BSD compiler with IEEE 1149.6 - 2003 option is compatible to 1149.1
• This TAP supports additional EXTEST instructions required for 1149.6 EXTEST, EXTEST_PULSE, and
EXTEST_TRAIN

18.2 Implementation Details

The Transcede 2xxx provides two JTAG ports.
• One is dedicated for ARM debug
• The other functions for Ceva, SerDes, or DDR debug based on the JTAG mode selected. C_JTAG_MODE is
the boot control output provided by Bootstrap, as shown in Table 2-2, Bootstraps Signals, on page 31.

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19 ARM Subsystem (with Dual-ARM
Cores)
This chapter describes the features and implementation details of the ARM Cortex A9.
The Transcede 2xxx features one dual-ARM subsystem.

19.1 A9 Feature List

• Dual Cortex A9 CPU with Snoop Control Unit (SCU)
• Core clock runs at 1 GHz
• 32 KB data and instruction L1 caches
• Translation Look-aside Buffer (TLB) size: 128
• Neon is supported
• Pre-Load Engine (PLE) is not supported
• Two 64bit AXI ports
• Generic Interrupt Controller (GIC) is included in SCU with support for 128 IRQS
• Timer is included in SCU
• ACP port is supported

19.2 L2 Feature List

• 8-way 256KB L2 cache
• 2 AXI 64bit buses with CPU
• Core clock is 1 GHz
• Address Filtering option is enabled – when enabled port 1 is used to access specific address region and port 0
is for rest; when disabled, if address is DDR window then port 1 is used, else port 0.
• Parity is supported
• Direct DDR access from AXI Master Port1
• ECC is not supported.

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19.3 Implementation Details

• The RWM parameter of the memory blocks in ARM Top is configured in “SYS_CFG_0 Register
(0xF4C0_0140)” in CFG_SYS.
• Coretex-A9 MPCore RTL code is from revision r3p0, PL310 L2 Cache Controller RTL code is from revision
r2p0, and CoreSight RTL code is from revision r1p0.
• AXI interface between L2 cache module and SYS Bus Matrix is asynchronous.
• PERIPH_BASE = 0xFFFF_0000 – Cortex-A9 MPCore internal private peripheral base address

Table 19-1 Cortex-A9 MPCore Private Memory Map

Address Offset from PERIPH_BASE Description
0x0000-0x00FC SCU registers
0x0100-0x01FF C-A9CE Interrupt Interface
0x0600-0x06FF Private Peripherals – Timers & Watchdog Units
0x1000-0x1FFF GIC

• REGFILE_BASE = 0xFFF1_000 – PL310 L2 cache register file base address

• DBG_ROM_ADDR = 0xF4E0_0000 – Top-level ROM table base address (ARM CORESIGHT / Debug APB
base address) in system memory map
• The ARM CORESIGHT / Debug APB bus address upper [31:21] bits are masked to zero before sending to
ARM subsystem.
Table 19-2 lists the CoreSight interface muxing information.

Table 19-2 CoreSight Interface Muxing: 16-bit Trace Port

Bootstrap CoreSight Select

Signal Name Option 1 (default) Option 2

EXP_A9 (B-Strap) = 0 EXP_A9 (B-Strap) = 1

RPDIF0_DIQ0[11:0] RPDIF0_DIQ0[11:0] A9_TRACE_D[11:0]
RPDIF0_DIQ1[3:0] RPDIF0_DIQ1[3:0] A9_TRACE_D[15:12]
RPDIF0_FBCLK RPDIF0_FBCLK A9_TRACE_CLK

NOTE: CoreSight Interface is 2.5V but it is 3.3V tolerant.

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Figure 19-1 ARM CA9 with CoreSight Debugging System

Sytem
Timestamp
Counter
Cross Trigger Matrix CTM interface

Timestamp Distribution

CTI
L2
CORTEXA9 INTEGRATION
Cross Trigger Matrix F ETB

CTI

ITM
CORTEX
A9MP
SCU

PTM Replicator
CortexͲA9

ROM
Table

F TPIU
Debug APB

Debug APB

DAP ROM Table 16Ͳbit Trace Port

PC based SWD/JTAG
Debug Tool External pin interfaces
JTAG/SWD Trace Port
Emulator Analyzer

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Table 19-3 Address Map of CSDK Components

Component System Address Debug Address
Dap ROM Table 0xF4E0_0000 0x0000_0000
ETB 0xF4E0_1000 0x0000_1000
ETB Memory Software Relocatable Software Relocatable
CTI 0xF4E0_2000 0x0000_2000
TPIU 0xF4E0_3000 0x0000_3000
Funnel 0xF4E0_4000 0x0000_4000
ITM 0xF4E0_5000 0x0000_5000
SWO 0xF4E0_6000 0x0000_6000
CA9 internal ROM Table 0xF4E2_0000 0x0002_0000
CA9 DBG_Reg 0 0xF4E3_0000 0x0003_0000
CA9 PMU_Reg 0 0xF4E3_1000 0x0003_1000
CA9 DBG_Reg 1 0xF4E3_2000 0x0003_2000
CA9 PMU_Reg 1 0xF4E3_3000 0x0003_3000
CA9 CTI_Reg 0 0xF4E3_8000 0x0003_8000
CA9 CTI_Reg 1 0xF4E3_9000 0x0003_9000
CA9 PTM_Reg 0 0xF4E3_C000 0x0003_C000
CA9 PTM_Reg 1 0xF4E3_D000 0x0003_D000

19.4 256KB System Internal RAM (IRAM)

19.4.1 Feature List

• 256 Kbytes
• One 64-bit AXI interface
• Supports access sizes 8, 16, 32, or 64 bit
• MBIST is included
• Built-In Self Repair (BISR) support is included
• Access base address can be re-mapped to 0x0000_0000
• Allows simultaneous Read Write capability

19.4.2 Implementation Details

• The assertion of “Map_iram_0” bit of BUS_CFG register in CFG_SYS (bit [25] of 0xF4C0_8000) will mirror
map the base address of IRAM to 0x0000_0000, and all the accesses to 0x0000_0000 – 0x0001_7FFF will be
directed to IRAM as long as this memory space is not assigned to DDR3 controllers.
• The RWM parameter of the memory blocks in IRAM is configured in “SYS_CFG Register (0xF4C0_0130)”.

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Figure 19-2 shows the memory architecture of IRAM. The memory size of IRAM is specified as 256KB.
Figure 19-2 IRAM Architecture

RD/WR LEFT BANK

ARBITER Ͳ
(odd word address)
LEFT
128K

AXI Ͳ
DW_axi_gs –
RD/WR
Read/Write
(64 bit)

RD/WR RIGHT BANK

ARBITERͲ
(even word address)
RIGHT
128K

Figure 19-3 shows the IRAM memory bank structure.

Figure 19-3 IRAM Memory Bank Structure

64 bit input data

odd address bank even address bank

(128K) (128K)

word1 Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0 Byte7 Byte6 Byte5 Byte4 Byte3 Byte2 Byte1 Byte0
word0
word3 word2
. 6Kx16 6Kx16 6Kx16 6Kx16 6Kx16 6Kx16 6Kx16 6Kx16 .
. .
pm_mem pm_mem_ pm_mem_ pm_mem_ pm_mem pm_mem pm_mem pm_mem
_r_blk3 r_blk2 r_blk1 r_blk0 _l_blk3 _l_blk2 _l_blk1 _l_blk0

address bit 3
Mux

64 bit output data

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19.5 TrustZone Support

The Transcede 2xxx device supports ARM’s TrustZone technology on its AXI buses. This allows address ranges to
be configured as secure or non-secure. Only secure masters may access secure address ranges, a non-secure
master trying to access a secure range will receive a bus error. Both secure and non-secure masters can access
non-secure address ranges. The secure/non-secure check is performed in hardware using a secure signal on the
AXI bus.
The Transcede 2xxx device can be configured to place various memory areas and functional blocks in secure
mode, meaning that if acting as a master it is a secure master, and if acting as a slave it can only be accessed by
secure masters.
The paragraphs below describe what can be configured for secure mode, any block not specifically listed below
can only be in non-secure mode.
• The ARM Cortex A9 cores natively support TrustZone, running as two virtual processors, one secure and one
non-secure. The secure boot process ensures that only trusted code can run, and this code will configure the
Cortex A9’s for correct secure operation.
• The SPAcc security accelerate also natively supports TrustZone. When an operation is set up via a secure
access, this operation will run in secure mode. When an operation is set up via a non-secure access, the
operation will run in non-secure mode.
The following list of functional blocks can be placed in either secure or non-secure mode, based on a set of
configuration registers that are themselves always in secure mode:
• USIM (slave)
• I2C (slave)
• SPI (slave)
• eFuse block (slave)
• UART0 (slave)
• SASPA
• USB (master)
• IPSec accelerator (master)
• MDMA SYS0 (master)

NOTE: Setting the PCIe or USB interfaces to secure mode can allow external masters to access
internal secure areas. This will most likely break 3GPP TrE compliance.

Specific address ranges that map to DDR, IRAM or the expansion bus may be set to secure mode. Both the IRAM
and expansion bus have corresponding registers to set the low and high address of the secure mode area. Only
one secure window can be set up for each. The DDR controller has four separately configurable ports, each with up
to four secure areas that can be set up.
The Transcede 2xxx also provides a secure timer, which is always in secure mode.

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20 Ceva-XC323 DSP
This chapter introduces the features of the Ceva processors.

20.1 Ceva-XC323 DSP

The Transcede 2xxx device features two Ceva-XC323 processors.
• 96 Kbyte of Program memory and 256 Kbyte of Data memory.
• Each Ceva can initiate stop clock operation to save power.
• Status of many semaphore registers can be read from local APB bus.
• Mail box write has interrupt out to Ceva Group interrupt controller and can be used to interrupt the receiving
Ceva. The mail box interrupt and acknowledge handshake in lock step, one pulse one request type.
• Mail box read has 8 indicators out that can be read from Ceva Group interrupt controller register or can be
connected to source Ceva GPIN pins. The indicators can be cleared by writing to the register in Ceva Group
interrupt controller.
• The int0, int1, int2, nmi, and vint are input from Ceva Group interrupt controller. Each interrupt has an
acknowledge output signal that handshake with it in lock step, one pulse one request type.
• Slave memory access snoop interrupt is connected to Ceva Group interrupt controller and can be used to
interrupt the receiving Ceva. The snoop interrupt and its acknowledge handshake in lock step, one pulse one
request type.
• Violation interrupt (from cevaxc_gvi_r) is connected to Ceva Group interrupt controller and can be used to
interrupt the receiving Ceva. The violation interrupt and its acknowledge handshake in lock step, one pulse one
request type.
• Two OCEM break point inputs are connected to Ceva Group interrupt controller. Each break point input has an
acknowledge output signal that handshake with it in lock step, one pulse one request type.

20.2 768KB CEVA Internal RAM (CRAM)

The Transcede 2xxx device features one dual-port CRAM interface.

20.2.1 Feature List

• One dual-port 768 Kbyte module.
• Two 128-bit AXI interfaces.
• Each 128-bit AXI bus can do the read and write transfer simultaneously into the CRAM.
• Supports access sizes 8, 16, 32, 64 or 128 bit.
• ECC is included (128-bit write accesses, all read accesses)
• Memory Built-In Self Test (MBIST) is included
• Built-In Self Repair (BISR) support is included

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20.2.2 Implementation Details

Figure 20-1 shows the memory architecture of CRAM. Figure 20-2 shows the memory bank structure of CRAM.
The memory is partitioned into two banks - Left and right. Data is organized in the memory banks in an interleaved
fashion, so all odd addresses will hit the left bank while the even addresses will hit the right bank. Simultaneous
memory accessed by the two ports is possible if the accesses alternate between odd and even words. Conflict
access to the same bank is resolved using simple arbiters one per bank.
Figure 20-1 CRAM Architecture

RD/WR RD/WR LEFT BANK

AXI - X ARBITER -
DW_axi_gs - X (odd word address)
(128bit) LEFT
384K

RD/WR RD/WR RIGHT BANK

AXI - Y ARBITER-
DW_axi_gs - Y (even word address)
(128bit) RIGHT
384K

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Figure 20-2 CRAM Memory Bank Structure

128 bit input data

odd address bank even address bank

(384 K) (384 K)

word1 Byte15 Byte14 Byte3 Byte2 Byte1 Byte0 Byte15 Byte14 Byte3 Byte2 Byte1 Byte0 word0
word3 word2

24Kx16 ... 24Kx16 24Kx16 24Kx16 ... 24Kx16 24Kx16

pm_mem pm_mem pm_mem pm_mem pm_mem pm_mem

_r_blk7 _r_blk1 _r_blk0 _l_blk7 _l_blk1 _l_blk0

address bit 4 Mux

128 bit output data

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21 Mindspeed Advanced Processor
(MAP) Array / FFT Accelerator
This chapter describes the Mindspeed Advanced Processor (MAP) Array or FFT Accelerator implemented in the
Transcede 2xxx.

21.1 Feature List

• One MAP array, or FFT accelerator.
• The MAP Array or FFT Accelerator has four processing units, and each one is a complete Mindspeed
Advanced Processor (MAP).
• The array has a 128-bit AXI bus for data transfer through MAP Direct Memory Access (DMA) controller.
• Accelerator for 4G Wireless (LTE): FFT (128 to 4 K points), IFFT (128 to 4 K points), and IDFT.
• Accelerator for WCDMA: RAKE receiver function.
• Accelerator for video application: DCT and IDCT.
• Accelerator for voice over IP: Echo canceller and high speed filtering (FIR, IIR, etc)

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21.2 MAP Processor Array Block Diagram

Figure 21-1 illustrates the block diagram of the MAP Processor Array in the Transcede 2xxx device.
Figure 21-1 MAP Processor Array Block Diagram

Target Requests and Acknowledges APB bus

MAP
FP MAP
FP MAP
FP MAP
FP APB
APBreg
reg
0 1 2 3

Inter MAP bus

FIFO
FIFO FIFO
FIFO Master
MasterControl
Control

MAPDMA0 FHEAD_EXP Target Requests

FTDMA0 FHEAD_EXP and Acknowledges

AXI Bus
• There is only one APB interface module that connects to the two MAPs, and the internal APB bus can be used
for high speed data transfer (Inter MAP transfer) between MAPs.
• MAPDMA can be configured as multi-channel DMA by enabling the FHEAD_EXP module. The combined
group allows independent descriptor chain for each MAP.
• Each MAP has comprehensive debug support. In debug mode, it can be stopped with specified instruction
pointer and step the execution. Also the registers can be read and write in debug mode through APB access.

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21.3 MAP Architecture

Figure 21-2 illustrates the block diagram of the MAP.
Figure 21-2 MAP Architecture

Read bus Write bus

64 bits 64 bits
IO

Mbank_0 32
2Kx(2x16) 32
Mbank_1
2Kx(2x16)
Mbank_2
2Kx(2x16) Data Path
Mbank_3
2Kx(2x16)
Mbank_4 48
2Kx(2x24) 48
4xMAC
Mbank_5
2Kx(2x24) 16 x 24 - bit
Mbank_6
2Kx(2x24)
Mbank_7
2Kx(2x24)

Program Mem
APB
Control Unit 512x160
Address Unit
8 Interrupt
Bank_sw I/O_Cntrl Event_reg Debug_cnt
8 8 16 24

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Figure 21-3 illustrates the memory bank structure of the MAP.

Figure 21-3 Memory Bank Structure of MAP

000-7FF Segment_15
Bank 7
000-7FF Segment_14
000-7FF Segment_13
Bank 6
000-7FF Segment_12
000-7FF Segment_11
Bank 5
000-7FF Segment_10
000-7FF Segment_9
Bank 4
000-7FF Segment_8
000-7FF Segment_7
Bank 3
000-7FF Segment_6
000-7FF Segment_5
Bank 2
000-7FF Segment_4
000-7FF Segment_3
Bank 1
000-7FF Segment_2
000-7FF Segment_1
Bank 0
000-7FF Segment_0

MAP data memory is divided into 16 memory segments and grouped into 8 memory banks, with each two
segments form one memory bank. The word length of segment 0 to 7 is 16 bit and the segment 8 to 15 is 24 bit.
The depth of memory segment is 2K words, and each memory segment has its own address space.

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21.4 MAP Processor Array APB Bus Memory Mapping

Figure 21-4 illustrates the APB bus memory mapping for each block.
Figure 21-4 APB Bus Address Mapping For Each Block

2 KB Write Broadcast
offset1=0xF800h
2 KB Master Control
offset1=0xF000h

~ ... ~
~ ~

offset1=0xE800h
1 KB FHEAD_EXP 0
offset1=0xE400h
1 KB MAPDMA 0
offset1=0xE000h

~ ... ~
~ ~

offset1=0x2000h
2 KB MAP3
offset1=0x1800h
2 KB MAP2
offset1=0x1000h
2 KB MAP1
offset1=0x0800h
2 KB MAP0
offset1=0x0000h
(Base Address)

Every block in the MAP Processor Array is assigned with 2 Kbyte of APB memory space. This includes four MAP
blocks and the Master Control block. The address of APB bus register inside of each block will have:
Block Base Address = Base Address + offset 1
The Base Address of MAP Processor Array APB registers is 0xF3D4_0000.
Besides these blocks of address space assigned to each module, there is a Write Broadcast block at offset1 =
0xF800h that allows a single APB bus write to any address in this block to be translated into simultaneous
broadcast APB write to any specified group of MAP blocks. In order words, a write to Write Broadcast block APB
memory space will assert the "p_sel" of every selected MAP block, and thus enable simultaneous write to more
than one MAP blocks.

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21.5 DMA Data Transfer

Master Control module controls the DMA data transfer between MAPDMA FIFO and each MAP. In each MAP,
FFT_IO module handshakes with Master Control to write or read the data to and from the internal 16 memory
segments.
FFT_IO uses TR_CONTROL input signals to determine the start address of the start memory segment to transfer
the data and how the data is formatted and how wide the bus to transfer. Also, when the transfer is complete, it
gives the option to interrupt the FFT_CU.
The TR_CONTROL signals are extracted either from the MAPDMA frame descriptor or from MC APB registers.
• For Target transfers and Pool Inbound transfer, the TR_CONTROL signals are extracted from MAPDMA frame
descriptor.
• For Pool Outbound transfer, the TR_CONTROL signals are from MC APB registers.

21.6 MAP Direct Memory Access (DMA) Controller

This section describes two functions: Direct Memory Access Controller (DMA) and MAP Master Controller. They
may operate at different clock rates. The DMA follows a data structure to transfer data from/to memory to/from
FIFOs. The MAP Master Controller (MC) transfers data from/to MAP to/from FIFOs.

21.6.1 Feature List

• One DMA channel to move data from/to multiple memory locations to/from MAPs.
• Independent Tx and Rx Frame and Buffer descriptors provide information about the packet to be transferred.
• Frame/ Buffer Descriptors can support linked list-transfer operations.
• For MAP-Pool mode, the DMA can support both Scatter and Gather modes.
• For MAP-Target mode, the DMA can only support Gather mode.

NOTE: Data transferred from memory to MAP must be a multiple of 8 bytes. When programming
Buffer descriptors, Bpointer[2:0] and Bcontrol[2:0] must be 0 (8-byte boundary.)
Data transferred from MAP to memory must be a multiple of 8 bytes. When programming
Buffer descriptors, Bpointer[3:0] must be 0 (16-byte boundary) and Bcontrol[2:0] must be
0 (8-byte boundary.) Scatter mode can still be used but buffers need to be at 16-byte
boundary. Historically, Scatter mode was not used.

21.6.2 MAP DMA and FFT_MC Block Diagram

The MAP DMA is to transfer data between memory and MAPs with a FIFO in between. A Tx (inbound) path is
defined as reads from memory, writes to Tx FIFO, reads from Tx FIFO, and writes to MAP. An Rx (outbound) path
is defined as reads from MAP, writes to Rx FIFO, reads from Rx FIFO, and writes to memory. The DMA controller
implements a data structure that has Frame and Buffer Descriptors which describe controls and data buffer
locations in memory. This structure moves data between the AXI bus and the FIFOs. Monitoring the FIFOs' status,
the MC moves data between MAPs and FIFOs.

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Figure 21-5 shows the MAP DMA and FFT_MC block diagram.
Figure 21-5 MAP DMA and FFT_MC Block Diagram

5 Sets of Controls
MAP Data In[63:0] MAP Data Out[4:0][63:0]
Valid/Ready Handshake

5:1
64 MAP Master Control APB
Mux
64

Tx FIFO Rx FIFO
Clock Domain Crossing
64x64 512x64

APB
DMA
IRQs
Linked List-Transfer
AXI

21.6.3 MAP Master Controller (MC)

Monitoring the FIFOs' status, the MC moves data between MAPs and FIFOs.
• Through APB configuration registers, the MC knows the data size each MAP needs, maximum 8K bytes. All
MAPs need that same amount of data. The DMA Frame descriptor is not used by software to tell MC that size.
• Through APB configuration registers, the MC can reset any MAP.
• Eight-bit status will be conveyed from MAP to software through the Frame Descriptors.

21.6.4 DMA Data Structures

The DMA controller exchanges control information and data with the system through three data structures:
• Frame descriptors
• Buffer descriptors
• Data buffers

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Figure 21-6 shows how these data structures are related.

Figure 21-6 DMA Data Structure

Queue
Access Frame Descriptors

Head Next Next Next

FControl FControl FControl

FControl FControl FControl

FControl FControl FControl

Buffer BPointer BPointer BPointer

Descriptors
BControl BControl BControl

BPointer BPointer BPointer

BControl BControl BControl

BPointer BPointer

BControl BControl

Data Buffers

21.6.5 Frame and Buffer Descriptors

Frame descriptors must be aligned on 16-byte boundaries. Buffer descriptors must follow Frame descriptors.

Table 21-1 Inbound (Tx) Frame and Buffer Descriptors Programming

Bit Name Description
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used
Frame Word1 = FControl0. Offset: x4
31 – 26 TR_CTRL Tr_Control bits [45:40].
bit [31:26] = tr_id.
25 - 17 Not used
16 Reserved
15 - 12 IRQTID Reserved for TID
11 - 4 IRQTID Task Done ID number when IRQTDONE is active.

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Table 21-1 Inbound (Tx) Frame and Buffer Descriptors Programming (Continued)
Bit Name Description
3 IRQTDONE IRQ Task Done Enable. Set an interrupt when acknowledging to an external DMAREQ.
2 BRESP_N 1: No waiting for AXI Bresp. Do not care if any AXI write successfully gets to the destination.
1 Reserved. Must be 0
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Frame Word2 = FControl1. Offset: x8
31 – 5 TR_CTRL Tr_Control bits [26:0].
bit [6:5] = load_type,
bit [7] = load_cont,
bit [15:8] = start_bank,
bit [16] = start_seg,
bit [18:17] = bus_size,
bit [19] = data_type,
bit [22:20] = tr_interrupt,
bit [31:23] = start_addr[8:0],
4 WSTAY Stay working at the current MAP (inbound only)
3 XPAN 3G Expander: Two’s complement a data bit to a byte
Note: This bit is for Transcede 2120/2150/2200.
2–0 FPID MAP number to be served. FPID=7 means to select a MAP from the FPenable register (Pool
process.) For Target transfer:
FPID = 0 -> MAP0
FPID = 1 -> MAP1
FPID = 2 -> MAP2
FPID = 3 -> MAP3
Frame Word3 = FControl2. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.
30 – 29 Not used
28 – 16 TR_CTRL Tr_Control bits [39:27].
bit [17:16] = start_addr[10:9],
bit [28:18] = seg_count,
15 – 8 D2MBdesc Must be zero.
7– 0 M2DBdesc Mem2Dma Number of Bpointer/BControl pairs. Buffer Words always start at offset x10.
Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer. Must be a multiple of 8 bytes.
Buffer Word 1 = BControl. Offset: x14
31 – 24 Not used
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes. Must be a multiple of 8 bytes.
Buffer Word 2 = BPointer. Offset: x18
Buffer Word 3 = BControl. Offset: x1C

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Table 21-1 Inbound (Tx) Frame and Buffer Descriptors Programming (Continued)
Bit Name Description
Buffer Word 4 = BPointer. Offset: x20
Buffer Word 5 = BControl. Offset: x24
Etc..

Table 21-2 Outbound (Rx) Frame and Buffer Descriptors Programming

Bit Name Description
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used
Frame Word1 = FControl0. Offset: x4
31 – 17 Not used
16 Reserved. Must be 0.
15 - 12 IRQTID Reserved for TID
11 - 4 IRQTID Task Done ID number when IRQTDONE is active
3 IRQTDONE IRQ Task Done Enable. Set an interrupt when acknowledging to an external DMAREQ.
2 BRESP_N No waiting for AXI Bresp. Do not care if any AXI write successfully gets to the destination.
1 Reserved. Must be 0
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Framexuandinh Word2 = FControl1. Offset: x8
31 – 5 TR_CTRL Tr_Control bits [26:0].
bit [6:5] = load_type,
bit [7] = load_cont,
bit [15:8] = start_bank,
bit [16] = start_seg,
bit [18:17] = bus_size,
bit [19] = data_type,
bit [22:20] = tr_interrupt,
bit [31:23] = start_addr[8:0],
4 INTER FP Inter MAP DMA transfer
3 Not used
2–0 FPID MAP number to be served. FPID >= 5 is an illegal setting. For pool transfer, this field is not
used, for target transfer:
FPID = 0 -> MAP0
FPID = 1 -> MAP1
FPID = 2 -> MAP2
FPID = 3 -> MAP3
Frame Word3 = FControl2. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.

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Table 21-2 Outbound (Rx) Frame and Buffer Descriptors Programming (Continued)
Bit Name Description
30 – 29 Not used
28 – 16 TR_CTRL Tr_control bits [39:27].
bit [17:16] = start_addr[10:9],
bit [28:18] = seg_count.
15 – 8 D2MBdesc Dma2Mem (from I/O to memory) Number of Bpointer/BControl pairs. Buffer Words always
start at offset x10
7– 0 M2DBdesc Must be zero.
Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer. Must be a multiple of 16 bytes.
Buffer Word 1 = BControl. Offset: x14
31 – 24 Not used
23 – 0 BLEN Number of bytes to be transferred. Zero means none. Maximum 16Meg – 1 bytes. Since the FFT
interface data bus is 64 bits wide, BLEN must be a multiple of 8. If scattering, BLEN must be a
multiple of 16 unless it is for the last buffer.
Buffer Word 2 = BPointer. Offset: x18
Buffer Word 3 = BControl. Offset: x1C
Buffer Word 4 = BPointer. Offset: x20
Buffer Word 5 = BControl. Offset: x24
Etc..

Table 21-3 Inbound Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus0. Offset: x8
31 – 0 No change.
Frame Word3 = FStatus1. Offset: xC
31 FDone = 1 if Register DONOSTA =0 and when this frame is completed. Else no change.
30 – 0 No change.

Table 21-4 Outbound Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus0. Offset: x8
31 – 10 Undetermined if Register IOSTATUS = 1. Else no change.
9–0 Status MAP status if Register DONOSTA = 0. Else no change to these bits.
Frame Word3 = FStatus1. Offset: xC
31 FDone = 1 if Register DONOSTA = 0 and when this frame is completed. Else no change.
30 – 0 Undetermined if Register IOSTATUS = 1. Else no change.

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22 Forward Error Correction (FEC)
Hardware Accelerator
This chapter describes the Forward Error Correction block implemented in the Transcede 2xxx.

22.1 Feature List

The FEC block has two accelerators:
• One for Up Link (UL) for 3G and 4G
• One for Down Link (DL) for 3G and 4G

NOTE: FEC accelerator for 3G is for Transcede 2120, Transcede 2150, and Transcede 2200.

The FEC block has the following features:

• 4G LTE DL
– Compute and append CRC to each transport/code blocks
– Transport block concatenation and code block segmentation
– Channel coding: CC Encoder, CTC Encoder
– Rate matching, Bit scrambling
• 4G LTE UL
– Channel-Deinterleaver
– Descrambling
– Deconcatenate / Demultiplex
– De – Rate matching
– HARQ Soft-Combining
– Channel de-coding: CC Decoder, CTC Decoder
– CRC check
• 3G WCDMA DL
– Compute and append CRC to each transport block
– Transport block concatenation and code block segmentation
– Channel coding: CC Encoder, CTC Encoder
– Rate matching
– 1st DTX insertion
– 1st interleaving
– Radio frame segmentation
– Transport channel (TrCH) multiplexing
– 2nd DTX insertion
– Physical Channel segmentation

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– 2nd interleaving
– Physical channel mapping
– HS-DSCH bit scrambling
– HS-DSCH HARQ functionality
– HS-DSCH constellation re-arrangement
– HS-SCCH coding, types 1,2,3
– E-AGCH coding
• 3G WCDMA UL
– 2nd de-interleaving
– Physical channel concatenation
– Transport channel de-multiplexing
– Rate de-matching
– Radio frame concatenation
– 1st de-interleaving
– Channel decoding: CC decoder, CTC decoder
– CRC check
– HARQ combining
– Control channel Reed-Muller decoding

NOTE: 3G WCDMA DL and 3G WCDMA UL features are for Transcede 2120, Transcede 2150,
and Transcede 2200.

22.2 Block Diagram

Figure 22-1 shows FEC downlink block diagram and Figure 22-2 shows FEC uplink block diagram for Transcede
2120, Transcede 2150, and Transcede 2200.
Figure 22-1 FEC Downlink Block Diagram

M1

CC, CTC LTE Circular

Rx CRC A CRC B Rate Scramb
Econder S2P Buffer A
Downlink insertio insertio P2S Matchin ler
n n TC7K g
/ DMA Filler
Insertion Circular
CTC Buffer B
3G Tx
Econder Uplink /
TC7K DMA
64 bits LTE, 3G
Block
Econder
3G
CC, 3G 3G Rate 3G second Scramb
Econder Match interleaver ler
64 bits

Status and Control

APB Interface

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Figure 22-2 FEC Uplink Block Diagram

CRC
checker

HARQ Write
Back Bypass

M5
M4
HARQ BYP CC,CTC LTE
LTE- CTC/CC Tx
sub block CC Tail Uplink
Rx
48bits Soft de- Viterbi Biting / DMA
Uplink M1 M3
Descra Combine nterleaver Decoder Buffer
/ DMA
mbler
LTE Channel
LTE de-
de-
Interleave
rate match HARQ CC,CTC 3G CTC, 3G and 4G 64 bits
64 bits De-mux
Memory sub block Decoder
De-concat de-
3G- CTC/CC
nterleaver
3G 2nd de-
3G de-
interleave
Rate
De-mux
Match Block
De-concat
Decoder

Status and Control

APB Interface

22.3 Software Interface

The FEC Controller exchanges control information and data with the system software via three data structures:
• Frame Descriptors: Traditional DMA descriptors to allow the software to interface with the FEC Controller using
the DMA. The Frame Descriptors specify the Frame Data and Control Words required by the FEC Controller.
• Frame Control Words: Specify the control parameters required by the FEC Controller.
• Frame Data: The actual data to be processed by the FEC Controller.
The Frame Control and Data are passed to the FEC Controller using Frame Descriptors.
Figure 22-3 Data Structure of Control Information

General
CRC
DownLink
Encode
Parameters
Rate Match
127 0 Interleaver
Addr
Scrambler
Control
Control
Size
General
CRC
Frame
Descriptor Decode
Uplink
Data DeRatematch Parameters
Total
Size De-interleave
HARQ

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22.4 FEC Direct Memory Access (DMA) Controller

22.4.1 Feature List

• One DMA channel (1 AXI bus master.)
• Multiple links of descriptors (or instructions.) Frame/ Buffer Descriptors can be linked for long operations.
• Frame and Buffer descriptors provide information about the packet to be transferred.
• Combined or Independent descriptors for Inbound and Outbound transfers.
• Supports scattering and gathering of data buffers.
• DMA can be started by an external signal or by register programming.
• The FEC Downlink has one DMA engine shared between 3G DL and 4G DL; the FEC Uplink has none DMA
engine shared between 3G UL and 4G UL.

22.4.2 DMA Hardware Interface

• Customer Interface—Table 22-1 shows the FEC DMA interface.
• Standard Interface—There are standard AXI and APB3 bus interface.

Table 22-1 FEC DMA Interface

Name I/O Description
CLK_IO I Synchronous and 1 or 2 times faster than CLK_AXI. The rising edge coincides with the CLK_AXI
rising edge.
MM_REQR O Read request from DMA
MM_ACKR I Read acknowledge from I/O application.
MM_RDATA[128:0] O Data sent from DMA to I/O Application. See Table 22-2 for the definition.
MM_RSIZE[3:0] I Number of bytes. 0 = 16 bytes. Should be 0 always. Must be 0 when access SOF or EOF word.
MM_EOFBUSY O Busy with the previous End-of-Frame (EOF). Do not write another EOF word.
MM_REQW O Write request from DMA.
MM_ACKW I Write acknowledge
MM_WDATA[128:0] I Data sent from I/O Application to DMA. See Table 22-3 for the definition.
MM_WSIZE[3:0] I Number of bytes. 0 = 16 bytes. Must be 0 when access SOF or EOF word.
IRQMem2DMA O Level interrupt. OR function of IRQFDONE, IRQFREADY, IRQFLAST, ERRAXIR, and ERRAXIW
IRQDMA2Mem O Level interrupt. OR function of IRQFDONE, IRQFREADY, IRQFLAST, IRQFLUSH, ERRAXIR, and
ERRAXIW

Table 22-2 MM_RDATA[128:0] Definition

Bit Start of Frame End of Frame Data
128 1 1 0
127 0 1 Data
126-123 TBD Numbers of valid bytes in the last Data
word
122-0 TBD TBD Data

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Table 22-3 MM_WDATA[128:0] Definition

Bit Start of Frame End of Frame Data
128 1 1 0
127 0 1 Data
126-123 TBD Reserved Data
122-0 TBD TBD Data

22.4.3 DMA Data Structures

The DMA controller exchanges control information and data with the system through three data structures:
• Frame descriptors
• Buffer descriptors
• Data buffers
Figure 22-4 shows how these data structures are related.
Figure 22-4 FEC DMA Data Structure

Queue
Access Frame Descriptors

Head Next Next Next

System System System

FStatus FStatus FStatus

FControl FControl FControl

Buffer BPointer BPointer BPointer

Descriptors
BControl BControl BControl

BPointer BPointer BPointer

BControl BControl BControl

BPointer BPointer

BControl BControl

Data Buffers

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NOTE: The memory address of a frame descriptor Word0 must be 16-byte align. The least
significant 4 bits of Frame Head and Frame Next must be 0. Frame and Buffer Words
must be consecutive.
For DMA to start operating, Frame Head must not be 0. For DMA to continue, Frame
Next must not be 0.
When Register FSYN = 1, only 8 Bpointer/BControl pairs are allowed. Both In and
Outbound share the same frame descriptor.

22.4.4 Frame and Buffer Descriptors

Frame descriptors must be aligned on 16-byte boundaries. Buffer descriptors must follow Frame descriptors.
Both the In and Outbound directions can use a common Frame/Buffer descriptors. Or each can have each own
Frame/Buffer descriptors.

NOTE: In this section, some different naming conventions have been inherited.
• IO = I/O Application such as FEC or FFT
• Inbound = Data are moved from Memory to DMA = Mem2Dma = M2D = Transmit = From Memory to
IO = M2IO
• Outbound = Data are moved from DMA to Memory = Dma2Mem = D2M = Receive = From DMA to
Memory = IO2M

Table 22-4 Mem2Dma (or memory to I/O) Frame and Buffer Descriptor
Bit Name Description
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used
Frame Word1 = FControl0. Offset: x4
31 – 17 Not Used.
16 – 3 Reserved
2 BRESP_N 1: No waiting for AXI Bresp. Do not care if any AXI write successfully gets to the destination.
1 FPAUSE Pause after finishing this frame.
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Frame Word2 = FControl1. Offset: x8
31 – 0 Not used
Frame Word3 = FStatus. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.
30 – 16 Not used
15 – 8 D2MBdesc Zero.
7– 0 M2DBdesc Mem2Dma Number of Bpointer/BControl pairs. Buffer Words always start at offset x10.
Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer.

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Table 22-4 Mem2Dma (or memory to I/O) Frame and Buffer Descriptor (Continued)
Bit Name Description
Buffer Word 1 = BControl. Offset: x14
31 – 30 Reserved. Must be 0.
29 – 27 LAST_BYTE_HOLE Beginning invalid bit (or hole) location in the last byte. Bit numbering method: 0 to 7, counting
from left to right. Zero means all bits are valid. If BLEN = 1, Last_Byte_Hole must be greater
than First_Byte_Bit. In this case, Zero means 8 or no holes after the First_Byte_Bit.
26 – 24 FIRST_BYTE_BIT Beginning valid bit location in the first byte. Bit numbering method: 0 to 7, counting from left to
right. If BLEN = 1, Last_Byte_Hole must be greater than First_Byte_Bit.
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Buffer Word 2 = BPointer. Offset: x18
Buffer Word 3 = BControl. Offset: x1C
Buffer Word 4 = BPointer. Offset: x20
Buffer Word 5 = BControl. Offset: x24
Etc..

Table 22-5 Dma2Mem (or from I/O to memory) Frame and Buffer Descriptor
Bit Name Description
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used
Frame Word1 = FControl0. Offset: x4
31 – 17 Not Used.
16 – 3 Reserved
2 BRESP_N No waiting for AXI Bresp. Do not care if any AXI write successfully gets to the destination.
1 FPAUSE Pause after finishing this frame.
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Frame Word2 = FControl1. Offset: x8
31 – 0 Not used
Frame Word3 = FStatus. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.
30 – 16 Not used
15 – 8 D2MBdesc Dma2Mem (from I/O to memory) Number of Bpointer/BControl pairs. Buffer Words always
start at offset x10
7– 0 M2DBdesc Zero.
Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer.
Buffer Word 1 = BControl. Offset: x14
31 – 24 Reserved. Must be 0.

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Table 22-5 Dma2Mem (or from I/O to memory) Frame and Buffer Descriptor (Continued)
Bit Name Description
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Buffer Word 2 = BPointer. Offset: x18
Buffer Word 3 = BControl. Offset: x1C
Buffer Word 4 = BPointer. Offset: x20
Buffer Word 5 = BControl. Offset: x24
Etc..

Table 22-6 Common, or 1, Frame and Buffer Descriptor for both Mem2Dma and Dma2Mem (FCOM)
Bit Name Description
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used
Frame Word1 = FControl0. Offset: x4
31 – 17 Not Used.
16 – 3 Reserved
2 BRESP_N No waiting for AXI Bresp. Do not care if any AXI write successfully gets to the destination.
1 FPAUSE Pause after finishing this frame.
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Frame Word2 = FControl1. Offset: x8
31 – 0 Not used
Frame Word3 = FStatus. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.
30 – 16 Not used
15 – 8 D2MBdesc Dma2Mem Number of Bpointer/BControl pairs. Buffer descriptors start at offset x10 + 8 *
M2DBdesc.
D2MBdesc + M2DBdesc = 8 maximum if Register FSYN = 1.
7– 0 M2DBdesc Mem2Dma Number of Bpointer/BControl pairs. Buffer descriptors always start at offset x10.
D2MBdesc + M2DBdesc = 8 maximum if Register FSYN = 1.
Mem2Dma Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer.
Mem2Dma Buffer Word 1 = BControl. Offset: x14
31 – 30 Reserved. Must be 0.
29 – 27 LAST_BYTE_HOLE Beginning invalid bit (or hole) location in the last byte. Bit numbering method: 0 to 7, counting
from left to right. Zero means all bits are valid. If BLEN = 1, Last_Byte_Hole must be greater
than First_Byte_Bit. In this case, Zero means 8 or no holes after the First_Byte_Bit.
26 – 24 FIRST_BYTE_BIT Beginning valid bit location in the first byte. Bit numbering method: 0 to 7, counting from left to
right. If BLEN = 1, Last_Byte_Hole must be greater than First_Byte_Bit.

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Table 22-6 Common, or 1, Frame and Buffer Descriptor for both Mem2Dma and Dma2Mem (FCOM)
Bit Name Description
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Mem2Dma Buffer Word N = BPointer. Offset: x10 + N*4 (N = even integer)
Mem2Dma Buffer Word N+1 = BControl. Offset: x14 + N*4 (N = even integer)
…..
Dma2Mem Buffer Word 0 = BPointer. Offset: 8 * M2DBdesc + x10
31 – 0 BPOINTER Address pointer of a data buffer.
Dma2Mem Buffer Word 1 = BControl. Offset: 8 * M2DBdesc + x14
31 – 24 Reserved. Must be 0.
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Dma2Mem Buffer Word M = BPointer. Offset: 8 * M2DBdesc + x10 + M*4 (M = even integer)
Dma2Mem Buffer Word M+1 = BControl. Offset: 8 * M2DBdesc + x14 + M*4 (M = even integer)
Frame Word0 = FNext. Offset: x0

Table 22-7 Mem2Dma Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus. Offset: x8
30 - 0 No change. Register IOSTATUS should be 0.
Frame Word3 = FStatus. Offset: xC
31 FDONE = 1 if Register DONOSTA = 0 and when this frame is completed. Else no change.
30 - 16 No change. Register IOSTATUS should be 0.

Table 22-8 DMA2Mem Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus. Offset: x8
31 – 0 STATUS = I/O Status bit[31:0] if Register IOSTATUS = 1. Else no change.
Frame Word3 = FStatus. Offset: xC
31 FDONE = 1 if Register DONOSTA = 0 and when this frame is completed. Else no change.
30 – 16 STATUS = I/O Status bit[46:32] if Register IOSTATUS = 1. Else no change.

Table 22-9 Common Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus. Offset: x8
31 – 0 STATUS = I/O Status bit[31:0] if Register IOSTATUS = 1. Else no change.
Frame Word3 = FStatus. Offset: xC
31 FDONE = 1 if Register DONOSTA = 0 and when this frame is completed. Else no change.
30 – 16 STATUS = I/O Status bit[46:32] if Register IOSTATUS = 1. Else no change.

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22.4.5 DMA Operation

22.4.5.1 Design Notes

FCOM is the common Frame descriptor for both in and outbound. But in and outbound transfers are independent.
FSYN is much like FCOM but only 8 bpointer/bcontrols are allowed. A DMA operation completes when both in and
outbound transfers complete.
When using FCOM, the outbound transfer may complete before the inbound and will set FDONE. That FDONE
may cause a misinterpretation for the inbound.
FCOM is used when the FHEADs of both in and outbound are the same.

22.4.5.2 DMA Interrupt

The IRQEN bit in a Frame descriptor and the IRQFDON bit in the configuration register cause equivalent effects.
The IRQFDON is static and set by APB bus.
The FEC DMA generates two separate IRQ signals: IRQMEM2DMA and IRQDMA2MEM. This method gives
flexibility on monitoring both the In and Outbound transfers.
When using FCOM (common frame descriptors), IRQEN bit appears in one descriptor will be seen by both In and
Outbound DMA engines. Both IRQ signals will be generated. Software may only want to know the DMA2MEM
interrupt. But in some cases (e.g. debugging), Software may want to see MEM2DMA interrupt as well. Use IRQDIS
register to disable IRQEN.
If in the block, where this DMA resides, these two IRQ signals are OR'ed before going to ARM then Software needs
to check both In and Outbound DMA registers to find out who causes the interrupt.
To know what causes IRQMEM2DMA, read offset 014 and 310.
To know what causes IRQDMA2MEM, read offset 114 and 310.

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23 Security Protocol Accelerator (SPA)
and Security Encryption Engine
This chapter introduces the features and implementation details of the SPA block.

23.1 Feature List

• The Security Protocol Accelerator (SPA) is the combination of two major blocks:
– Internet Protocol Security (IPSec) block
– SPAcc-PDU block
• The IPSec block does the full ESP/AH processing. Inside of the IPSec block there are three engines:
– AES core (ECB, CBC, CTR modes)
– (3)DES core
– Hashing core (HMAC-SHA-1/SHA-256/MD5)
• The IPSecESP/AH engine offloads the following protocol-level processing:
– IPv4/IPv6 AH mode processing
– IPv4/IPv6 ESP mode processing
– Transport Mode processing
– Tunnel Mode processing
– Extended Sequence Numbers

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23.2 IPSec Block Diagram

Figure 23-1 shows the block diagram for the IPSec section of the SPA.
Figure 23-1 IPSec Block Diagram

aes_wrapper

Memory
Context
AES
Core

Message
Memory
Inbound
des_wrapper
Packet

Memory
Context
Processor
DES
Core

Message
Memory
Security
Resource
Manager
Slave Interface

Decoder

hmac_adv_wrapper
Decoder
Arbiter

Memory
Context
Memory
Secret
Hashing
Master Interface

Outbound Core
Packet
Processor

Message
Memory

SDMA

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23.3 SPAcc-PDU Block Diagram

Figure 23-2 SPAcc-PDU Block Diagram

System Memory Host Processor

AXI
System
Bus

AXI AXI
Master Slave

SPAcc TRNG PKA

SPAccͲPDU

The SPAcc-PDU is a complex design with several engines:

• Security Protocol Accelerator (SPAcc)—The SPAcc engine consist of:
– AES Core with ECB, CBC, CCM, CTR modes.
– Kasumi Core with ECB, UEA1 (f8), UIA1 (f9) modes.
– SNOW-3G Core with ECB, UEA2 (f8), UIA2 (f9) modes.
– ZUC
• Public Key Accelerator (PKA)—The PKA engine for RSA provides Modular Math (i.e. ModExp, ModDiv, etc.)
and the associated Pre-Compute functions across multiple key sizes (512, 1024-bit “native” RSA operations
and 2048-bit RSA operations using CRT).
• True Random Number Generator (TRNG)—The TRNG engine combines a whitening circuit with a noise
source that provides automatic seeding of the random number stream and an ongoing source of entropy to the
core.

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Figure 23-3 SPAcc Block Diagram

AXI Slave AXI Master

Register/ SDMA
Decode
Interface

Sequencer
Cipher Data Hash Data
Buffer Buffer

MultiͲmode AES Kasumi (ECB, f8) SNOWͲ3G (ECB, f8) f9

Cipher Key Buffer Hash Key Buffer

23.4 True Random Number Generator (TRNG)

23.4.1 Overview

The True Random Number Generator (TRNG) generates random data that is statistically equivalent to a uniformly
distributed random data stream. The circuit includes a noise generator which creates non-deterministic random
noise to seed a noise whitener circuit. The output of the noise whitener is the random number.
The TRNG can operate in one of two modes: self-seeding mode (also called random mode) and nonce seeding
mode. In self-seeding mode, the ring oscillators automatically produce a seed that is fed to a whitening circuit. The
initial automatic self-seeding takes on the order of 260,000 clock cycles to complete. After the initial self-seeding

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phase, the TRNG will produce pseudo-random numbers at a rate of one 128-bit random number every 512 clock
cycles.
In nonce-seeding mode, a user specified is injected into the noise generation circuit as an alternate way of seeding.
In this case the TRNG is ready to generate random numbers as soon as the nonce write operation is complete.
The host may initiate a nonce TRNG seeding operation at any time after reset. A self-seeding operation may be
initiated whenever another self-seeding operation is not under way.
The supported feature set is listed as below:
• Random Number Generation (TRNG)
– Internal random (re)seed operation
– Host-driven nonce reseed option
– 128-bit random number generation

23.4.2 TRNG Architecture

The TRNG consists of a random noise seed generator that feeds into a noise whitening cryptographic circuit. A host
interface allows access to a set of control and status registers to configure and monitor the core’s activity.

23.4.2.1 Random Noise Seed Generator

The random noise seed generator produces seed bits to supply the follow-on pseudo random number generator
(PRNG) with an initial state.
Figure 23-4 Random Noise Seed Generator

Ring Ctrl

Ring 5

XOR D Q D Q Accumulator
Ring 4 G G

Sampling FF #1 Window Gate

XOR D Q D Q XOR
Ring 1 G G LFSR

Sampling FF #2 Gate modulator

Seed bit
Ring 0

The random noise seed generator is based on a number of ‘relatively prime’ length ring oscillators. Several of these
ring oscillators are mixed together and delivered to accumulators. (The term ‘mixed’ here is used in the modulation
sense of the word. The modulator is this case is a multi-input XOR gate.)

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The ring oscillators have lengths chosen such that:

1. Each ring length is based on a different prime number to minimize periodic behaviour.
2. The lengths of rings 0 through 5 are all different and chosen such that the middle frequency is approximately 2
times the system clock frequency. Each ring is chosen to be a different prime number of inverting elements.
The frequencies are chosen to ensure that sufficient edges are seen at the sampling flip flop to ensure the flip
flop enters metastable timing regions a reasonable fraction of the time. The mixing function is a standard logical
exclusive-OR (XOR).
3. Rings 1 through 5 are mixed and delivered to sampling flop #1. The sample flop is designed to be driven into
metastability some fraction of the time and the result is accumulated through two non- overlapping time
windows.
4. Rings 0 through 4 are mixed and delivered to sampling flop #2 This set is designed to both perturb the seed
LFSR while driving the front end LFSR flip flop into metastability some fraction of the time.
Seed bits are created until the whitening element declares it has been completely seeded. However, in order to
maximize entropy, the seed LFSR runs continuously, even after the whitener declares it has been completely
seeded, unless the rings are shut down by an external circuit.

23.4.2.2 Whitening Circuit

This circuit is comprised of two cascaded long-chain LFSR rings (128 and 127 bits respectively).
On startup, the output bits produced by the random noise seed generator are shifted into the LILI-II LFSR registers
as they are produced. When this LILI-II key has been loaded, a finite state machine (FSM) triggers the LILI-II key
stream generator to create a pseudo random stream. The pseudo random stream is captured into an output shift
register as it is produced.
The length of the resulting random number depends on the parameterized width of the output shift register. A
minimum gate-count system will have a 32-bit result while a maximal version will have 128 bits.
A reseeding sequence can be commanded from the host whenever it desires to renew the entropy state. The
reseeding can either use the existing random noise generator or a host supplied nonce. The random reseed
operation can only initiated when another random reseed operation is not under way.
Figure 23-5 Seed/Whitener Circuit

Nonce Reseed
LILI-2 Key Stream Command
Free Random Generator
Noise Generator Seed Cntr

Random Reseed
Command
Bit Cntr Shift Reg

Status and IRQ IRQ Random Number

ACK

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23.4.3 TRNG Usage

The TRNG can operate in one of 2 modes: random re-seed mode and nonce re-seed mode.
In random re-seed mode, the TRNG uses a set of free running ring oscillators to generate a random seed for a
Pseudo Random Number Generator (PRNG). The random reseed operation takes between 200,000 and
300,000 clock cycles. The PRNG continuously generates 128-bit pseudo random numbers based on the random
seed. The PRNG can be reseed from the ring-based seed generator. After reset the TRNG automatically performs
a random re-seed operation. When a random reseed operation is under way, the host must not initiate a new
random reseed operation.
In nonce reseed mode, the TRNG is “manually” seeded / reseeded via a host defined nonce. After the reseed
operation, the PRNG continuously generates 128-bit pseudo random numbers based on this seed. A new nonce
reseed operation may be initiated at any time. The nonce reseed operation may even be initiated while a random
reseed operation is under way, as this automatically terminates the ongoing random reseed operation.
The TRNG_CTRL register allows the host to select several different modes of operation.
When written with a 1 the RAND_RESEED bit causes the circuit to be (re)seeded from the random seed circuit. A
read of this bit will show the current state of a random reseeding operation.
When written with a 1 the NONCE_RESEED bit causes the circuit to be (re)seeded by the host in parallel from the
TRNG_DATAx registers. A nonce reseed involves the following steps:

1. Write the NONCE_RESEED bit with a 1 to place the TRNG in nonce reseed mode. All other bits should be
zero.
2. Write the TRNG_DATAx registers with the first 128 bits of the 255 bit nonce.
3. Write the TRNG_CTRL register with {NONCE_RESEED, NONCE_RESEED_LD, NONCE_SEED_SELECT}
== 3'b110.
4. Write the TRNG_DATAx registers with the second 127 bits of the 255 bit nonce. The 127 bits are formatted
across the registers as follows: {TRNG_DATA3[30:0], TRNG_DATA2, TRNG_DATA1, TRNG_DATA0}.
5. Write the TRNG_CTRL register with {NONCE_RESEED, NONCE_RESEED_LD, NONCE_SEED_SELECT}
== 3'b111.
6. Clearing the NONCE_RESEED bit completes the nonce reseeding process.
At the completion of either type of (re)seeding operation the TRNG will automatically begin generating the first new
random number in the same manner as if the GEN_NEW_RANDOM bit had been written with a0x1.
The TRNG will assert the TRNG_IRQ_STAT bit and an interrupt (if enabled) upon completion of a random number
generation. The host may now extract the random data from the TRNG_DATAx registers. The TRNG_IRQ_STAT bit
must be acknowledged. The data has no endianess and thus it does not matter whether TRNG_DATA0 is extracted
as the least or most significant word.
Once a random number has been read, writing a 1 to the GEN_NEW_RANDOM bit causes the TRNG to begin
collecting a new random number in the TRNG_DATAx registers. Reading the GEN_NEW_RANDOM bit returns the
current state of the random number generation operation.

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Figure 23-6 TRNG Signaling Protocol

clk

I_en

I_addr A B C D E F G H

I_wr

I_data a b c d

I_rd

O_data e f g h

O_ack

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24 Chip Rate Processor (CRP)
Correlator
This chapter describes the CRP correlator and sub-blocks for Transcede 2120, Transcede 2150, and Transcede
2200.

NOTE: CRP correlator is for Transcede 2120, Transcede 2150, and Transcede 2200.

24.1 Feature List

The Chip Rate Processor (CRP) Correlator processor has the following features.
• Types of functional blocks inside the CRP:
– RACH Preamble Detector (RPD)
– Pilot Search Correlator (PSC)
– Correlator for Control Channels (COR-C)
– Correlator for Traffic Channels (COR-T)
• AXI interface for data and control.
• DMAs are used for moving data in and out.

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All four kinds of modules have the AXI interface for data and control configuration. DMA is used to transfer the data.
The number of copies of each module is highly scalable to the size and capacity of base station.
Figure 24-1 shows top level block diagram, on which, each module has one copy as an example.
Figure 24-1 Top Level Block Diagram of CRP

Chip Rate Processor

RPD

AXI

PSC

CORͲC

CORͲT

The Transcede 2120, Transcede 2150, and Transcede 2200 have the following capabilities related to the CRP:
• Number of cell = 1. (It could support multiple cells but with the same amount of total users.)
• Number of Rx antennas = 2
• Number of users supported = 24(each can support one R99 RL and HSPA RL)
• Aggregate L1 T-put for uplink = 11.5 Mbps.
• Number of G-rake users = 8
• Cell size = 500 m

24.2 RACH Preamble Detector (RPD)

The RPD utilizes the correlator bank to search RACH preamble. In every access-slot, it searches a timing window
with 32 chips of delay spread, and generates power profile for 32 chips. In large cells, multiple search windows can
be used to cover larger arrival RACH timing difference. The RPD design provides the following capabilities:
• Sampling rate = 2x chip rate. Results can be interpolated to higher sampling resolution by software.
• Search all 16 signatures using Hadamard transform.
• One search window = 32 chips.
• With 500 Mhz clock frequency, the search of one window can be done within 31.5 WCDMA chips.
• Multiple search windows can be used to cover larger spread of arrival timing.

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• Configurable coherent and non-coherent accumulation length.

Figure 24-2 depicts the RPD architecture.
Figure 24-2 RPD Top Level Block Diagram

Search Engine Output

Even Sample Memory
(antennaͲ0) Even
DMA
Input
Memory
(antenna0)

Search Engine Output

Odd Sample Memory
(antennaͲ0) Odd

AXI

Controller RPD

The PRACH preamble searcher is consisted of input memory, a controller and two engines for searching even
samples and odd samples. Each engine has its own output memory. The search engines are used for computing
correlations for 32 timing candidates. The even search engine processes 32 timing candidates τ = [0,1,...,31]Tchip
at a time, the odd search engine processes 32 timing candidates τ = ([0,1,...,31] + 0.5) Tchip at a time. The
correlation results are stored into the output buffer for each engine. The controller is responsible to send the data
from input memory and split the even samples to even engine and odd samples to odd engine. After the first run of
32 chip of delay spread is searched, the controller will start the second round of search with timing candidates for
the next 32 chips. This process is repeated until all the timing candidates are completed.

24.3 Pilot Search Correlator (PSC)

The PSC searches all symbols of uplink DPCCH channel and generates power profile for a search window. For
each user, the pilot pattern can be configured to include all data fields in DPCCH, including pilot, TPC, etc. Multiple
search windows are used to cover multiple users and or larger delay spread.
The PSC has the following capabilities:
• Supports coherent/non-coherent accumulation of pilot symbol and other control bits.
• Supports weighted combining between different control fields.
• Searches once per slot and generate power profile of search window.
• One search window = 64 chips for one user.
• With clock frequency = 500 Mhz, the search of one window can be done in around 20 WCDMA chips. Multiple
user or larger delay spread can be covered by running PSC multiple times.

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The top level functional diagram of the pilot search correlator (PSC) is shown in Figure 24-3.
Figure 24-3 Top Level Diagram of PSC Unit

Controller

Even Path
samples
AXI Searcher
Input Even
Output
Mem
Mem
Odd Path
samples
Searcher
Odd

The pilot searcher consists of input memory, a controller and two engines for searching even samples and odd
samples.

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24.4 Correlator for Control Channels (COR-C)

The COR-C simultaneously despreads control channels and overhead channels. It is responsible for UL-DPCCH,
HS-DPCCH, E-DPCCH, and the control channel of RACH message part. It has the following capacities:
• Supports timing adjustment <±1 chip with resolution of 1/16 chip.
• Interpolation filter: Input signal at 2x chip rate, output 1/16 chip rate.
• No multipath combining for COR-C.
• Supports Frequency error compensation using NCO.
• Supports early, ontime and late finger measurement.
• Multiple user supported by time sharing of correlator engines and multiple engines.
• All users are being processed simultaneously, processing latency around 32 chip of time.
• With clock frequency = 500 Mhz, 24 users, 2 RX stream. The processing margin is 63%.
The block diagram of the control channel correlator is shown in Figure 24-4.
Figure 24-4 Block Diagram of COR-C

Command
Command
Correlator queue queue
Engine

Command
queue
Filter Engine
controller
controller
Circular Controller
Buffer
Correlator Output
engine
Correlator memory
Output
I/Q engine memory
Buffer Correlator Output
8 buffer
(16x) engine memory

The COR-C consists of one filter engine and multiple correlator engines. The number of correlator engines is
configurable to match with different requirements. In Transcede 2120, Transcede 2150, and Transcede 2200, the
number of engine is set to one.
The filter engine has an input buffer holding multiple streams data with 32 chips for each stream. It has an
interpolation filter which takes the data from each stream and after interpolation the output data is sent to a buffer.
The data in buffer are broadcasted to correlator engines to despread in parallel. The outputs are sent to the output
memory without combining.

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24.5 Correlator for Traffic Channels (COR-T)

The COR-T despreads and combines multipaths for Traffic channels including DPDCH, E-DPDCH and RACH
message data part. For a user or a group of user which frame timings similar, the COR-T can take IQ sample from
an external memory and provide accurate timing interpolation, despread user signals and generate combined
symbols at once. Multiple runs are used for multiple group of users.
The COR-T has the following features:
• Despreads one TTI (2ms/10ms) of user signals from DDR memory at a time.
• Multiple users whose TTI ends at similar timing are despreaded at the same time to reduce DDR throughput.
• One engine can support 4 fingers per antenna. Multiple engines can be used to support more fingers for G-
rake receiver.
• Multipath combining supported between fingers from the same antenna. Up to 224 chips of delay spread can
be combined.
• With clock frequency = 500 Mhz, the 10 ms TTI processing for one user on 1 RX stream can be done in
around 295 WCDMA chips, and the 2 ms TTI processing for one user on 1 RX stream can be done in around
59 WCDMA chips.
• Supports data combining with provided combining weight from SW.
• Supports frequency error compensation by using NCO.
The traffic channel processor diagram is illustrated as Figure 24-5.
Figure 24-5 Traffic Channel Despreader

Command
Correlator Engine
queue
Command
queue
Command
Filter Engine Queue
Combiner Engine
controller
controller
Input Controller Chest
Buffer Memory
Correlator
engine
Correlator
I/Q engine
Correlator Combiner Output
Upsample
buffer
8 Engine Core Engine Core Memory
Buffer

The COR-T consists of a filter engine, multiple correlator engines and multiple combiners.

24.6 Memory to Memory DMA Controller for CRP (MDMA-CRP)

Instructed by Frame and Buffer Descriptors, the Direct Memory Access (DMA) controller transfers data between
memory locations.

24.6.1 Feature List

• One DMA channel (1 AXI bus master.)
• Up to 8 links of descriptors (or instructions.) Frame/ Buffer Descriptors can be linked for long operations.
• Frame and Buffer descriptors provide information about the packet to be transferred.
• Common (same) or Independent descriptors for Inbound and Outbound transfers

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• Supports scattering and gathering of data buffers.

• DMA can be started by an external signal or by register programming.

24.6.2 DMA Hardware Interface

All signals are synchronous with CLK.
• Customer Interface—Table 24-1 shows the MDMA interface.
• Standard Interface—There are standard AXI and APB3 bus interface.

Table 24-1 MDMA Interface

Name I/O Description
DMAREQ[Link-1:0] I External request for DMA. One per link. Once H, stays H until DMAACK goes H. To use, please
set Register STARTEXT to 1.
DMAACK[Link-1:0] O Request acknowledge. One per link. Once H, stays H until DMAREQ goes L. To use, please set
Register STARTEXT to 1.
IRQMem2DMA O Level interrupt. OR function of IRQFDONE, IRQFREADY, IRQFLAST, ERRAXIR, and ERRAXIW.
IRQDMA2Mem O Level interrupt. OR function of IRQFDONE, IRQFREADY, IRQFLAST, IRQFLUSH, ERRAXIR, and
ERRAXIW.
IRQ_RTDONE_ACK I Not used.
IRQ_RTDONE O Not used.
IRQ_RTDONE_ID O Not used.
IRQ_WRDONE_ACK I Acknowledge to IRQ Write Transfer Done.
IRQ_WRDONE O IRQ Write Transfer Done.
IRQ_WRDONE_ID O IRQ Write Transfer Done ID number.

24.6.3 DMA Data Structures

The DMA controller exchanges control information and data with the system via three data structures:
• Frame descriptors
• Buffer descriptors
• Data buffers

NOTE: The memory address of a frame descriptor Word0 must be 16-byte align. The least
significant 4 bits of Frame Head and Frame Next must be 0. Frame and Buffer Words
must be consecutive.
For DMA to start operating, Frame Head must not be 0. For DMA to continue, Frame
Next must not be 0.
When Register FSYN = 1, only 8 Bpointer/BControl pairs are allowed. Both In and
Outbound share the same frame descriptor.

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Figure 24-6 shows how these data structures are related:

Figure 24-6 DMA Data Structure

Queue
Access Frame Descriptors

Head Next Next Next

FControl FControl FControl

FControl FControl FControl

FControl FControl FControl

Buffer BPointer BPointer BPointer

Descriptors
BControl BControl BControl

BPointer BPointer BPointer

BControl BControl BControl

BPointer BPointer

BControl BControl

Data Buffers

24.6.4 Frame and Buffer Descriptors

Frame descriptors must be aligned on 16-byte boundaries. Buffer descriptors must follow Frame descriptors.
Both the In and Outbound directions may use the same Frame descriptors. Each has its own Buffer descriptors.

NOTE: In this section, some different naming conventions have been inherited.
• IO = I/O Application such as FEC or FFT
• Inbound = Data are moved from Memory to DMA = Mem2Dma = M2D = Transmit = From Memory to
IO = M2IO
• Outbound = Data are moved from DMA to Memory = Dma2Mem = D2M = Receive = From DMA to
Memory = IO2M

Table 24-2 Mem2Dma (or memory to I/O) Frame and Buffer Descriptor
Bit Name Description
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used

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Table 24-2 Mem2Dma (or memory to I/O) Frame and Buffer Descriptor (Continued)
Bit Name Description
Frame Word1 = FControl0. Offset: x4
31 – 17 Not Used.
16 FACK_N 1: No DMAACK to be asserted at the end of this frame.
15 - 12 IRQTID Reserved for TID
11 - 4 IRQTID Task Done ID number when IRQTDONE is active
3 IRQTDONE IRQ Task Done Enable. Set an interrupt when acknowledging to an external DMAREQ.
2 BRESP_N 1: No waiting for AXI Bresp. Don’t care if any AXI write is successfully get to the destination.
1 FPAUSE Pause after finishing this frame. Allow the arbiter to give the AXI bus to another link.
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Frame Word2 = FControl1. Offset: x8
31 – 0 Not used
Frame Word3 = FStatus. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.
30 – 16 Not used
15 – 8 D2MBdesc Zero.
7– 0 M2DBdesc Mem2Dma Number of Bpointer/BControl pairs. Buffer Words always start at offset x10.
Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer.
Buffer Word 1 = BControl. Offset: x14
31 – 24 Reserved. Must be 0.
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Buffer Word 2 = BPointer. Offset: x18
Buffer Word 3 = BControl. Offset: x1C
Buffer Word 4 = BPointer. Offset: x20
Buffer Word 5 = BControl. Offset: x24
Etc..

Table 24-3 Dma2Mem (or from I/O to memory) Frame and Buffer Descriptor
Bit Name Description
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used
Frame Word1 = FControl0. Offset: x4
31 – 17 Not Used.
16 FACK_N 1: No DMAACK to be asserted at the end of this frame.

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Table 24-3 Dma2Mem (or from I/O to memory) Frame and Buffer Descriptor (Continued)
Bit Name Description
15 - 12 IRQTID Reserved for TID
11 - 4 IRQTID Task Done ID number when IRQTDONE is active
3 IRQTDONE IRQ Task Done Enable. Set an interrupt when acknowledging to an external DMAREQ.
2 BRESP_N No waiting for AXI Bresp. Don’t care if any AXI write is successfully get to the destination.
1 FPAUSE Pause after finishing this frame. Allow the arbiter to give the AXI bus to another link.
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Frame Word2 = FControl1. Offset: x8
31 – 0 Not used
Frame Word3 = FStatus. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.
30 – 16 Not used
15 – 8 D2MBdesc Dma2Mem (from I/O to memory) Number of Bpointer/BControl pairs. Buffer Words always
start at offset x10
7– 0 M2DBdesc Zero.
Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer.
Buffer Word 1 = BControl. Offset: x14
31 – 24 Reserved. Must be 0.
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Buffer Word 2 = BPointer. Offset: x18
Buffer Word 3 = BControl. Offset: x1C
Buffer Word 4 = BPointer. Offset: x20
Buffer Word 5 = BControl. Offset: x24
Etc..

Table 24-4 Common, or 1, Frame and Buffer Descriptor for both Mem2Dma and Dma2Mem (FCOM)
Bit Name Description
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used
Frame Word1 = FControl0. Offset: x4
31 – 17 Not Used.
16 FACK_N 1: No DMAACK to be asserted at the end of this frame.
15 - 12 IRQTID Reserved for TID
11 - 4 IRQTID Task Done ID number when IRQTDONE is active
3 IRQTDONE IRQ Task Done Enable. Set an interrupt when acknowledging to an external DMAREQ.

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Table 24-4 Common, or 1, Frame and Buffer Descriptor for both Mem2Dma and Dma2Mem (FCOM)
Bit Name Description
2 BRESP_N No waiting for AXI Bresp. Don’t care if any AXI write is successfully get to the destination.
1 FPAUSE Pause after finishing this frame. Allow the arbiter to give the AXI bus to another link.
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Frame Word2 = FControl1. Offset: x8
31 – 0 Not used
Frame Word3 = FStatus. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.
30 – 16 Not used
15 – 8 D2MBdesc Dma2Mem Number of Bpointer/BControl pairs. Buffer descriptors start at offset x10 + 8 *
M2DBdesc.
D2MBdesc + M2DBdesc = 8 maximum if Register FSYN = 1.
7– 0 M2DBdesc Mem2Dma Number of Bpointer/BControl pairs. Buffer descriptors always start at offset x10.
D2MBdesc + M2DBdesc = 8 maximum if Register FSYN = 1.
Mem2Dma Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer.
Mem2Dma Buffer Word 1 = BControl. Offset: x14
31 – 24 Reserved. Must be 0.
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Mem2Dma Buffer Word N = BPointer. Offset: x10 + N*4 (N = even integer)
Mem2Dma Buffer Word N+1 = BControl. Offset: x14 + N*4 (N = even integer)
…..
Dma2Mem Buffer Word 0 = BPointer. Offset: 8 * M2DBdesc + x10
31 – 0 BPOINTER Address pointer of a data buffer.
Dma2Mem Buffer Word 1 = BControl. Offset: 8 * M2DBdesc + x14
31 – 24 Reserved. Must be 0.
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Dma2Mem Buffer Word M = BPointer. Offset: 8 * M2DBdesc + x10 + M*4 (M = even integer)
Dma2Mem Buffer Word M+1 = BControl. Offset: 8 * M2DBdesc + x14 + M*4 (M = even integer)

Table 24-5 Mem2Dma Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus. Offset: x8
30 - 0 No change.
Frame Word3 = FStatus. Offset: xC
31 FDONE = 1 if Register DONOSTA = 0 and when this frame is completed. Else no change.
30 - 16 No change.

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Table 24-6 DMA2Mem Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus. Offset: x8
31 – 0 STATUS I/O Status bit[31:0] if Register IOSTATUS = 1. Else no change.
Frame Word3 = FStatus. Offset: xC
31 FDONE = 1 if Register DONOSTA = 0 and when this frame is completed. Else no change.
30 – 16 STATUS I/O Status bit[46:32] if Register IOSTATUS = 1. Else no change.

Table 24-7 Common Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus. Offset: x8
31 – 0 STATUS = I/O Status bit[31:0] if Register IOSTATUS = 1. Else no change.
Frame Word3 = FStatus. Offset: xC
31 FDONE = 1 if Register DONOSTA = 0 and when this frame is completed. Else no change.
30 – 16 STATUS = I/O Status bit[46:32] if Register IOSTATUS = 1. Else no change.

24.6.5 DMA Operation

24.6.5.1 Design Notes

FCOM is the common Frame descriptor for both in and outbound. But in and outbound transfers are independent.
FSYN is much like FCOM but only 8 bpointer/bcontrols are allowed. A DMA operation completes when both in and
outbound transfers complete.
When using FCOM, the outbound transfer may complete before the inbound and will set FDONE. That FDONE
may cause a misinterpretation for the inbound.
FCOM is used when the FHEADs of both in and outbound are the same.

24.6.5.2 DMA Interrupt

The IRQEN bit in a Frame descriptor and the IRQFDON bit in the configuration register cause equivalent effects.
The IRQFDON is static and set by APB bus.
DMA generates 2 separate IRQ signals: IRQMEM2DMA and IRQDMA2MEM. This method gives flexibility on
monitoring both the In and Outbound transfers.
When using FCOM (common frame descriptors), IRQEN bit appears in one descriptor will be seen by both In and
Outbound DMA engines. Both IRQ signals will be generated. Software may only want to know the DMA2MEM
interrupt. But in some cases (e.g. debugging), Software may want to see MEM2DMA interrupt as well. Use IRQDIS
register to disable IRQEN.
If in the block, where this DMA resides, these 2 IRQ signals are OR'ed before going to ARM then Software needs
to check both the In and Outbound DMA registers to find out who causes the interrupt.
To know what causes IRQMEM2DMA, read offset K14 and N10.
To know what causes IRQDMA2MEM, read offset L14 and N10.

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25 Bit Processor
This chapter provides the block diagram of the bit processor and its features.

25.1 Feature List

• One Bit Processor
• One DMA channel to move data from memory location another memory location.
• Independent Inbound and Outbound Frame and Buffer descriptors provide information about the packet to be
transferred.
• DMA data structure supports scattering and gathering of data buffers.
• Programmable AXI burst length (maximum 16).
• Internal Function for 3G operation (for Transcede 2120, Transcede 2150, and Transcede 2200)
– Programmable CRC Polynomials (support byte aligned CRC only): gCRC12.
– The Scrambler for the HS-DSCH transport channel, it is used for scrambling of the CRC attached transport
block before the block segmentation and channel coding.
– Orthogonal Variable Spreading Factor generation (OVSF).
– Downlink Gold Code Scrambler.
– Rake Receiver Gold Code Scrambler.
– Chipwise accumulator for 3G DL channel combining.
• Internal Functions for 4G operation:
– Programmable CRC Polynomials (support byte aligned CRC only): gCRC24, gCRC16, gCRC8.
– LTE Scrambler / Descrambler.

25.2 Implementation Details

The 3G Downlink Spreading Code Generator is the combination of OVSF and Downlink Gold Code Scrambler,
while the 3G Uplink Spreading Code Generator is OVSF and Rake Receiver Gold Code Scrambler.
The Bit Processor integrates the following elements:
• Single channel bit-processor (BPDMA)
• Additional three pairs of DMAs (DMA1READ) and 3G downlink spreading code generation units (DL3_SCGU),
and their glue logic blocks (BITPCWRITE)
• A post-processing (combining/weighting) unit (POSTPROC_WRAP) including one more DL3_SCGU (for
optional "post-scrambling" only)
• Configuration registers (BPDMA_4DL_REG)

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Figure 25-1 Bit Processor Block Diagram

BPDMA

Others (UL3_SCGU, 4G_SCR/DESC, RAND, CRC, HSDCH)

AXI_0
Slave
DMA1LINK BITPC DL3_SCGU
(Full)

MUX
POSTPROC
DMA1READ BITPC_w DL3_SCGU

DL3_SCGU
AXI_1~3
Slaves
DMA1READ BITPC_w DL3_SCGU
(AR, R
Only)

DMA1READ BITPC_w DL3_SCGU

POSTPROC_WRAP
Addr[9:2],
DmaPsel_0~3

Addr Decoder
Addr[12:2]
APB Configuration Registers (2'sCmpl, Bypass, Chn_En, N_Trunc)

BPDMA_4DL_REG

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26 Memory to Memory DMA (MDMA)
Controller
This chapter describes the features and implementation of the MDMA controller.

26.1 Feature List

The Memory to Memory DMA (MDMA) controller block transfers data from/to memory to/from memory. In case the
ARM processor wants to free a certain area in the memory occupied with data by one of the peripherals, it can use
MDMA to read data from the current location and write it back to a new location.
The Transcede 2xxx has two Memory to Memory DMA (MDMA) controllers. Each MDMA controller has the
following features.
• One DMA channel (1 AXI bus master).
• Provides the option to move data from one place in the memory to another in the same or different memory.
• Frame/ Buffer Descriptors can be linked (or chained) for long operations.
• Frame and Buffer descriptors provide information about the packet to be transferred.
• Common (same) or Independent descriptors for Inbound and Outbound transfers.
• Supports scattering and gathering of data buffers.
• Supports data management using a 2 dimensional chained list. A chained list of frames and each frame can
have a chained list of data buffers.
• DMA can be started by an external signal or by register programming.

26.2 DMA Data Structures

The DMA controller exchanges control information and data with the system through three data structures:
• Frame descriptors
• Buffer descriptors
• Data buffers

NOTE: The memory address of a frame descriptor Word0 must be 16-byte align. The least
significant 4 bits of Frame Head and Frame Next must be 0. Frame and Buffer Words
must be consecutive.
For DMA to start operating, Frame Head must not be 0. For DMA to continue, Frame
Next must not be 0.
When Register FSYN = 1, only 8 Bpointer/BControl pairs are allowed. Both In and
Outbound share the same frame descriptor.

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Figure 26-1 shows how these data structures are related.

Figure 26-1 DMA Data Structure

Queue
Access Frame Descriptors

Head Next Next Next

FControl FControl FControl

FControl FControl FControl

FControl FControl FControl

Buffer BPointer BPointer BPointer

Descriptors
BControl BControl BControl

BPointer BPointer BPointer

BControl BControl BControl

BPointer BPointer

BControl BControl

Data Buffers

26.3 Frame and Buffer Descriptors

Frame descriptors must be aligned on 16-byte boundaries. Buffer descriptors must follow Frame descriptors.
Both the In and Outbound directions may use the same Frame descriptors. Each has its own Buffer descriptors.

NOTE: In this section, some different naming conventions have been inherited.
• IO = I/O Application such as FEC or FFT
• Inbound = Data are moved from Memory to DMA = Mem2Dma = M2D = Transmit = From Memory to
IO = M2IO
• Outbound = Data are moved from DMA to Memory = Dma2Mem = D2M = Receive = From DMA to
Memory = IO2M

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Table 26-1 Mem2Dma (or memory to I/O) Frame and Buffer Descriptor
Bit Name Description
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used
Frame Word1 = FControl0. Offset: x4
31 – 17 Not Used.
16 FACK_N 1: No DMAACK to be asserted at the end of this frame.
15 - 12 IRQTID Reserved for TID
11 - 4 IRQTID Task Done ID number when IRQTDONE is active
3 IRQTDONE IRQ Task Done Enable. Set an interrupt when acknowledging to an external DMAREQ.
2 BRESP_N 1: No waiting for AXI Bresp. Do not care if any AXI write successfully gets to the destination.
1 FPAUSE Pause after finishing this frame. Allow the arbiter to give the AXI bus to another link.
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Frame Word2 = FControl1. Offset: x8
31 – 0 Not used
Frame Word3 = FStatus. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.
30 – 16 Not used
15 – 8 D2MBdesc Zero.
7– 0 M2DBdesc Mem2Dma Number of Bpointer/BControl pairs. Buffer Words always start at offset x10.
Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer.
Buffer Word 1 = BControl. Offset: x14
31 – 24 Reserved. Must be 0.
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Buffer Word 2 = BPointer. Offset: x18
Buffer Word 3 = BControl. Offset: x1C
Buffer Word 4 = BPointer. Offset: x20
Buffer Word 5 = BControl. Offset: x24
Etc..

Table 26-2 Dma2Mem (or from I/O to memory) Frame and Buffer Descriptor
Bit Name Descriptor
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used

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Table 26-2 Dma2Mem (or from I/O to memory) Frame and Buffer Descriptor (Continued)
Bit Name Descriptor
Frame Word1 = FControl0. Offset: x4
31 – 17 Not Used.
16 FACK_N 1: No DMAACK to be asserted at the end of this frame.
15 - 12 IRQTID Reserved for TID
11 - 4 IRQTID Task Done ID number when IRQTDONE is active
3 IRQTDONE IRQ Task Done Enable. Set an interrupt when acknowledging to an external DMAREQ.
2 BRESP_N No waiting for AXI Bresp. Do not care if any AXI write successfully gets to the destination.
1 FPAUSE Pause after finishing this frame. Allow the arbiter to give the AXI bus to another link.
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Frame Word2 = FControl1. Offset: x8
31 – 0 Not used
Frame Word3 = FStatus. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.
30 – 16 Not used
15 – 8 D2MBdesc Dma2Mem (from I/O to memory) Number of Bpointer/BControl pairs. Buffer Words always
start at offset x10
7– 0 M2DBdesc Zero.
Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer.
Buffer Word 1 = BControl. Offset: x14
31 – 24 Reserved. Must be 0.
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Buffer Word 2 = BPointer. Offset: x18
Buffer Word 3 = BControl. Offset: x1C
Buffer Word 4 = BPointer. Offset: x20
Buffer Word 5 = BControl. Offset: x24
Etc..

Table 26-3 Common, or 1, Frame and Buffer Descriptor for Both Mem2Dma and Dma2Mem (FCOM)
Bit Name Description
Frame Word0 = FNext. Offset: x0
31 – 4 FNext Frame Next Pointer. 0 means this frame is the last frame to be processed.
3–0 Not used
Frame Word1 = FControl0. Offset: x4
31 – 17 Not Used.
16 FACK_N 1: No DMAACK to be asserted at the end of this frame.

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Table 26-3 Common, or 1, Frame and Buffer Descriptor for Both Mem2Dma and Dma2Mem (FCOM)
Bit Name Description
15 - 12 IRQTID Reserved for TID
11 - 4 IRQTID Task Done ID number when IRQTDONE is active
3 IRQTDONE IRQ Task Done Enable. Set an interrupt when acknowledging to an external DMAREQ.
2 BRESP_N No waiting for AXI Bresp. Do not care if any AXI write successfully gets to the destination.
1 FPAUSE Pause after finishing this frame. Allow the arbiter to give the AXI bus to another link.
0 IRQEN IRQ enable. Set a level interrupt when DMA completes this frame or if the FDONE bit of this
frame is on.
Frame Word2 = FControl1. Offset: x8
31 – 0 Not used
Frame Word3 = FStatus. Offset: xC
31 FDONE Done a DMA transfer. Set by Hardware when a frame is completed. If this bit is 1 when the
Hardware reads this descriptor and Register DONOSTOP = 0, no transfer happens and the
frame is completed. If DONOSTOP = 1. DMA will happen.
30 – 16 Not used
15 – 8 D2MBdesc Dma2Mem Number of Bpointer/BControl pairs. Buffer descriptors start at offset x10 + 8 *
M2DBdesc.
D2MBdesc + M2DBdesc = 8 maximum if Register FSYN = 1.
7– 0 M2DBdesc Mem2Dma Number of Bpointer/BControl pairs. Buffer descriptors always start at offset x10.
D2MBdesc + M2DBdesc = 8 maximum if Register FSYN = 1.
Mem2Dma Buffer Word 0 = BPointer. Offset: x10
31 – 0 BPOINTER Address pointer of a data buffer.
Mem2Dma Buffer Word 1 = BControl. Offset: x14
31 – 24 Reserved. Must be 0.
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Mem2Dma Buffer Word N = BPointer. Offset: x10 + N*4 (N = even integer)
Mem2Dma Buffer Word N+1 = BControl. Offset: x14 + N*4 (N = even integer)
…..
Dma2Mem Buffer Word 0 = BPointer. Offset: 8 * M2DBdesc + x10
31 – 0 BPOINTER Address pointer of a data buffer.
Dma2Mem Buffer Word 1 = BControl. Offset: 8 * M2DBdesc + x14
31 – 24 Reserved. Must be 0.
23 – 0 BLEN Number of bytes to be transferred. Maximum: 16 Meg – 1 bytes.
Dma2Mem Buffer Word M = BPointer. Offset: 8 * M2DBdesc + x10 + M*4 (M = even integer)
Dma2Mem Buffer Word M+1 = BControl. Offset: 8 * M2DBdesc + x14 + M*4 (M = even integer)

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Table 26-4 Mem2Dma Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus. Offset: x8
30 - 0 No change.
Frame Word3 = FStatus. Offset: xC
31 FDONE = 1 if Register DONOSTA = 0 and when this frame is completed. Else no change.
30 - 16 No change.

Table 26-5 DMA2Mem Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus. Offset: x8
31 – 0 STATUS I/O Status bit[31:0] if Register IOSTATUS = 1. Else no change.
Frame Word3 = FStatus. Offset: xC
31 FDONE = 1 if Register DONOSTA = 0 and when this frame is completed. Else no change.
30 – 16 STATUS I/O Status bit[46:32] if Register IOSTATUS = 1. Else no change.

Table 26-6 Common Frame Descriptors Changed by Hardware

Bit Name Description
Frame Word2 = FStatus. Offset: x8
31 – 0 STATUS = I/O Status bit[31:0] if Register IOSTATUS = 1. Else no change.
Frame Word3 = FStatus. Offset: xC
31 FDONE = 1 if Register DONOSTA = 0 and when this frame is completed. Else no change.
30 – 16 STATUS = I/O Status bit[46:32] if Register IOSTATUS = 1. Else no change.

26.4 DMA Operation

26.4.1 Design Notes

FCOM is the common Frame descriptor for both in and outbound. But in and outbound transfers are independent.
FSYN is much like FCOM but only 8 bpointer/bcontrols are allowed. A DMA operation completes when both in and
outbound transfers complete.
When using FCOM, the outbound transfer may complete before the inbound and will set FDONE. That FDONE
may cause a misinterpretation for the inbound.
FCOM is used when the FHEADs of both in and outbound are the same.

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26.4.2 DMA Interrupt

The IRQEN bit in a Frame descriptor and the IRQFDON bit in the configuration register cause equivalent effects.
The IRQFDON is static and set by APB bus.
DMA generates two separate IRQ signals: IRQMEM2DMA and IRQDMA2MEM. This method gives flexibility on
monitoring both the In and Outbound transfers.
When using FCOM (common frame descriptors), IRQEN bit appears in one descriptor will be seen by both In and
Outbound DMA engines. Both IRQ signals will be generated. Software may only want to know the DMA2MEM
interrupt. But in some cases (for example, debugging), Software may want to see MEM2DMA interrupt as well.
To know what causes IRQMEM2DMA, read offset 014 and 310.
To know what causes IRQDMA2MEM, read offset 114 and 310.

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27 Internal Boot ROM (IBR)
Implementing Secure Boot
This chapter describes the IBR related information, for example, boot mode and eFuse.

27.1 Feature List

• Four instances of 4096-word by 32-bit memory
• Diffusion-programmable one-transistor cell storage array with fully static memory circuitry
• AMBA APB bus interface ready

27.2 IBR Overview

This section specifies the workings of the IBR for the Transcede 2xxx device. The Transcede 2xxx has two Stage
booting:
1. 1st Stage – IBR
2. 2nd Stage – Microloader / U-Boot
After power on Reset IBR works as First stage Boot Loader. The IBR copies the Microloader / U-Boot from the
selected Boot Device. The following options for Boot Devices are supported. Selection is done from the Boot Strap
Register.
• SPI Boot
• I2C Boot
• NOR (8 Bit / 16 Bit) Boot

27.3 Transcede 2xxx Boot Mode

The Transcede 2xxx IBR supports the following boot modes:
• Internal Boot Non Secure boot mode—This is a normal boot mode as explained above where two stage
booting will take place, but no security will be involved.
• Internal Boot Secure boot mode—This is a secure boot mode where two stage booting will take place, and all
the boot images (Microloader / U-Boot / Linux) will get authenticated using Security Engine.

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27.4 Clock and Frequency Options

The Transcede 2xxx supports the following eight clock options in IBR. Clock options are selected from Bootstrap
register.
• 19.2 MHz Ref Freq in PLL Bypass mode
• 25 MHz Ref Freq in PLL Bypass mode
• 26 MHz Ref Freq in PLL Bypass mode
• 40 MHz Ref Freq in PLL Bypass mode
• 19.2 MHz Ref Freq in PLL Enabled mode.
• 25 MHz Ref Freq in PLL Enabled mode.
• 26 MHz Ref Freq in PLL Enabled mode.
• 40 MHz Ref Freq in PLL Enabled mode.

Table 27-1 Extended Boot Option Bits – Clock Option

BIT[22:20] Outcome
000 19.2 MHz PLL Bypass Mode
001 25 MHz PLL Bypass Mode
010 26 MHz PLL Bypass Mode
011 40 MHz PLL Bypass Mode
100 19.2 MHz PLL Enabled Mode
101 25 MHz PLL Enabled Mode
110 26 MHz PLL Enabled Mode
111 40 MHz PLL Enabled Mode

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27.5 IRAM Memory Layout

Below Figure 27-1 explains the memory layout of 256K IRAM memory:
• Top 10KB space is reserved for IBR stack.
• After IBR stack 6KB area is reserved for IBR Data segment.
• Starting 240K of memory area is reserved to store SBL / U-Boot.
Figure 27-1 IRAM Layout

Offset – 0x40000

IBR Stack 10K

Offset – 0x3D800

IBR Data Segment

6K

256K ARAM Memory

Offset – 0x3C000

Memory reserved to store

240K
SBL (or U-Boot)

Offset – 0x0000

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27.6 Boot Header

The image header will reside on top of the boot Image. Figure 27-2 and Table 27-2 explain different fields of Boot
Image header.
Figure 27-2 Boot Image Header

Magic number
0x4D535044

Timestamp creation

CRC

Key length

Image Hash type

Image Length

Hash value (256bit)

Public key (0, 1024,2048 bits)

Table 27-2 Boot Image Header Fields Description

Boot Image Header Fields Description
Magic Number Fix string " MSPD - 0x4D535044 "
Timestamp Image creation timestamp
CRC 32 Bit CRC on full header. At the time of CRC calculation this field should be 0.
Polynomial used is x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2
+x+1
Image Hash Type Hash Type 0/Sha-256/Rsa-Sha-256.
• Zero -- Initialized with all zero.
• SHA-256 - SHA-256 hash on the image.
• RSA-SHA-256 - RSA encrypted sha-256 hash on the image.
Key Length Length of Public Key 0/1K,2K. Zero means no key
Image Length Length of Current Image (excluding header)
Hash value Hash result 256 bits
Public key (optional) Public key used for firmware authentication (Size 1K/2K)

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27.7 Transcede 2xxx Boot Options

The IBR reads Bootstrap and Bonding options from “Strap Pin And Boot Control Register (Base Address:
0xF4C0_8000)“ from the Secure Configuration Registers space.
The IBR main code call the init function for the selected boot device and register the driver read routine in IBR
Context.

NOTE: See Table 2-1, Transcede 2xxx Boot Options, on page 30 for boot options.

27.8 Extended Boot Option

The Transcede 2xxx IBR supports SPI devices supporting 2 byte, 3 byte and 4 byte address cycle, as shown in
Table 27-3.

Table 27-3 Extended Boot Option Bits – SPI Address Length

BOOT_OP[18:17] Outcome
00 N/A
01 2 Byte Address
10 3 Byte Address
11 4 Byte Address

The Transcede 2xxx IBR supports SPI devices supporting both polarities for serial clock, as shown in Table 27-4.

Table 27-4 Extended Boot Option Bits – SPI SC Polarity

BOOT_OP[19] Outcome
0 -ve
1 +ve

The Transcede 2xxx IBR supports two clock freq options, as shown in Table 27-1.
If Debug mode is enabled - Bit0 of eFuse ID Byte-1, then Secure Boot Option will be derived from this bit, as shown
in Table 27-5.

Table 27-5 Extended Boot Option Bits – Secure Boot Opt

BIT[23] Outcome
0 Disable
1 Enable

27.9 Transcede 2xxx eFuse

EFuse block will be used in the Transcede 2xxx for IBR boot options and security configurations.
eFuse instance #0, eFuse ID, will be used for configurations and the 53-eFuse instances will be used for Security
Keys ~6.5Kbits.

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48-bits are required for device unique CID (lot#, wafer# and X-Y coordinates), thus rest of the eFuse ID bits are
divided into Configuration bits, Bonding option bits and Secure bits.
The following diagram illustrates the “eFuse ID” decoding fields.
Figure 27-3 eFuse ID

bit 0 bit 32 bit 64 bit 127

Unique Device CID
31-bits Configs Sec Bit RSVD
(48-bits) + 16-bits Reserved

Figure 27-4 explains the layout of eFuse area.

Figure 27-4 eFuse Layout

BIT-0 BSCANMODE
0 Not Blocked
BIT 0 - BSCANMODE 1 Blocked

BIT 1 – Trustzone BIT-1 Trustzone

0 Enabled
BIT 2 - JTAG 1 Disabled
eFuse ID BIT 3 - Reserved
Byte-0 BIT
Definitions BIT 4 - Reserved BIT-2 JTAG
0 Not blocked
BIT 5 - Reserved 1 Blocked
BIT 6 - Reserved

BIT 7 - Reserved BIT-0 Debug Mode

0 Enabled
eFuse ID Byte - 0 1 Disabled
eFuse ID
D Byte - 1
eFuse BIT-1 Authentication
eFuse ID Bit 31-secure enable BIT 0 – Debug Mode
Instance-0 0 Disabled
Rest of the eFuse ID BIT 1 – Authenticate Boot Code 1 Enabled

BIT 2 – Key Size 0 BIT-3 BIT-2 Key Size

eFuse Read once per boot eFuse eFuse ID BIT 3 - Key Size 1 0 0 N/A
Instance-1 block Byte-1 BIT 0 1 1K
Definitions BIT 4 – Reserved 1 0 2K
1 1 N/A
Last time program eFuse BIT 5 - Reserved
eFuse block
Instance-2 BIT 6 - Reserved
Disable debug/global byte15 BIT 7 - Reserved

eFuse Disable external pin access

832 Bytes eFuse block
eFuse Address Instance-3 BIT 0 – Reserved
Space BIT-4 TEST Features
BIT 1 – Reserved 0 Enabled
1 Disabled
eFuse BIT 2 – Reserved
Disable
debug BIT 3 - Reserved
Non invasive
Global BIT-5
BIT 4 – TEST Features debug
Space to Store Public Key/ Byte 15 0 Enabled
eFuse Hash on Public Key / other BIT 5 - Non invasive debug 1 Disabled
Instance purposes
No 4 to 51 BIT 6 – Invasive debug
BIT-6 Invasive debug
BIT 7 – Global last time program 0 Enabled
1 Disabled

Global lasttime
BIT-7
program
0 Enabled
1 Disabled

Out of 53 instances, the first instance is used for eFuse ID.

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eFuse ID Byte-0 and Byte-1 are used secure-boot configuration options.

In the Transcede 2xxx before ARM Cortex A9 comes out of reset, auto sense of all the eFuse instances is
performed. In the IBR code there is no need to perform full read sequence for eFuse instances. After autosense all
the 16 Byte of data of each eFuse gets latched into the DOUT registers of each eFuse instance. An eFuse Status
Register (offset - 0xFE0F0044) is provided. On completion of autosense operation bit zero of this register will
become '1'.

27.9.1 eFuse Operations

The eFuse block has two main operations: Program and Sense. It also has the option to do sense operation on
each eFuse block automatically after reset in case 'auto_sense' bootstrap is set. At the end of the operation the last
eFuse block DOUT will be selected to output.
eFuse is controllable through software, however, in order to do that 'auto_sense' input needs to be reset to zero.
The control is done by configuring internal registers that drive the block's inputs through the APB interface.
FSOURCE inputs are pin controlled, and connect to efuse instance in a Round-Robin fasion. FSOURCE_0
connects to eFuse instances 0, 3, 6, ..., 51; FSOURCE_1 connects to eFuse instances 1, 4, 7, ..., 49;
FSOURCE_ID connects to eFuse instances 2, 5, 8, ..., 50.

27.9.2 eFuse Sense Operation

1. The eFuse Sense operation needs to be done on each eFuse block sequentially and not in parallel.
2. In order to select which eFUSE block is worked on, the 'inst_cnt' register needs to be configured with the block
number that we want to do the operation on.
3. After the operation is done, the eFuse data will be valid on DOUT output. This output can be read through APB.

27.9.3 eFuse Program Operation

1. The eFuse Program operation needs to be done on each eFuse block sequentially and not in parallel.
2. In order to select which eFuse block is worked on, the 'inst_cnt' register needs to be configured with the block
number that we want to do the operation on.
3. In case more than one FSOURCE input, the correct FSOURCE needs to be driven in order to program a
certain eFuse block.

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28 Interrupts, Timers, Clock and Reset
This chapter describes the interrupts, timers, clocking scheme and reset function:
• Interrupts
• Timers
• Clock
• Reset

28.1 Interrupts
The Transcede 2xxx provides the following categories of interrupts:
• CevaXC Interrupts
• Cortex-A9 MPCore (Dual ARM) Interrupts

28.1.1 CevaXC Interrupts

Each CevaXC has three interrupt inputs:
• Inter-processor interrupt (IPI): The IPI is used for processor communication among two CevaXC processors
and from ARM processor to Ceva. INT0 pin of the Ceva is used for the IPI interrupt.
• Non Mask-able Interrupt (NMI): The NMI is used for debugging and core dump interrupt of Ceva processors.
NMI pin of the Ceva is used for this interrupt.
• Break Point Request (BP): The BP Request is used for break point of Ceva OCEM module. Ext_bp1_reg pin of
the Ceva is used for this purpose.
The generation of these CevaXC Interrupts is accomplished through Ceva APB register write.
The base address of the Ceva Interrupt Controller (INTC_Ceva) is 0xF0D2_0000.

28.1.2 Cortex-A9 MPCore (Dual ARM) Interrupts

The Transcede 2xxx features one Cortex-A9 MPCore with two ARM cores, Generic Interrupt Control unit (GIC) and
General Timer block. Each Cortex-A9 core has 128 Shared Peripheral Interrupt (SPI) IRQS input pins. Dual-ARM’s
IRQS pins are mapped to the same interrupt signals from various modules of the system; so the interrupt from any
module can be routed to any of the two ARM cores through the software configuration.

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Table 28-1 Dual ARM External IRQS Assignments

IRQS Interrupt Signal Note
0 PTP0_IRQ Processor to Processor Interrupt (set under firmware control) – Set via register at
offset 0x9C and clear at 0x98
1 PTP1_IRQ
2 reserved
3 reserved
4 A9_L1_PAR_IRQ A9 L1 Parity Fail Interrupt
5 reserved
6 reserved
7 reserved
8 arm2_L2_irq Dual ARM L2 cache
9 reserved
10 A9_PMU0_IRQ A9 PMU CPU0 Interrupt
11 A9_PMU1_IRQ A9 PMU CPU1 Interrupt
12 fec_dnl_irq[0] FEC DL irq0
13 fec_dnl_irq[1] FEC DL irq1
14 fec_upl_irq[0] FEC UL irq0
15 fec_upl_irq[1] FEC UL irq1
16 spacc_irq[0] SPAcc Wireless Accelerator irq0
17 spacc_irq[1] SPAcc Wireless Accelerator irq1
18 espah_irq IPSec Accelerator
19 saspa_irq SaSPA Accelerator
20 ddr_ctrl_irq DDR Controller
21 reserved
22 mdmasys0_irq[0] MDMA_SYS0 irq0
23 mdmasys0_irq[1] MDMA_SYS0 irq1
24 mdmasys1_irq[0] MDMA_SYS1 irq0
25 mdmasys1_irq[1] MDMA_SYS1 irq1
26 reserved
27 reserved
28 reserved
29 reserved
30 ceva2arm_irq[0] Ceva 0 output (ceva_gpout0) pin
31 ceva2arm_irq[1] Ceva 1 output (ceva_gpout0) pin
32 reserved
33 reserved
34 reserved
35 reserved
36 reserved

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Table 28-1 Dual ARM External IRQS Assignments (Continued)

IRQS Interrupt Signal Note
37 irq_tz_timer
38 iirq_bpdma0_mem2dma
39 irq_bpdma0_dma2mem
40 irq_bpdma1_mem2dma
41 irq_bpdma2_mem2dma
42 irq_bpdma3_mem2dma
43 irq_cvcomb2arm
44 irq_fpdma_m2map MAPDMA 0 outbound
45 irq_fpdma_map2m MAPDMA 0 inbound
46 c2c_dist_irq[0] cluster2cluster irq
47 c2c_dist_irq[1]
48 fp2arm_irq MAP to ARM (combined)
49 reserved
50 cpri_irq CPRI Controller (for Transcede 2120/2150/2200)
51 reserved
52 reserved
53 cpdma_tx_irq CPDMA TX IRQ (for Transcede 2120/2150/2200)
54 cpdma_rx_irq CPDMA RX IRQ (for Transcede 2120/2150/2200)
55 reserved
56 irq_tdone2arm[0]
57 irq_tdone2arm[1]
58 irq_tdone2arm[2]
59 irq_tdone2arm[3]
60 irq_tdone2arm[4]
61 irq_tdone2arm[5]
62 irq_tdone2arm[6]
63 irq_tdone2arm[7]
64 irq_crp_err CRP Error Indication (for Transcede 2120/2150/2200)
65 irq_syncnet2arm Sync Net IRQ
66 irq_iqcntr2arm[0] IQ Counter IRQ0
67 irq_iqcntr2arm[1] IQ Counter IRQ1
68 irq_iqcntr2arm[2] IQ Counter IRQ2
69 irq_iqcounter_ovf IQ Counter Overflow
70 reserved
71 reserved
72 Pcie_x1_irq
73 Pcie_x4_irq
74 Pcie_x4_dma_irq

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Table 28-1 Dual ARM External IRQS Assignments (Continued)

IRQS Interrupt Signal Note
75 reserved
76 rad_timer_irq[0] Radio Interface FSYNC Timers, FSYNC IRQ
77 rad_timer_irq[1] Radio Interface FSYNC Timers, CHIP IRQ
78 rad_timer_irq[2] Radio Interface FSYNC Timers, SLOT IRQ
79 rad_timer_irq[3] Radio Interface FSYNC Timers, FRAME IRQ
80 reserved
81 reserved
82 reserved
83 reserved
84 jesd0_irq RPDIF0 (JESD207) Interrupt
85 jesd0_dplane_irq
86 jesd1_irq RPDIF1 (JESD207) Interrupt
87 jesd1_dplane_irq
88 jdma0_tx_irq JESD0 DMA Transmit Interrupt
89 jdma0_rx_irq JESD0 DMA Receive Interrupt
90 jdma1_tx_irq JESD1 DMA Transmit Interrupt
91 jdma1_rx_irq JESD1 DMA Receive Interrupt
92 e0mx_gemirq
93 e0mx_gemirq1
94 e0mx_gemirq2
95 e0mx_gemirq3
96 usim_irq USIM Interrupt
97 usb_irq USB2.0 Interrupt
98 e1mx_gemirq
99 e1mx_gemirq1 GEMCORE 0
100 e1mx_gemirq2 GEMCORE 1
101 e1mx_gemirq3
102 tsu_ntg_irq NTG for Ethernet 1588
103 reserved
104 gpio_irq[0] GPIO pin 0
105 gpio_irq[1] GPIO pin 1
106 gpio_irq[2] GPIO pin 2
107 gpio_irq[3] GPIO pin 3
108 gpio_irq[4] GPIO pin 4
109 gpio_irq[5] GPIO pin 5
110 gpio_irq[6] GPIO pin 6
111 gpio_irq[7] GPIO pin 7
112 timer_irq General Purpose Timers

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Table 28-1 Dual ARM External IRQS Assignments (Continued)

IRQS Interrupt Signal Note
113 timer_tdm_irq TDM FSYNC Timer
114 uart0_irq UART 0 (DMA)
115 uart_s_irq UART 1 (Slave)
116 spi0_irq SPI0 Controller (DMA)
117 spi_s_irq SPI1 Controller (Slave)
118 dus_irq from DUS block (SPI/UART – DMA)
119 i2c_s_irq I2C Controller (Slave)
120 tdm_ntg_irq NTG for TDM
121 tdma_tdtxchk_irq[0] TDMA TX Transfer Count (TDM0)
122 tdma_tdtxchk_irq[1] TDMA TX Transfer Count (TDM1)
123 tdma_tdrxchk_irq[0] TDMA RX Transfer Count (TDM0)
124 tdma_tdrxchk_irq[1] TDMA RX Transfer Count (TDM1)
125 tdma_errtdtx_irq TDMA TX Bus Error
126 tdma_errtdrx_irq TDMA RX Bus Error
127 tdma_2tdma_irq TDMA Receive buffer full, Transmit buffer empty, Receive Overrun, and Transmit
Underrun.

28.2 Timers

28.2.1 Feature List

The Advanced Peripheral Bus (APB) timer module includes the following types of timers:
• General Purpose Timers
– Three 32-bit timers (timer0, timer2, timer3) providing glitch-less pulses to the interrupt controller
– One 30-bit timer (timer1) used to provide interrupts
– Two interrupts (timer_irqa and timer_irqb) that can be programmed from one or more of the four timer
pulses
– A secondary interrupt status register to indicate which of the timers had issued a pulse
• TDM Frame Sync Timers
– Eight 16-bit TDM timers driven by TDM frame sync timing, providing glitch-less pulses to the interrupt
controller.
• Two TDM Rx FrameSync timers
• Two TDM Tx FrameSync timers
– One TDM timer interrupt can be programmed from one or more of the eight timer pulses
– A secondary TDM timer interrupt status register to indicate which of the timers had issued a pulse
• Watchdog Timer
– One 32-bit watchdog timer driven by AHB clock, providing glitch-less level hard reset to the reset block.
Watchdog Timer is controlled by the two registers listed in Table 28-2.

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Table 28-2 Registers Controlling Watchdog Timer (Base Address = 0xFE05_0000)

Offset Bits R/W Default Description
0xFE05_00D0 bits[31:0] R/W 0x00000000 Watchdog Timer Max Count, also a write to this register starts the count
from beginning.
0xFE05_00D4 bits[9:0] R/W 0x00000000 Watchdog Timer Enable.
Bit[1:0] = 00, disable reset and Watchdog Timer count.
Bit[1:0] = 01, enable reset to ARM0 when Watchdog Timer timeout.
Bit[1:0] = “10”, enable reset to ARM1 when Watchdog Timer timeout.
Bit[1:0] = “11”, enable reset whole chip
Bit[7:2], Reserved
Watchdog Timer Reset Status (read only):
Bit[8] = 1, Watchdog Timer has sent a reset to ARM0.
Bit[9] = 1, Watchdog Timer has sent a reset to ARM1.

28.2.2 Functional Description

Figure 28-1 Individual Timer Block Diagram

hclk

APB
timeout
32bit Register 32bit Up Counter

There are four general-purpose timers in the timer block. Each timer consists of two sections, a register and a
count-up counter. The register is loaded on the rising edge of pstbn when selected. The counters are loaded on the
rising edge of hclk one cycle after the registers are loaded or when the counters reach zero. Otherwise, the count-
up counter is incremented on the rising edge of hclk.

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Figure 28-2 Timer Top-level Block Diagram

IRQ_MASK

Timeout0 TIMER_IRQA (Pulse)

Timer0

Timeout1
Timer1 Status

Timeout2 TIMER_IRQB (level)

Timer2 Status

Timeout3
Timer3 Status

The IRQA and IRQB mask registers are used to selectively enable the timerout pulses to generate the IRQA and
IRQB interrupts. An interrupt status register in the timer block can be read to check which of the timers had
generated a timeout.

28.2.3 Radio Frame Synchronization Timers

The main function of the Radio Frame Timers is to trigger events (or interrupts) at selected times within Radio
Frames, starting upon detection of an external pulse (Frame Sync for example), or anytime under software control.
Additionally, the Timers can also be used to generate a periodic pulse, with manually adjustable phase and
frequency.
A radio frame's length is 10 ms, the start of which is indicated by a Frame Sync pulse. A frame is composed of 15
or 20 Slots of 0.667 ms or 0.5 ms respectively depending on the frame format. Each Slot is divided into Chips, and
each Chip is divided into Sub-Chips. A Super-Frame is a collection of frames.
Figure 28-3 Example Frame Formats

2560 chips

One radio frame, Ti = 307200Ts= 10 ms

DATA
One slot, Tslot = 15360Ts = 0.5 ms

PILOT TFCI FBI TPC #0 #1 #2 #3 ………... #18 #19

One subframe

0 1 2 3 ... 14

10 ms
WCDMA LTE

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Events can be set to trigger at any Chip and/or Slot within a frame, and/or when a certain number of frames or
super-frames have been reached.
As an example application, timers can be connected to a CPRI controller, which asserts a Frame Synchronization
indication (FSync) at the beginning of each frame received or transmitted. If enabled, the timers will start the
counting process once an FSync is detected, and events are generated at the desired chip, slot, frame, and super
frame locations until the timers are disabled. Event generation can be selected to start after a certain count had
elapsed (or offset) for each of the chip, slot or frame counters. Counter values for chip, slot, frame and super frame
can also be read by software for debug or statistics purposes.
In other application, the Timer can be used to generate a Frame Sync indication to drive Radio controllers. Based
on the controller clock rate, the timer can be programmed to generate a periodic 10ms pulse, which can be slewed
by software as a manual adjustment if needed. The pulse generation can start under software control, or at the
detection of an external sync pulse, like a GPS 1 pps pulse.

28.2.3.1 Feature List

• A total of 6 Timers shall be available for event generations. The events trigger interrupts at programmable
points during a frame or super-frame. These timers shall be referred to FSync Timers.
• Additional three timers (referred to as ESync Timer) shall be used for generation of three independent Frame
Sync pulses, to synchronize the radio controllers. The pulse target frequency is 10 ms. Interrupts are also
generated at select times within the frame.
• Each Timer shall be assigned to any one of the following clocks: 2 RF clocks (MCLK0 and MCLK1), CPRI
clock, CPRI RX, CPRI TX, External clock, or AXI clock. Each timer shall be assigned to a clock and sync pair
with no restriction.
• Software control to enable counters when a Frame Sync is not connected. Timers operation can be triggered
by software, bypassing the Frame Sync detection logic.
• Each Timer shall have a basic counter for clock rate division, a chip counter, slot counter, frame counters and
super-frame counters for event generation.
• Counters and event generation logic shall toggle between two sets of configuration values, switching from one
to the other each count iteration. This can be used by the software to implement a circular buffer of counter's
terminal count values, to support variable chip and slot sizes within a frame.
• Ability for the Software to load initial values (or count offset) into the counters before the start of operation, and
on-the-fly when Terminal Count is reached. This feature can be used to manually adjust the phase location of
the pulse output when time is used as frame sync generator.
• It shall be possible to delay events generation until a certain amount of count (or event offset) has elapsed.
• Events shall be generated when the counter values match their corresponding compare values. Any bit of the
counter can be masked. Masked bits are treated as don't care during the compare process. This feature can be
used to trigger events at multiple chips/slots/frame locations.
• Events can be disabled or enabled selectively for each timer, per slot, chip, frame and super-frame.
• Support for 4 independent interrupt controllers (or CPUs), with flexibility to program each timer to interrupt one
or more of the 4 CPUs.
• Generated output pulses should be monitored on a GPIO for debug purposes.
• A clock divider is added for input clock pre-scaling if needed.
• Offset values for the three timers (chip, slot, frame, and super-frame) can work independently, or combined to
form a single location within a certain frame.
• Events can trigger independently, or be combined to indicate a single location within a certain frame.
• Error indication when an event is generated before the previous one has been cleared.
• Glitch-less switching between clock sources.
• Support for synchronous or asynchronous Frame Sync input signal (goes through two stage registers).

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• Counters hold to freeze operation.

• Read operation of counter values.

28.2.3.2 Limitations
The clocking limitations are listed as below:
• Back-to-back writing to APB registers is not allowed before the previous write data has been transferred to the
counter clock domain (6 clock cycles of APB clock, plus 3 cycles of counter clock). Interrupt control register
does not have this limitation because of its potential higher access rate.
• The FSync Timer block needs to be reseted if its selected clock source is stopped (LOS condition for example).
Switching to another clock will not be possible since a glitch-less mux is used.
• For counter value read operation, it is necessary to wait for the counter select bits to propagate from APB clock
domain to the counter clock domain before the read operation can be initiated. That will be about 3 APB + 3
Counter clocks. Otherwise read value can be of the previously selected counter.
• A delay of 15 counter clocks are needed between the de-assertion of the block reset (configuration bit) and the
next access to the block registers or block operation. This is because the internal reset delay due to the reset
synchronization scheme.
When used as pulse generator, positive phase slewing pulse (pulse delay) is possible only if the Terminal Count is
less than the counter overflow value.

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28.2.3.3 Functional Description

28.2.3.3.1 Top Level Diagram

Figure 28-4 Radio Timers Top Level Diagram

Radio Group
Radio Timers
Esync0 Intrpt Timer0 Clk

10ms Fsync0 Timer0 Sync Timer Interrupt

Chip Interrupt
FBCLK0 ESync0 Timer1 Clk Chip Error
RPDIF0
Timer Timer1 Sync
Frame Slot Interrupt
MCLK0 Sync Slot Error
Timer2 Clk Timer
No. 0 Frame Interrupt
1pps pulse Timer2 Sync
Frame Error

Timer3 Clk SFrame Interrupt

MCLK1 SFrame Error

Timer3 Sync

ESync1
RPDIF1 Timer4 Clk
FBCLK1 Timer
Timer4 Sync
APB Interface
10ms Fsync1
MUX Timer5 Clk
Esync1 Intrpt
Timer5 Sync
Esync2 intrpt

10ms Fsync Pulse SFrame Error

1pps SFrame Interrupt

pulse ESync2
Timer Frame Error
Frame Frame Interrupt
cpri_clkx Sync
CPRI
txclk Timer Slot Error
tx_fsync No. 5 Slot Interrupt
rxclk
rx_fsync
Chip Error
Chip Interrupt
Ext Clk
Timer Interrupt
Ext Sync

Axi Clk
GND
Chip Errors[5:0]
APB Config & Status
Slot Errors[5:0]
Interface Registers
Frame Errors[5:0]
Super Frame
Errors[5:0]
Super Frame CPU interrupt[3:0]
Frame CPU interrupt[3:0] Super Frame
Interrupts[5:0]
Slot CPU interrupt[3:0] Frame
Chip CPU interrupt[3:0] Interrupts[5:0]
Interrupt
Timer CPU interrupt[3:0] Slot
Masking Interrupts[5:0]
Super Frame interrupt Logic
Chip
Frame interrupt Interrupts[5:0]
Slot interrupt
Chip interrupt Timer
Interrupts[5:0]
Timers interrupt

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28.2.3.3.2 System Operation

Three pulse generation timers (ESync Timers) generate 10 ms pulses (FSync) for the two RF and one CPRI
controllers. The pulses will be in phase with the GPS generated 1pps, and 100 pulses will be generated between 2
successive pps. These timers can be started by software in case the pps is not connected.
The output pulse is generated by the same event that triggers the interrupts, and can be selected to be driven by
the slot, frame or super frame event generator. Interrupts are routed from the ESync timers to CPU, and can be
used similarly to the Frame Sync Timers interrupts.
The Frame Sync can be slewed by software by a selected chip or slot number, using the counter’s initial value load
operation. Pulse generation can be programmed to trigger at mid-way the counter overflow value, so that slewing
up and down can be possible by loading corresponding initial values on-the-fly. For example, if the Terminal Count
(TC) is set to 2, loading an initial value of 3 will delay the event by 1, while an initial value of 1 will pull it in by 1.
Figure 28-5 below shows the effect of positive and negative phase shift of the Frame Sync pulse.
Figure 28-5 Frame Sync Pulse Phase Shift Waveform

Init = 1 Init = Overflow

Chip
Slot Slot0 Slot1 Slot0 Slot1 Slot0 Slot1 Slot0

Frame Frame0 Frame1 Frame2 Frame3

FSync

Each of the 6 available event timers is assigned to one of the 2 RFs and CPRI interfaces, and to either the RX or Tx
lanes. An external clock source and corresponding frame sync are available as well, which can be used for test
mode or to support an external CPRI interface.
Interrupts from all timers are aggregated to form four interrupts: one dedicated for chip interrupt, one for slot, one
for frame, and one for super-frame, and one for the logic ORing of the three of them. Each of the four interrupt
outputs can be enabled or disabled separately.
Four sets of interrupts are routed to 4 different CPUs. Each of the 4 CPUs can be configured to be interrupted by
one or multiple timers out of the 6 available, forming a 6 to 4 switch matrix, with no restrictions.

28.2.3.3.3 FSync Timers

The FSync timer is assigned to a certain RF controller lane or to an external source by configuring its pre-scaler's
"clock source" field. The corresponding frame sync indication is selected simultaneously. The selected clock can be
scaled down if needed, and it drives all the synchronous logic in the block.
Each Timer contains four counters, all driven by the same clock:
• Basic Counter: Regulates the clock to the Chip rate (its TC condition is used as clock enable for the Chip
Counter).
• Chip Counter: Performs Chip count and regulates the clock to Slot rate. Increments only when Basic counter
reaches its TC.
• Slot Counter: Performs Slot count and regulates the clock to Frame rate. Increments only when Chip Counter
reaches its TC.
• Frame Counter: Performs Frame count. Increments only when Slot Counter reaches its TC.
• SFrame Counter: Performs Super Frame count. Increments only when Frame Counter reaches TC.

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After the timers are configured, they should be enabled to start operation. If manual start is not enabled, on the first
FSync detected, the counting process starts, and further FSync are disregarded. Each of the three counters
increments until its TC value is reached, at which point, the counting restarts again.
Two values for Terminal Count can be programmed for each of the Chip, Slot and Frame counter, value A and B
respectively. Initially, value A is used, and when TC is reached and the counter restarts, value B will be used, and
so forth. An indication of which value is currently being used is available for each counter as a status bit.
Figure 28-6 Timer Count Operation

Frame cnt Slot cnt Chip cnt Sub-chip

11

11
0

0
3

0
d
Teminal count
TCFrame = 4095
TCslot = 14
TCchip = 2559
TCsubchip = 7

28.2.3.3.4 Event Generation

If enabled, events (or interrupts) are generated when the count value matches a programmed compare value.
Except the Basic counter, all counters can trigger events. Similarly to the TC, two compare values can be
programmed, A & B, and toggling between them is in sync with the TC value.
A masking mechanism gives the ability for one compare value to generate events at 2n values of the counter: any
bit of the compare value can be masked, reducing it to a "don't care" during the comparison process. The number
of matching values becomes 2n, where n is the number of bits masked. For example, masking the LSB of compare
value 0010 will generate events at count values 0010 and 0011.
For each counter, events can be suppressed until the count reaches a programmed offset number. Each counter
can use its corresponding offset independently of the other counters, or offsets can be aggregated and compared
to the aggregate of the three counters, which suppresses events until Frame offset has been met, followed by Slot,
followed by Chip offset (waiting for a specific Chip number, of a specific slot, within a specific Frame).

28.2.3.4 IQ Counter
The IQ counter block monitors the amount of IQ samples being transferred from radio interface (CPRI or JESD) to
internal memory and depending on the preprogrammed count value interrupt a processor.
This block has 7 counters and each counter has associated delay counter before interrupt (int_req_out) is
generated. Figure 28-7 shows the IQ transfer counter top level block diagram.

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Figure 28-7 IQ Transfer Counter Top Level Block Diagram

trans_indicator p3_sel
int_req_out[3:0]
Sync Net p3_penable
int_ack_in[3:0]
p3_pwrite

p3_pwdata[31:0]
IQ GP
Counter p3_paddr[15:0] busmatrix
int_req_out[6:4]
ARM
p3_prdata[31:0]

p3_pready
int_ack_in[6:4]
Sys Config p3_pslverr

28.2.3.4.1 Functional Description

The IQ counter block implements 7 counters to generate 7 independent interrupts based on the IQ samples
transferred from radio interface. The IQ counter uses either trans_indicator input or radio_clk input to count up the
IQ counters. The radio_clk input is a divided down signal from CPRI or JESD radio clock. The counters count the
number of pulses on trans_indicator input and the counter wraps or resets to zero when it reaches the max value
specified in "IQ Transfer Counter Max Value register".
At the rising edge of each trans_indicator input, the low counter is counted up by 1. When the low counter reaches
a programmed max value, it goes to 0 on the next trans_indicator pulse and, at the same time, the high counter is
incremented by 1.
The value of these 2 counters are monitored by the interrupt generator. When the counter matches the value of
"Interrupt Trigger register", it triggers the generation of the interrupt after a delay counter specified in
"Prgmd_delay_cnt register".
"Interrupt Mask register" can be used to enable generation of multiple interrupts throughout one loop of counter. Or
"en_clr_cntr_int_trig" can be set to '1' so the counter is reset on each interrupt generation.
The top registers (addr[11:8] = 0xF) are to control and monitor all the counter modules. To synchronize among
counter modules, both en_counter and fs2en_counter registers can be used:
1. Set the corresponding en_counter bit = '0'.
2. Select either radio_clk or trans_indicator to count up each counter.
3. initialize every parameter in each counter module, including the counter offset.
4. Set the corresponding fs2en_counter bit to '1' so on next FrameSync all those counter modules where
fs2en_counter bit asserted will start running simultaneously.
5. If needed, enable fs2init_counter to init the corresponding counter to the init value whenever the frame_sync is
asserted.
The registers are configured through APB3 interface.

28.2.3.4.2 Timing Diagrams

Figure 28-8 shows the normal case timing diagram. Figure 28-8 and Figure 28-9 show the overflow cases.

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Figure 28-8 Normal Case Timing Diagram

Figure 28-9 Overflow Case Timing Diagram 1

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Figure 28-10 Overflow Case Timing Diagram 2

28.3 Clock

28.3.1 Clocking Scheme Description

The clock generation for the device is done in the top_clk_rst block located in the top level. The top level clock and
reset block instantiates 4 analog PLLs, all sharing one input reference clock. For each clock domain in the device,
the PLLs outputs are muxed and optionally divided down to generate the required clock rate. The output of each
clock divider is split into several branches, to be distributed to blocks that run at the same rate, and each branch is
gated for shut down option. This provides the option to shut down clocks of individual blocks when they are not in
use.
To achieve phase alignment when two or more clock dividers are running in parallel from the same PLL source, an
enable or a sync pulse is sent from the master clock divider to all slave dividers. For example, to achieve a 1:2 and
a 1:4 clocks, a divide by 2 and a divide by 4 can be sourced from the same main clock. This is an alternative to
using cascaded (in series) dividers (1:2 feeding another 1:2) which can complicate timing closure.
The clock generation module also generates the “clock enable” signals required to regulate data flow between
clocks that are multiples but synchronous to each others. Integer and half integer multiples shall be supported, 1:1,
2:3, 1:2, and so on.
For each clock branch, a dedicated reset signal is provided that is controlled by software. The reset generation
circuit sends an indication to the clock generation circuits when the reset is transitioning from asserted to de-
asserted state, a certain clock cycles before and after the transition. The clock circuitry uses this indication to shut
down the clock during that window, to avoid any reset timing violations. This eliminates the need for reset
synchronization and the reset removal timing requirements.

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28.3.2 Reference Clock Definition

The below reference input and operating output clocks for various options are implemented for the analog modules
and system PLLs. Based on the application, the proper reference clock scheme can be selected to reduce the
board’s bill of materials.

Table 28-3 Reference Clock Definition

Ref Ref. Input Core Clock
Optn. # Source Source Type Application Notes
Macro (MHz) (MHz)
PLL0 1 25 PS_XI Pin External Xtal In 1,000 Cortex A9 System clk sync. source
PLL1 1 25 PS_XI Pin External Xtal In 720 Ceva Subsystem Alternative system clk
sync. source
PLL2 1 25 PS_XI Pin External Xtal In 750 FEC_DL Not needed if FEC &CRP
can be timing closed
same as Ceva.
PLL3 1 25 PS_XI Pin External Xtal I 550 CRP/FEC_UL
CPRI PHY 1 153.6 S0_REFCLK Pin Differential Clock In 307.2 6.1G Radio link SerDes0 config as CPRI
(for T2120/ 2 153.6 S1_REFCLK Pin Differential Clock In 307.2 6.1G Radio link SerDes1 config as CPRI
T2150/
T2200)
DDR PHY 1 Internal PLL Clock In 400 1.6G DDR3 DDR PHY is 800MHz to
External
PCIe PHY 1 156.25 S0_REFCLK Pin Differential Clock In 500 5G Gen2 PCIe SerDes0 Config as PCIe
2 156.25 S1_REFCLK Pin Differential Clock In 500 5G Gen2 PCIe SerDes1 Config as PCIe
SGMII PHY 1 156.25 S0_REFCLK Pin Differential Clock In 125 1.25G SGMII SerDes0 config as SGMII
2 156.25 S1_REFCLK Pin Differential Clock In 125 1.25G SGMII SerDes1 config as SGMII
USB PHY 1 12 UP_XI/UP_XO Pins External Xtal In 33 480M USB 2.0 Xtal connected to XI/XO
2 12/19.2/24/48 UP_XO Pin External Clock In 33 Clock connected to XO
3 19.2 PS_XI Pin External Xtal In 33 Share with system refclk
Notes:
• “Clock In” source is an input clock from Internal clock generator.

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Figure 28-11 Clock Muxing Diagram

S1_REFCLKP/M
156. 25 MHz
S0_REFCLKP/M for SGMII/ PCIe Crystal: 12 MHz to UP_XO and
156. 25 MHz for 153. 6 MHz UP_XI PS_XI
PCIe Oscillator: 12/19.2/24/48 MHz
for CPRI 19.2/25/26/40 MHz
to UP_XO only

LVDS LVDS LVDS

XO XI Clockcore PLL0 PLL3
SERDES0 SERDES1 DDR PHY
PLL SE PLL
PLL SE USB2.0 PLLSE

SE = Single Ended Reference clock input pin

LVDS = LV Differential Reference clock input pins

28.3.3 System Clock Definition

Table 28-4 lists the different system clocks, their rates, default states, clock grouping information and any rate
requirements or special considerations needed.

Table 28-4 System Clock Definition

Clock Rate (MHz)
Clock
Clock Sources Clock Groups Clock Requirements
Description
Min Max
CA9 Group
A9 Core Clk 800 1000 PLL0 arm_grp Only clock provided to
CA9_grp
A9 Core Div_en 400 500 PLL0 A9 Core Clk divided by 2
enable
A9 L2 CC Clk 500 1000 PLL0 arm_grp
ACP Clk 400 500 PLL0 arm_grp
CoreSight Clk 200 250 PLL0 arm_grp, axi_grp
A9 TPI Clk 200 250 PLL0 tpi_grp CoreSight trace port
AHB Bus Glb Clk 200 250 PLL0 arm_grp, axi_grp Equal to AXI Clk
AXI Bus Blk Clk[0] 200 250 PLL0 arm_grp, axi_grp
AXI Bus Glb Clk 200 250 PLL0 arm_grp, axi_grp
DAPClk 200 250 PLL0 dap_grp CoreSight debug
CEVA Group
Ceva Clk 720 720 PLL2 ceva_grp

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Table 28-4 System Clock Definition (Continued)

Clock Rate (MHz)
Clock
Clock Sources Clock Groups Clock Requirements
Description
Min Max
Ceva Div_en 360 PLL2 Ceva Clk divided by 2 enable
AXI Ceva Clk 360 360 PLL2 ceva_grp
AHB Ceva Clk 187.5 200 PLL2 ceva_grp
APB Ceva Clk 187.5 200 PLL2 ceva_grp
FFT Clk 800 800 PLL1 fft_grp
FFT Clk Div_en 300 400 PLL1 FFT Clk divided by 2 enable
CRP Clk (for T2120/T2150/ 500 550 PLL3 crp_grp
T2200)
CRP Clk Div_en (for T2120/ 275 PLL1 CRP Clk divided by 2 enable
T2150/T2200)
FEC Group
FEC DL Clk 750 750 PLL2 fec_dl_grp Timing close indep. from Ceva
FEC DL Clk Div_en 375 PLL2 FEC DL Clk divided by 2 enable
FEC UL Clk 450 550 PLL3 fec_ul_grp
FEC UL Clk Div_en 275 PLL3 FEC UL Clk divided by 2 enable
FEC DL BM Clk 300 375 PLL2 fec_dl_grp
FEC UL BM Clk 250 275 PLL3 fec_ul_grp
GEM Group
GEM Tx Clk 125 125 PLL0 gem_tx_grp
GEM NTG 1588 300 500 PLL0 gem_ntg_ref_grp Can be source from any PLL
SPACC Clk 250 400 PLL1 spacc_grp
SASPA Clk 250 400 PLL1 saspa_grp
IPSEC Clk 250 400 PLL1 ipsec_grp
RAD Group
CPRI RX Clk (for T2120/ 307.2 SerDes0/1 cpri_rx_grp Multiplexing between diff.
T2150/T2200) modes
CPRI TX Clk (for T2120/ 307.2 SerDes0/1 cpri_tx_grp Multiplexing between diff.
T2150/T2200) modes
JESD 207 120 External jesd_grp
PCIe PHY Clk 500 SerDes0/1
SGMII Clk 125 SerDes0/1 Multiplexing between diff.
modes
SYSTEM Group
AXI Fabric Clk 200 250 PLL0/PLL1 axi_grp Coupled & divided down from
Ceva or CA9 clock
DDR Clk 800 400 PLL1 ddr_grp PHY gen. x2 & x4
I2C Clk 0.1 3.4 External I2c_grp
SGMII PHY 156.25 External LVDS
SPI Clk 16 External spi_grp

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Table 28-4 System Clock Definition (Continued)

Clock Rate (MHz)
Clock
Clock Sources Clock Groups Clock Requirements
Description
Min Max
TDM NTG Refclk 300 500 PLL0 tdm_ntg_ref_grp
TDM Internal Clk 1.536 16.384 TDM NTG tdm_int_grp
USB PHY Refclk 12 12 External Crystal usb_phy_grp
USB UTMI Clk 33 33 USB PHY utmi_grp

28.3.4 Clock Specifications

Table 28-5 lists the clock specifications.

Table 28-5 Clock Specifications

Clock Duty
Clock Name Description Frequency Tolerance I/O Characteristics Clock Jitter
Cycle
RGMII_REFCLK RGMII SerDes • 125 MHz (for 1Gbps) ± 50 ppm 2.5 V CMOS interface ± 0.8 nsec max (for 45% to 55%
clock v1.3 • 25 MHz (for 100 voltages as defined by 125MHz) (for 125MHz)
Mbps) JEDEC EIA/JESD8-5.
PCB should be 50 Ω ±
15%.
S0_REFCLK_P/M SerDes clock for 156.25 MHz ± 300 ppm Differential with min 3.0 ps RMS from 10 40% to 60%
PCIe v2.0 swing of 0.15 Vpp (PCIe KHz to 1.5 MHz
mode). relative to a 100MHz
clock
For PCB: 100 Ω
differential transmission
line (50 Ω single ended).
Matched differential pair.
Keep traces as short as
possible. AC couple on
PCB (75 nF to 200 nF for
each TX lane)
S1_REFCLK_P/M SerDes clock for 156.25 MHz for PCIe or ± 300 ppm Differential with min 3.0 ps RMS from 10 40% to 60%
PCIe v2.0 or SGMII. swing of 0.15 Vpp (PCIe KHz to 1.5 MHz
SGMII The SerDes has a mode). relative to a 100MHz
fractional PLL which can For PCB: 100 Ω clock
be used to allow other differential transmission
clocks in the range of line (50 Ω single ended).
100MHz to 200 MHz Matched
Differential pair. Keep
traces as short as
possible. AC couple on
PCB (75 nF to 200 nF for
each TX lane)
PS_XI Device input 19.2/25/26/40 MHz or ± 100 ppm XTAL or 1.8 V CMOS. 3 ps RMS 40% to 60%
reference clock 1.8V CMOS input if The input range is
external between 1.65 V and 1.95
V
UP_XO Device input 12 MHz XTAL or ± 400 ppm XTAL or 1.8 V CMOS Peak Jitter of 40% to 60%
reference clock 12/19.2/24/48 MHz 1.8V ±100 ppm
CMOS input if external

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Table 28-5 Clock Specifications (Continued)

Clock Duty
Clock Name Description Frequency Tolerance I/O Characteristics Clock Jitter
Cycle
RPDIF0_MCLK Data clock Up to 61.44 MHz (2T2R 3GPP CMOS 1.2 V to 2.5 V TBD 45% to 55%
(radio CMOS generated by the at Nyquist for 20 MHz compliant based on input VDD.
interface data clock ADI radio to the LTE)
port 0) BBIC
RPDIF1_MCLK Data clock Up to 245.76 MHz (2T2R 3GPP ANSI-644 compatible TBD 45% to 55%
(radio LVDS generated by the at Nyquist for 20MHz compliant LVDS. 1.8 V to 2.5 V
interface data clock ADI radio to the LTE) based on input VDD
port 1) BBIC
Note:
For clock RPDIF0_MCLK, RPDIF1_MCLK, the clock comes from the ADI radio directly and does not need to be generated on the PCB. For 2T2R
20MHz LTE, only 1 of these 4 interfaces is needed.

28.4 Reset

28.4.1 Global Resets

• External Hardware Reset—Asynchronous active low input that resets the whole device. Once activated, it
reaches all flops without any synchronization. It is synchronized to each clock domain when it is de-asserted.
Internally, the Hardware reset is expanded, and clocks are shut off when it transitions from active to inactive.
• Watchdog Reset—When the watchdog timer expires, it resets all the blocks, clock and reset modules, PLLs,
and including itself after some synchronization delay in the reset block. It behaves similarly to the external hard
reset. Internally, the reset is expanded, and clocks are shut off when it transitions from active to inactive.
• Global Software Reset—The top clock and reset block has a self-clear global software register. Global software
reset should reset all blocks except the PLLs and clock reset modules. The register is self-cleared after few
cycles, but the reset itself is expanded.
• Functional Software Reset—Functional Software reset shall reset all functional blocks, that is, all blocks
except: PLLs, clock and reset modules, and all debug logic circuitry. This allows for debugging the boot up
sequence, by setting up the debug circuitry then issuing a functional reset to trace the boot up sequence. Two
types of functional resets are available: Self-Clear and Static resets.
• Debug Reset—A static configuration bit in the top level clock and reset shall keep all debug logic circuitry in
reset. This includes the CoreSight logic, as well as the ARM debug logic. The ARM debug logic can be put in
reset individually by configuration bits within the System cluster clock and reset. By default, all debug reset
configuration bits are in the inactive state (no reset).

NOTE: All CPUs of the ARM core must have their debug resets inactive during boot up, even if
only CPU0 is being used. All debug reset signals are ANDed internally to form one reset
signal.

28.4.2 Block Resets

Each clock domain has a dedicated reset that is synchronized to it. A global reset control bit shall reset the whole
clock domain, including all branches.
For each branch of the clock domain, a configuration bit shall reset that specific branch.

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28.4.3 Reset Description

When reset is asserted, clocks are kept running for few cycles, then clocks are shut down, reset is de-asserted,
and after few cycles, clocks are powered up again, all under hardware control. The duration of reset, number of
cycles to shut down the clocks, and the cycles to power them up again, are under parameter control.
Figure 28-12 Reset Waveforms

ref_dk

rst_event

ref_clock_gated
START_EVENT
RESET_WIDTH EVENT_END

reset_n

28.4.4 Reset Sequence

After external hard reset or Watchdog Timer reset de-activation, all circuitry will come out of reset except the ones
controlled by a dedicated software reset. Their order shall be under software control.
It is possible using proper parameters, to generate RTL that has the clock dividers come up of reset while the
blocks are kept in reset for a longer period of time. This allows the use of clock divider as the default while making
sure that the blocked is clocked during reset (clock divider needs to be out of reset to operate).

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29 Electrical and Environmental
Specifications
This chapter provides all electrical and environmental specifications for the Transcede 2xxx:
• Power Supply Requirements
• Power Turn-On Sequence and Timing Requirement
• Thermal Characteristics

29.1 Power Supply Requirements

The tables in this section list the voltage, current and power requirements, DDR3 mode DC specifications and DC
electrical specification for the Transcede 2xxx.
Table 29-1 is for conservative hardware design considerations assuming all power rails running at worst case
conditions simultaneously, which is not the case normally.

Table 29-1 Power Supply Voltages and Tolerances

Transcede 2xxx
Voltage (VDC)
Parameter Symbol Max Current
Nominal ± Margin
Consumption Power Consumption (W)
per Domain (A)
VCORE Supply Voltage VDD 1.1 ± 3% 3.1 3.41
3.3 V Supply Voltage VDDO_3P3 3.3 ± 5% 0.03 0.099
2.5 V Supply Voltage VDDO_2P5 2.5 ± 5% 0.01 0.025
1.8 V Supply Voltage VDDP_1P8 1.8 ± 5% 0.01 0.018
DDR PLL Voltage 1.8V DDR_PLL_VDD 1.8 ± 5% 0.01 0.018
DDR3 VREF Supply Voltage DDR_VREF 0.75 ± 2.5% 0.0005 0.000375
DDR3 Supply Voltage DDR_VDDQ 1.5 ± 5% 0.28 0.42
USIM Supply Voltage VDDO_USIM 1.8 ± 5% 0.01 0.018
PLL Analog Supply Voltage AVDD_CORE_PLL 1.1 ± 5% 0.05 0.055
SRDS Analog Supply PA_AVDD1 1.1 ± 2.5% 0.2 0.22
Voltage
SRDS Analog Supply PA_AVDD2 1.8 ± 2.5% 0.1 0.18
Voltage
SRDS Analog Supply PA_AVDD3 2.5 ± 5% 0.002 0.005
Voltage
USB PHY Voltage AVDD33V 3.3 ± 5% 0.01 0.033
USB PLL AVDD11V 1.1 ± 5% 0.001 0.0011

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Table 29-1 Power Supply Voltages and Tolerances (Continued)

Transcede 2xxx
Voltage (VDC)
Parameter Symbol Max Current
Nominal ± Margin
Consumption Power Consumption (W)
per Domain (A)
RPDIF LVDS Voltage AVDD18V 1.8 ± 5% 0.001 0.0018
THERMAL Voltage Supply VDDA1P8_TH 1.8 ± 5% 0.001 0.0018
Note:
The Max current consumption as shown is estimated for worst case conditions @75 oC Case. We recommend adding 50% margin on top of these
numbers in the design of power regulators.

Table 29-2 DDR3 Mode - DC Specifications

Symbol Parameter Min Nom Max Units
VIH(DC) DC input voltage High VREF + 0.1 VDDQ V
VIL(DC) DC input voltage Low VSSQ – 0.3 VREF – 0.1 V
VOH DC output logic High 0.8 * VDDQ V
VOL DC output logic Low 0.2 * VDDQ V
RTT Input termination resistance 108 120 192 Ω
(ODT) to VDDQ/2 54 60 96
36 40 64

Table 29-3 DC Electrical Specification for 3.3V tol and non-tol IO (VDD = 1.65V~3.60V, Vext = 3.0~3.6V, TA
= -40 to 85 oC)
Parameter Condition Min Typ Max Unit
Vtol Tolerant external voltage** VDD Power Off & On 3.6 V
Vih High Level Input Voltage
CMOS Interface 0.7*VDD VDD + 0.3 V
Vil Low Level Input Voltage
CMOS Interface VDD = 2.5V ± 10%, 3.3V ± 10% -0.3 0.7 V
VDD = 1.8V ± 10% -0.3 0.3*VDD
∆V Hysteresis Voltage 0.15 V
lih High Level Input Current
Input Buffer Vin = VDD VDD Power ON -3 3 uA
VDD Power Off & SNS = 0 -5 5
Input Buffer with pull-down Vin = VDD VDD = 3.3V ± 10% 20 45 80 uA
VDD = 2.5V ± 10% 20 40 80
VDD = 1.8V ± 10% 20 40 80

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Table 29-3 DC Electrical Specification for 3.3V tol and non-tol IO (VDD = 1.65V~3.60V, Vext = 3.0~3.6V, TA
= -40 to 85 oC) (Continued)
Parameter Condition Min Typ Max Unit
lil Low Level Input Current
Input Buffer Vin = VSS VDD Power ON & Off -3 3 uA
Input Buffer with pull-up Vin = VSS VDD = 3.3V ± 10% -15 -40 -80 uA
VDD = 2.5V ± 10% -15 -40 -80
VDD = 1.8V ± 10% -15 -40 -80
Voh Output High Voltage loh = -1.8mA 0.75*VDD VDD V
Voh Output High Voltage loh = -3.2mA, -7.2mA, -10.8mA 0.8*VDD VDD V
Vol Output Low Voltage IoI = 1.8mA, 3.2mA, 7.2mA, 10.8MA 0 0.2*VDD V
loz Output Hi-Z current -5 5 uA
CIN Input capacitance Any input and Bidirectional buffers 5 pF
Note: **specification is only available on tolerant cells.

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Table 29-4 DC Electrical Specification for 5V Tolerant IO (VDD = 3.0V~3.60V, Vext = 4.5~5.5V, TA = -40 to
85 oC)
Parameter Condition Min Typ Max Unit
Vtol Tolerant external voltage** VDD = 3.3V ± 10% 5.5 V
Vih High Level Input Voltage
CMOS Interface VDD = 3.3V ± 10% 0.7*VDD VDD+0.3 V
Vil Low Level Input Voltage
CMOS Interface VDD = 3.3V ± 10% -0.3 0.7 V
lih High Level Input Voltage
Input Buffer Vin = VDD -12 12 uA
Vin = 5V ± 10% -20 20
Input Buffer with pull-down Vin = VDD VDD = 3.3V ± 10% 20 45 80 uA
lil Low Level Input Voltage
Input Buffer Vin = VSS -3 3 uA
Input Buffer with pull-up Vin = VSS VDD = 3.3V ± 10% -15 -40 -80 uA
Voh Output High Voltage loh = -1.8mA 0.75*VDD VDD V
Voh Output High Voltage loh = -3.2mA, -7.2mA, -10.8mA 0.8*VDD VDD V
Vol Output Low Voltage lol = 1.8mA, 3.2mA, 7.2mA, 10.8MA 0 0.2*VDD V
loz Output Hi-Z current -12 12 uA
CIN Input capacitance Any input and Bidirectional buffers 5 pF
Note: **specification is only available on tolerant cells.

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Table 29-5 DC Electrical Specification for LVDS Receiver

Parameter Condition Min Typ Max Unit
VTH [1]
Differential Input High VCM = 1.2V 100 mV
Threshold
VTL Differential Input Low -100 mV
Threshold
|Vid| Differential input voltage 100 350 600 mV
VI[2] Input Voltage Range 0.2 0.9 Vdd-100m V
TST Settling Time 10 us
(When RESETB signal is High)
IVDD Dynamic Current CL=0.2 pF 2.0 3 mA
Fop = 200 MHz @Binary Pattern
IPD Power Down Current RESETB=Low 100 uA
Notes:
1. VCM means the common-mode voltage of input signal
2. VI means the input common-mode voltage range of receiver.
3. Typical values measured at AVDD18A=1.8V, AVSS18A= 0V, AVDD10D=1.1V, AVSS10D=0V; TA=25°C.

Table 29-6 Electrical Specification for LVDS Driver

Parameter Condition Min Typ Max Unit
VOD Output Differential Voltage RL=100 Ω 250 350 450 mV
VOS Output Offset Voltage 0.7 0.9 1.1 V
Ipd Power Down Current RESETB=Low - 100 uA

Note:
VOD typ value is 350mV when ROUT port of ref_bias block connects to the 4.3K external R. Vod value depends on external R

Table 29-7 Typical Pull-up, Pull-down Resistance

Parameter Pull-Up Pull-Down
VDD = 3.30 V, T = 25 oC 70 KΩ 85 KΩ
VDD = 2.5 V, T = 25 oC 60 KΩ 65 KΩ

29.2 Power Turn-On Sequence and Timing Requirement

0.75V, 1.1V, 1.5V, 1.8V, 2.5V, and 3.3V are available. Startup sequence:
1. Power-up pre-driver supply (Pre-IO power) first: 1.8V Supply
2. Power-up VCore supply (core power): 1.1V Supply
3. Power-up IO supply (IO power): 2.5V, 3.3V, 1.5V, 0.75V Supplies

NOTE: The power ramp should be lower than 0.5 V per microsecond.

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To prevent excessive current from power supply during power-up and power-down periods, the power sequences
given in Figure 29-1 should be followed.
Figure 29-1 Power Sequence for Normal IO Mode

Core Power
IO Power

Pre-IO Power

IO Power
Pre-IO Power
Core Power

T>0us T>0us T>0us T>0us

To prevent shoot-through current from power supply and glitch on the pad during power-up and power-down
periods:
1. Power-up PRE-IO supply (VDDP) first, core supply (VDD), and then power-up IO supply (VDDO).
2. Power-down core supply (VDD) first, IO supply (VDDO), and then power-down PRE-IO supply (VDDP).

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29.3 Thermal Characteristics

29.3.1 Thermal Operating Conditions

Table 29-8 lists the thermal operating conditions for the Transcede 2xxx.

Table 29-8 Thermal Operating Conditions

Parameter Symbol Min. Typical Max. Units
Junction Temperature Tj -40 — 110 °C

29.3.2 Package Thermal Design and Test Structure

Figure 29-2 shows the structure of the Transcede 2xxx HFC-BGA package. With the die lying face down on the
substrate, solder bumps provide direct interconnections between them. A polymeric underfill is dispensed to
surround the solder bumps.
Figure 29-2 HFC-BGA Package Structure

Die
Heatspreader
Thermal interface material

Underfill resin
Solder bump

Substrate Solder ball

Test board

NOTE: Drawing in the figure is not to scale. This is for illustration only.

To obtain the best package thermal performance, connect the thermal balls to the motherboard ground plane,
using thermal vias shown in Figure 29-3.
Figure 29-3 Connecting Thermal Balls to Motherboard Ground Plane Using Thermal Vias

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29.3.3 Product Thermal Performance

This subsection discusses two key thermal parameters:
• θjc = Package Thermal Resistance from Case to Junction (°C/W)
The θjc value for the Transcede 2xxx device package is a constant that is related to the package.
• θja = Package Thermal Resistance Junction to Ambient (°C/W)
The θja value for a Transcede 2xxx device mounted on a JEDEC standard board with no air flow is directly
proportional to the mounting area (high power component density).

NOTE: See Transcede 2xxx Thermal Application Considerations (PN: 842xx-HWG-001) for
details.

Figure 29-4 shows test conditions. For more information, see JESD 51-9 standard.
Figure 29-4 Test Conditions

A = 114.5 mm
B = 101.5 mm
Lp (PCB thickness) = 1.6 mm
Lp (component height) = 3.2 mm

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30 Package Dimensions
This chapter provides mechanical packaging information for the Transcede 2xxx.
Figure 30-1 is the drawing of the Transcede 2xxx package dimensions.
• 21 mm x 21 mm FCBGAH with four metal layers, Flip-Chip.
• 25 row x 25 row, 625 solder balls at 0.8 mm ball-pitch.

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Transcede 2xxx Package Dimensions
Figure 30-1
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Revision Summary

Revision Summary
Revision Date Changes
A September, 2013 Changes in 842xx-DSH-001-A
A4 September, 2013 Changes in 842xx-DSH-001-A4
A3 October, 2012 Changes in 8422x-DSH-001-A3
A2 September, 2012 Changes in 8422x-DSH-001-A2
A1 July, 2011 Changes in 8422x-DSH-001-A1

Changes in 842xx-DSH-001-A
• Initial release.

Changes in 842xx-DSH-001-A4
1. Changed the device name from T2200 to T2xxx.
2. Updated Figure 1-1, “Transcede 2xxx Block Diagram,” on page 24 for FEC DMA FIFO.
3. Updated Table 1-2, “Transcede 2xxx Devices,” on page 23. and the whole document for the device part
numbers.
4. Updated I/O in Table 3-2, “DDR Signals,” on page 47,Table 3-5, “Expansion Bus Signals,” on page 50, Table 3-
9, “UART Signals,” on page 54, Table 3-12, “USB Signals,” on page 55 and Table 3-15, “JTAG Signals,” on
page 58.
5. Updated EXP_A_3 in both Table 2-2, “Bootstraps Signals,” on page 31 and Table 3-5, “Expansion Bus Signals,”
on page 50.
6. Updated Table 3-7, “TDM Signals,” on page 53 and Table 3-8, “SPI Signals,” on page 53.
7. Updated Table 3-10, “GPIO Signals,” on page 55 for I/O and PD/PU.
8. Updated Table 3-18, “Test and Misc Signals,” on page 59.
9. Updated I/O values in Table 3-13, “RPDIF 0 (JESD207) Signals,” on page 55 and Table 3-14, “RPDIF 1
(JESD207 LVDS) Signals,” on page 56.
10. Updated the CPRI rate 2 and rate 3 to 1228.8 Mbit/s and 2457.6 Mbit/s in Section 6.1.1, "General Features,"
on page 74.
11. Removed the QoS support described in the last feature of Section 8.1, "Feature List," on page 92.
12. Updated the max clock frequency in Section 11.1, "Feature List—SPI," on page 124.
13. Updated GPIO 10 to GPIO 15 in Table 13-1, “GPIO Muxing,” on page 131.
14. Updated Section 22.4.1, "Feature List," on page 180 for the last feature.

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Revision Summary

15. Added Section 23.4, "True Random Number Generator (TRNG)," on page 190.
16. Removed Section 28.2.3 Timer Interface and Section 28.2.4 Timing.
17. Added Section 28.2.3, "Radio Frame Synchronization Timers," on page 229.
18. Added Table 28-3, “Reference Clock Definition,” on page 238
19. Updated USB PHY in Table 28-3, “Reference Clock Definition,” on page 238.
20. Updated UP_XI in Figure 28-11, “Clock Muxing Diagram,” on page 239.
21. Updated USB PHY Refclk in Table 28-4, “System Clock Definition,” on page 239
22. Added UP_XO and input range for PS_XI in Table 28-5, “Clock Specifications,” on page 241.
23. Added “UDP checksum offload is only supported by RGMII. SGMII does not support UDP checksum offload”.
24. Added Section 28.2.3.4, "IQ Counter," on page 234.
25. Updated Figure 29-1, “Power Sequence for Normal IO Mode,” on page 249.
26. Updated Table 29-3, “DC Electrical Specification for 3.3V tol and non-tol IO (VDD = 1.65V~3.60V, Vext =
3.0~3.6V, TA = -40 to 85 oC),” on page 245 and Table 29-4, “DC Electrical Specification for 5V Tolerant IO
(VDD = 3.0V~3.60V, Vext = 4.5~5.5V, TA = -40 to 85 oC),” on page 247.

Changes in 8422x-DSH-001-A3
1. Added Transcede 2100 device and changed the title to Transcede 2xxx Data Sheet Preliminary.
2. Updated Table 2-2, “Bootstraps Signals,” on page 31.
3. Updated Section 6.2, "CPRI System Block Diagram," on page 76 for AXI2CPUIF block.
4. Updated Section 8.1, "Feature List," on page 92 for the number of QoS queues.
5. Updated Figure 27-4, “eFuse Layout,” on page 221.
6. Updated Section 28.2.1, "Feature List," on page 227 for the TDM Rx FrameSync timers number.

Changes in 8422x-DSH-001-A2
1. Rearranged the outline of the data sheet contents
2. Added Section 1.3, "Transcede 2xxx Devices," on page 23
3. Updated Table 1-3, “CEVA Group Partition (0xF0),” on page 27 for BP memory size.
4. Updated Section 1.6.1, "CEVA Group Slaves," on page 27, Section 1.6.4, "Radio Group," on page 28,
Section 1.6.5, "System Masters/Slaves Group," on page 28
5. Updated Table 2-1, “Transcede 2xxx Boot Options,” on page 30
6. Updated Table 2-2, “Bootstraps Signals,” on page 31
7. Updated Table 3-4, “RGMII Signals,” on page 50
8. Updated Table 3-5, “Expansion Bus Signals,” on page 50, removing the muxing information for EXP_A_14.
9. Updated Table 3-13, “RPDIF 0 (JESD207) Signals,” on page 55 and Table 3-14, “RPDIF 1 (JESD207 LVDS)
Signals,” on page 56
10. Added Section 3.4, "Unused Interface Termination," on page 61
11. Added Section 5.2, "Supported Standards," on page 73

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12. Change CPRI version to 4.1 in Section 5.1, "Feature List," on page 73 and Section 6.2, "CPRI System Block
Diagram," on page 76
13. Updated CPRI feature list and added CPRI DMA in Chapter 6, “Common Public Radio Interface (CPRI),” on
page 74
14. Updated Chapter 9, “Expansion Bus Interface,” on page 104
15. Updated Section 11.2, "Feature List—High Speed SPI," on page 124, Section 11.5, "SPI Timing," on
page 126, Section 11.6, "High Speed SPI DMA," on page 128
16. Added Section 12.2, "Feature List—HS-UART," on page 129
17. Added item 7 in Section 16.3, "Smart Card Session Description," on page 144
18. Removed Section USIM Architecture
19. Updated feature list of Section 17.1, "Features List," on page 149
20. Updated Section 17.3, "RPDIF Data Plane Variations," on page 150
21. Added Section 17.5, "RPDIF Timing Parameters," on page 153
22. Added Section 13.2, "GPIO Muxing," on page 131
23. Updated Chapter 16, “Universal Subscriber Identity Module (USIM) Interface,” on page 143
24. Added Section 19.5, "TrustZone Support," on page 162
25. Added Section 21.6, "MAP Direct Memory Access (DMA) Controller," on page 171
26. Added Section 22.4, "FEC Direct Memory Access (DMA) Controller," on page 180
27. Added Section 24.6, "Memory to Memory DMA Controller for CRP (MDMA-CRP)," on page 200
28. Updated Table 24-1, “MDMA Interface,” on page 201
29. Added DMA descriptions in Chapter 26, “Memory to Memory DMA (MDMA) Controller,” on page 209
30. Updated Chapter 27, “Internal Boot ROM (IBR) Implementing Secure Boot,” on page 216
31. Updated Section 27.4, "Clock and Frequency Options," on page 217
32. Updated Table 27-5, “Extended Boot Option Bits – Secure Boot Opt,” on page 220
33. Updated Section 27.9.1, "eFuse Operations," on page 222
34. Added timers in Chapter 28, “Interrupts, Timers, Clock and Reset,” on page 223
35. Updated Figure 28-11, “Clock Muxing Diagram,” on page 239
36. Updated Table 28-4, “System Clock Definition,” on page 239
37. Added Section 28.3.4, "Clock Specifications," on page 241
38. Updated Section 29.2, "Power Turn-On Sequence and Timing Requirement," on page 248

Changes in 8422x-DSH-001-A1
1. Preliminary release.

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General Information:
Telephone: (949) 579-3000
Headquarters - Newport Beach
4000 MacArthur Blvd., East Tower
Newport Beach, CA 92660

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