Amplifiers n Action

A high-voltage differential probe is a critical piece of test equipment for looking at

high-voltage signals. In his article, Andrew describes his design of a high-voltage
differential probe with features simlar to commercial devices, but at a considerably
lower cost. It uses just three op amps in a classic instrumentation amplifier
configuration and provides a great exercise in precision analog design.

A high-voltage differential probe is an

indispensable piece of test equipment
for anyone who wants to examine high
voltage signals on a standard oscilloscope
and do so safely. For safety reasons, the ground side
of your oscilloscope probe Is connected directly to
Fortunately, there is a safe way to measure high-
voltage circuits such as in this example: a differential
probe. It has two high-impedance inputs and a single,
ground-referenced output. The output is proportional
to the difference in voltage between the positive
and negative inputs. Any common-mode signal Is
mains earth. This means you can only measure earth- rejected. In the example of our off-Inis switcher, we
referenced signals, or truly floating signals, such would connect the negative input to the "reference
as those encountered in battery-powered circuits, rail, and the positive input to the point we want to
where it is possible to connect one part of the circuit investigate. The output would be proportional to the
to mains earth via the scope. difference between the two.
But what if we want to measure some signals in
a mains-referenced circuit such as an off-line switch- DESIGN APPROACH
mode power supply? The control circuit is typically While I have owned a commercial differential probe
referenced to the negative side of the rectified to, some years, I find it a littJe bit inconvenient to use.
mains. This point is certainly not at earth potential. That's because it requires a wa-wart power supply
If you were to connect the ground clip of a standard that clutters up my benditop and it is quite chunky. I
oscilloscope probe to this point, you would create thought it would be nice to build a differential probe
a short directly to earth via your oscilloscope. This that was reasonably small sized with a rechargeable
would almost certainly damage your oscilloscope and battery. It has proved to be an interesting exercise in
probably destroy the circuit under test. precision analog design, as you will see later.
Incidentally, when I started my career many years I wanted specifications similar to commercial
ago in the power electronics field, you would routinely units costing $300 or $400, so I started by writing
see oscilloscopes with the earth wire cut at the down a few target specifications:
mains plug to avoid just this problem. This was—and
remains—an extremely dangerous practice, because • Basic 9aMl accuracy of better than 1%.
it meant that the entire oscilloscope would be floating •Input impedance above I 1W with parallel
at mains potential. Merely touching the case of the capacitance under S pE.
scope could deliver a fatal shock. I even owned a •Input voltage range suitable for measuring
1970s; en oscilloscope with a Ofiround lifto switch on 230 V +15% mains, which we have in Australia
the back panel to make it more convenient to make (lets say ±400 V). It arnold be safe to connect to
the instrument lethal. considerably higher voltages
(Ifl]t.t•t fl

•Abandw$dthofatle.st25 MHz to parasitic capacitances and board layout. I

• DC and 50/60 Its common-mode rejection also had to contend with all the usual non-
ratio (CMRR) of 60 dB or better (1/1,000) ideal characteristics of op amps such as input
• More than 3 hour, of battery life offset voltages, input common mode ranges,
Input bias currents and the like. Sounds like
In principle, the concept of a differential fun, so here I will walk through the design
probe is pretty straightforward: a matched process pretty much as I tackled it.
pair of input attenuators followed by a classic
three op-amp differential instrumentation INPUT ATIENUATOR
amplifier, as shown in R,urt 1. You can think For this stage, we need a pair of input
of this circuit has having three sections: an attenuators capable of safely withstanding
attenuator, a buffer stage and a difference mains voltages, with a high input impedance,
amplifier stage. The overall gain of the circuit each with a gain of 1/200 matched to better
is given by multiplying the gains of each of than 0.1% and with a bandwidth of at least
these stages as shown in this equation: 50 MHz.
I started by selecting the Input resistance Ro
Vout_( Rb f'1 2Rc'jRf to be 4 MO, mad, up of a Wing of four, 1 MO,
V'—V IRa#Rbfl. Rd )(Re 0.1%, OA W, 1206 SMT resistors In series. Series
resistors are required here, since the maximum
I started by choosing the input attenuabon working voltage of a single resistor of the type
ratio to be 1/200, so hat the maximum I chose Is limited to 200 V. A quick check shows
operating voltage of *400V will be attenua ed power dissipation in this resistor string will not
to ±2 V-4ow enough to be within the npot bean Issueupto2.S kV, sothemaxkntvnvoltage
common mode range of typical Ff1 input op is limited to800Vby the resistor(maximum
amps powered from ISV rails. 01 course, this working voltages. This comfortably exceeds our
means smaller signals—such as the gate drive design requirement of 400 V.
In our notional power supply—will be just The value of Rb can new be calculated to be
Iew tens of millivolts after the attenuator. 20.1005 kg. The schematic in Figure 2 shows
Clearly, we need the following stage to this pretty odd value is made up of a string of
optionally provide some gain when we are resistors and a trim-pot. In practice, we can
looking at small differential sagnals. achieve a DC GiM of better than 120 dB with
The good news I, that the gain of the this arrangement.
buffer stage of a classic instrumentation amp Half the trimpot accounts for 50 0 of the
such as this can be programmed a single value of Rb The rest is made up of two 10 cO.
resistor, Rd in Figure I. If Rd is open &aia, 0.1% resistors and a 91 0, 1% fixed resistor.
the gain of this stage will be unity, suitable for The 10 kQ resistors are part of a 4-resistor
input signals in the multi-hundred-volt rage. matched array. This turns out to be a much
By switching in a resistor Rd we can add an cheaper way of buying precision resistors
additional range with a gain of perhaps 10, than as individual components though with
allowing us to sensibly measure differential a limited range of value,. As an added bonus,
signals In the tens of volts. these resistors are matched to each other
The final stage is the difference amplifier, within 0.05% and tnck with temperature,
which converts the differential signal into because they are in on the same substrate.
a single-ended ground-referenced one. I This helps keep our attenuators matched.
decided to set the gain of this stage to 2, The astute reader will have already
so that the overal differential gain of the observed that this combination of resistors
instrument would be 1/100 or 1/10, and the adds up to 20,141 kg, not the 20.1005 kQ
maximum output swing is nominally *4 V
which we should be able to achieve with AS
rails. Therefore, our full-scale input ranges
are ±400 V or ±40 V.
So far, so good. I now had three analog
stages to design, plus a power supply. To
achieve an overall DC gain accuracy less than
1%, each stag, had to have * gain accuracy
of about 0.25%. Achieving greater than 60 dB
CMMR (common mode rejection ratio) means
matching the attenuators and the resistors
In the difference amplifier to at least I part
in 1,000. Achieving a large-sgnal bandwidth FIE S
greater than 25 MHz would require some hctoo'.crwOo-wd%ttd ptde OvdirSimix A mAdheJ per ctItt*tu$erI3lt,oOt,
pretty special op amps and careful attention •CiWC ?TttWW,PIf*VMt%InWW.Of i,rwItyi,qutq, cMine.
$4 CUIt ia• Mn. 2O nfl

mentioned above. This is beause we have protection diodes will be on the order of
to Lake into aunt the tiled of the parallel 4.3 p1. Not much, you might say. But the
10 MQ resistors (R12 and RIS). 10 MO in corner frequency of this low-pass filter will be
paraflel with 20.141 iQ is bang on 20.1005 Ia. under 10 kHz.
R12 is associated with op amp offset nulling, The answe. of Caine, is to add some
discussed later, while RIS is there purely to frequency compensation capacitance across
keep the circuit symmetrical. the 4 MO resistors. The impedance of this
We can safely Ignore the input impedance and the parasitic capacitance should be
of the op amp as we will we an Fr input in the some ratio as the resistances in the
type with an impedance north of 100 GO. voltage divider. In our case, the compensation
Smilady, a quick calculation shows that with capacitors should be 199 times smaller than
an approximately 20 Ia source impedance, 4.3 p1'. Obviously, this is not practical, so we
we can ignore the op amp input bias current have to tackle this problem from the other
as long as it is less than 50 pA. The diode direction. Ant, let's choose a reasonable
pairs DPi and 0P2 are there to protect the op compensation capacitance and calculate the
amp inputs from any overvoltage making its other capacitance.
way through the attenuator. They effect vcly I chose to use a string of four IQ pF, 500 V.
clip the signal to one diode drop above or 5460 1206 SW capacitors In series. This gives
below the supply rails. us a compensation capacitance of 2.5 pF and
This is all well and good for DC signals. We will handle input voltages to 2kv, comfortably
have a safe circuit with precise attenuation exceeding our S800Vinputliitthtdefined bythe
and great CMRR. But what about the AC resistors. For proper frequency compensation
behavior? The buffer op amps will have a we now need a total capacitance at the input
small but finite input capacitance, as will the to the buffer op amps of 497.5 pF. In practice,
protection diodes. This capadtance, with the this is made up by the parallel combination of
4 MO input resistance, forms a low-pass filter the op amp and diode input capacitance, two
that wiN severely attenuate high-frequency, fixed capacitors (C9/00 and Cu/Cu) and.
signals. According to the datasheets, this trimmer capacitor. The trimmer provides a
combined capacitance of the op amp and range of adjustment of 461 pF to 524 pF to

-
e... -
JI_ •
(a,.. -
—a-
5:

-- -- -- -- - a a .S% ,p.-t3t.
- :•.t
111111

11
4-

NCZ 2
e thefjzwmdc dtepca C.,.,,.,1 otto be mdem,qvnS An I gp.coia drtoItgt s,ase,frT*TC.WO aS*eiy mck e,at Vvc
allow for component tolerances and layout tolerance for the 120 D resistor, but only 1%
differences. The total capacitance seen at the for the 1.5 kill resistor. I could do this because
Input terminals is nominally 2.5 pF, since the the error in the 120 Q resistor, dominates, and
compensation capacitors will dominate. any tighter tolerance on the other resistor is
just wasted money. The same applies foe the
INSTRUMENTATION AMPLIFIER 91 0 resistors; and the trimpot in the input
Next is the three op amp instrumentation attenuato. This ea trick wd worth keeping in
amplifier. This classic circuit has a few very mind for your precision designs.
nice futures that come in handy for this Just as for the input attenuator, I had
application. It has very high input impedance, to provide frequency compensation for
common mode gain of 1 independent of the voltage divider formed by Rc and Rd
resistor matching, and differential mode gain (figure 1). As before, I selected a nice round
programmable viajust one resistor as already value (100 p9 for the capacitors across ftc
discussed. (R14 and RL5 in Figure 2) and calculated that
The technical requirements for the Input we needed 450 pF across R20 and R21. This
op-amps for Ui and U2 are pretty tough. I is a series connection of 470 pF and 10 riF
needed FET inputs for high impedance and capacitors.
I" bias current, a very wide large signal The final difference amplifier is, by
bandwidth, a flat response below about comparison, fairly simple to design. The
50 MHz, low Input offset voltage, +5 V supply rejection of any remaining common-mode
railsuppliesandan inputcommonmode range signal relies on well-matched components, so
to *2 V. I chose Analog Devices A0A4817 again I took advantage of low-cost matched
which is expensive at around $10, but fits resistor arrays for R22 and k23. For this
the bill nicely. It has an input impedance of op amp, I could relax the requirements a
500 GO in parallel with 1.3 p1', typical input little compared with Vi and 112. Any input
bias current of 2 pA, a large signal bandwidth impedance greater than about S MQ and
to 200 MHz, 0.1 dB gain (lathes, to GC MHz, a an input capacitance lower than about 5 p1'
typical offset voltage of 0.4 mV (very low (or should be fine, because the source impedance
a Ff1' input op amp) and an input common is relatively low. Similarly, an input bias
mode range of -4.2 to 2.2 V with ±5 V rolls. cuirejit less than 10 pA should be no problem.
III only required a gain of 1 for this stage, I needed an Input common mode range of
I could have simply wired these op-amps *2 V and an output swing of ±4 V. A lower
as non-inverting buffers. Since I wanted to cost CMOS op amp should suffice here, so one
have the option of a gain of 10, 1 had to close would expect fairly low input offset voltages
the feedback loop around each op imp with compared to the FU input as amps used in
a resistor (MS In the sdwmatic and Pic in the previous stage. I did, howeveç need a
Figure I). It is a good idea to choose a fairly pretty good large signal bandwidth.
low value for this resistor, because it will I diose the 1116611 from Texas Instrtwnents
form an RC low-pass filter with the op amp (TI), which has an input impedance of 6 NO in
input capacitance—the effect of which will parallel with 2.5 p1'. Typical input bias current
be to increase the gain of the buffer as the Is -6.S pA. Input common mode range Is-S.2V
frequency rises. to +3.8 V. and input offset voltage is typically
I selected a resistance of 500 Q, made up 74 iN. The output can swing to within 200 my
from a pair of paralleled I kQ resistors from of the supply rails into a 1 kQ load. The output
another precision matched resistor army. is intended to be coMected to a standard
This minimizes the effect of gain peaking in oscilloscope input, which is typically a 1 MQ
the frequency range of interest. but there resistance in parallel with a few picofarads of
is still a potential issue At high frequencies capacitance. The 51 Q resistor R30 is there to
that should be addressed. The 510 Q resistor protect the output op amp from inadvertent
in series with each op amps non'4nv.rting short Circuits.
Input S the result, it forms another low-pass
filter that attenuates the input signal at about
the same rate as the low-pass filter in the ABOUT 7W AUTHOR
feedback loop amplifies It. Neat. Andrew Levido ned a baflelor's degree in
With Re (Figure I) fixed at $00 Q, we can Electrical €nginening in Sydney, Australia. is 1*. He worW for several
easily calculate the value we will need for Rd wers in RSD for power dectronics ard teleco m,uncation companies before
to achieve a gain of 10 on the h4.-gain range. rre4rq into management roles. Ardinivi has maintained * hands-on interest
This tLnlS out to be the infinitely repeating in electronics, particularly embedded sntms, pwer donics and control
value of 121.11 Q. This odd value was easy to theory in his free time. Over the years he has written a nLmber of articles
create with a parallel combination of 120 Q and for various electronics publications and occasio,,aPy provides corsultinç ser-
1.5 kfl (R20 and R21 in Figure 2). You will note vices as time allows.
from the schematic that I have specified a 0.1%
$ cmcurg8aa.n..eztsJ4s

FI 3 of inductors and three low ESR ceramic

¶t uic?A41 d.The114 crc&. The capacitors. The chip also has a low-voltage
4 fir roçtattectcnte shut-down to protect the LIPo cell from over
ads ors! .1 'X icqrnro, . .t
discharge. I was concerned that them might
rtbctom. yo lccco.vtt ,m
onøctNtQraw. be a bit too much switching noise on the
power rails, so added an IC filter (1.3/C29
and 14/d0) between the switcher and the
analog circuitry. A green LED (LED2) across
the power rails provides user indication that
the power Is on.
The battery is charged from a Micro B
USB connector via a MAXISSS charger from
1 Maxim Integrated. This is a very simple linear
charger with two inputs, intended to be used
in applications where there Is both a USB
power source and a DC nil wart. If power is
present at the DC input (1.14 pin 4), the tWo
cell will be charged at 280 muh. If only the
USB source is available (34 pin 1), charging
will be limited to 100 MA, respecting the USB
specification. I have configured the circuit so
I can connect either of these inputs to the
USB connector via R24 and R25. By omitting
R24 and loading a 0 0 resistor In R25, I can
choose to use a high-current 1)58 charger
for faster charge or, by omitting R25 and
loading a 0 0 resistor in R25, configure the
differential probe to be USB compliant and
put up with a longer charge cycle. A green
LED (LED 1) indicates that the battery Is
charging. The USB power input is protected
POWER SUPPLY by a Tfl diode (Zi) and a resettable thermal
Calculations show we need ArS V power (use (Fl).
rails with a maximum current drain in the Note that the power switched via SWIA.
order of 80 mA. I chose to use a single cell In the Off/Charge position, the battery Is
IWo battery as the power source, since this connected to the charger and isolated from
could be charged from the standard USB the rest of the circuit. In either the xIO or
power supplies that have become ubiQuitous. xIOO gain position, the battery is connected
M AA-slzed(14,500) cell would fit nicety in the to the switcher and isolated from the charger.
case I had in mind. I needed two switch-mode This means it is not possible to both use and
converters—one to step the battery voltage up charge the probe. This was a deliberate choice
to +5 V and another to create the -5 V rail. on my part to keep the modes completely
There we a few ways to do this, but I figured I separate and encourage me to keep my bench
could not be the first person with the need for as clear as possible.
dual S V supplies from a single IWo cell. Testing shows the circuit can achieve
After a few hours an various manufacturer 3 hours and 45 minutes of operation on a full
websites, I came across the 1P565133 from charge with the 800 cM-hours LiPo I used.
TI, which fit the bill perfectly. This nice Charging takes a couple of hours on the high-
little chip accepts a 2.9 to 5.0 V input and current setting, and about 6 hours on the
produces ±5V rails at up to 250 mA. It is 92% low-current setting. You could substitute an
efficient at 100 MA. It requires only a couple 18650 eel If you reconfigure the mechanical
design, which should more than double both
the running and charging times.
For diitaAetl arIide re(ere,ceq and •ddltioaM resources go to:
www.clicullcall3f.tom/artid2-Mterials CONSTRUCTION
I built my probe on a double-sided printed
RESOURCES PCB, sized to fit a Hammond Industries 1593X
handhold case, measuring 66 W mm x 240 1
AiLj )r. ,t I v.wvandoq.con,
mm it 28 D civ,,. Figure 3 shows a vIew of
I4axin integrated I wwsttnaxiniintegrted. the case. Two 4 mm banana input sockets
protnide through one end of the case, and
Texas Mstrurnent. I wwaMcufn the 81K output connector and 158 MinI-B
connectors protrude through the other end. noodle
The power/range switch is on the top of the mc tie ciled once.
tW n p,.L lwo!d'rcc
case, which also houses two off-the-shelf
Pvi bit. 4mdfl.n
light-pipes for the LED indicators. The label to the left s * the
was made using a laser printer label and (vp oi the Ie flea ec OK
transparent sticky plastic film. A pill of this n.dc.
artwork is available on the Circuit Cellar code thtpMtthottrIgtt..wIaQy(ftm
& files download webpage. tfic rthgocofly.
The board layout Is critical. If you Intend
to do this yourself, you must keep the Input
attenuator symmetrical and observe the
manufacturer's layout guidelines for the
A0A4817s, which will happily oscate at
250 lutz given half a chance. Trust me, I
learned this the hard way. Use short traces,
use the special ieedback output pin and do
not use a ground plane in this area. You should
also take care with the layout of the DC-DC
converter, keeping loops small and the whole
lot far from the sensitive analog circuitry.
mpw. 4 shows the completed circuit board
in the case.
Assembly was straightforward, with the
DC-CC converter chip being the only leadless
part that takes a bit of care to solder by hand.
I stuck with 0805 and larger components
where possible, to make things a bit easier
for myself.

TESTING AND CALIBRATION

Once you have built the differential probe,
you need to go through a simple calibration
and testing procedure.

1.Check that the AS V supplies are present

and at the right value when the power S. Adjust the frequency compensation, teed
switch I, In the xlO or xlQO position. The a 1 lIlt square wan into the positive
power LW should be lit. Make all the tests input with respect to ground. Crank up the
with the power on. amplitude on your signal generator as far as
2.Temporarily short C13, to eliminate the it will go. Set the probe to the xlO setting.
effect of the offset adjustment on the input Connect your oscilloscope to the probe via
attenuator. a BPIC-to-BNC cable. Ensure the scope Is
3.Adjust thSCMRR. Connect a high but safe DC on the high-impedance setting and any
voltage between both Inputs and ground. bandwidth Inking Is off. You should now
I used 60 V from my *30 V bench supply. be able to trigger on the square wave and
Connect a digital rnultimete. between Till adjust the conipsation trimmer VC1 (or
and 192. Adjust YRI (OIRR) to null the optimum compensations just as you would
voltage between these inputs as close to compensate a standard xlO probe. The
zero as possible. You should be able to get correct compensation is achieved when the
down below 60 iv (-120 d6) with a bit of ris?ng edge of the square wave shorn no
care. oers1,oa or undershoot. Use a non-qnetallc
4.Adjust the DC offset. Connect the voltmeter tool to make this adjustment. Repeat the
between 195 (the output) and ground. process for the negative input and VU.
Remove the short from C13, connect the
two inputs together and adjust VR2 (Offset) CONCLUSION
for the lowest possible output voltage. I found designing and building this project
You will need to switch between ranges very satisfying. The opporttmity to design a
frequently to dial in the best compromise. project that does not includes microcontro$er
It will be unlikely you can get to zero on and required me to dust off my analog design
both ranges, but you should be able to get skills was a welcome change. The end result is
below *2 my on each without too mud, a useful ir,stnanent that exactly meets my
trouble. needs and Is In regular use on my bench. C-