B.

TECH/ECE/6TH SEM/ECEN 3201/2019

DIGITAL VLSI DESIGN

(ECEN 3201)

Time Allotted : 3 hrs Full Marks : 70

Figures out of the right margin indicate full marks.
Candidates are required to answer Group A and
any 5 (five) from Group B to E, taking at least one from each group.
Candidates are required to give answer in their own words as far as
practicable.
Group – A
(Multiple Choice Type Questions)

1. Choose the correct alternative for the following: 10 × 1 = 10

(i) VLSI technology uses ________ to form integrated circuit
(a) transistors (b) switches
(c) diodes (d) buffers
(ii) In Pseudo-nMOS logic, n transistor operates in
(a) cut off region (b) saturation region
(c) resistive region (d) linear region.
(iii) According to Moore’s Law, Number of Transistor per chip gets
doubled in
(a) 12 Months (b) 18 Months
(c) 24 Months (d) 30 Months.
(iv) Latest Integration Technology is
(a) LSI (b) VLSI
(c) ULSI (d) GSI.
(v) The noise immunity ____________ with noise margin
(a) increases (b) decreases
(c) remains constant (d) remains independent
(vi) Stick diagrams are those which convey layer information through
(a) thickness (b) colours
(c) layers (d) shapes.
(vii) Value of “Lambda” in 130nm Process Node is
(a) 130nm (b) 65nm
(c) 180nm (d) 100nm.
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B.TECH/ECE/6TH SEM/ECEN 3201/2019 B.TECH/ECE/6TH SEM/ECEN 3201/2019
(viii) BDD is used in 5. (a) Draw Layout of CMOS inverter using Standard Cell Layout Topology
(a) High Level Synthesis (b) Logic Synthesis and show all the layers.
(c) Floorplan (d) Routing.
(b) What is the difference between “Micron based Design Rule” and
(ix) KL Algorithm is related to “Lambda Based Design Rule” ?
(a) Routing (b) Partitioning
(c) Draw schematic and Stick Diagram of 2 input NAND gate.
(c) Logic synthesis (d) High level synthesis.
4 + 3 + 5 = 12
(x) ATPG stands for
(a) Advanced Test Pattern Generator Group - D
(b) Active Test Pattern Generator
(c) Automatic Test Pattern Generator 6. (a) What do you mean by Bit Swizzling? State with example the types of
(d) Both b and c. circuit modelling using HDL.
(b) Write an HDL module for a 2:4 decoder.
Group - B
(c) Discuss the limitations of RTL synthesis.
(2 + 4) + 4 + 2 = 12
2. (a) What are the differences between Full Custom Design and Std Cell
based Semi Custom Design ?
7. (a) Write the verilog code for a 4-bit counter.
(b) Draw Circuit Diagram of 2 input XOR gate using CMOS Logic.
(b) Write a verilog program for a Moore machine.
(c) Draw Circuit Diagram of 2 input XOR gate using CMOS Transmission
(c) What is compaction?
Gate (TG).
4 + 6 + 2 = 12
4 + 4 + 4 = 12
Group - E
3. (a) Draw Voltage Transfer Characteristic curves of a CMOS inverter for
kr = 0.5, 1 and 3 in the same graph. Briefly explain the differences in 8. (a) Find the test vector of the following circuit using D-algorithm. Write
the three curves. the logic statements clearly.
(b) Draw the CMOS circuit of the expression Y= { A(B  C )}  D . Calculate
the logical effort for all the inputs.
(c) Implement a 4- input AND gate using Domino logic.
(2 + 2) + 4 + 4= 12
(b) What do you understand by transistor fault? Write the truth –table
Group - C for the fault-free and faulty Nor gate considering all the MOS-
components are at stuck on and stuck off fault one at a time.
4. (a) Draw Circuit Diagram of a D-Latch using CMOS Transmission Gate (TG).
(c) What is path delay fault?
(b) Draw Circuit Diagram of a Positive Edge Triggered D-Flip Flop using 5 + 5 + 2 = 12
D-Latch.
(c) Explain Euler Path solution of a CMOS gate which represents 9. (a) Discuss the different types of bridging faults with the help of
function f = (AB+C) ! (! Means Bar) and draw Stick Diagram of the necessary diagrams.
same CMOS gate based on Euler Path Solution. (b) Design the block diagram of a test generator for a 4K×32 static RAM.
3 + 3 + (3 + 3) = 12 6 + 6 = 12
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