Optimizing your automotive system with Jacinto™ 7

SoCs and MCU integration

Eric Best
Texas Instruments
Jacinto™ 7 SoCs
TDAx DRAx
SoC family SoC family

Common IP, software & Tools

Safety & Security
ADVANCED DRIVER
ASSISTANCE SYSTEMS

Front Camera Driver Monitoring Integrated Cockpit Digital Cluster

Surround View CMS / Mirror Replacement Center Stack HMI Heads-Up Display

Sensor Fusion / Domain Lidar / Time of Flight Silverbox V2V / V2X

Radar Rear Camera Rear-seat Vehicle compute, Gateway

2
T D A4 V - M I D
Integrated Safety MCU

Processing Cores
High Speed Interconnect 16nm Auto • 2x ARM Cortex A72 @ 2GHz
• 1x C71x DSP + MMA @ 1GHz
Vision Processing ACC • 2x C66 DSP @ 1GHz
+
*
-
Safety MCU • Up to 8 MB Shared on-chip memory w/ECC
C66 MMA ISP NF • 3x ARM Dual Cortex R5F dual/lock-step
scalar ARM R5F
ARM R5F
C66
DSP C7x + ARM R5F • Vision Acceleration – VISP, VPAC, DOF, SDE
ARM A72
ARM R5F
ARM A72
DSP
vector
MMA ARM R5F REMAP MSC • 1x GE8430 GPU (100 GFLOPS)
ARM R5F
ARM R5F
ARM R5F
Video / Vision
Depth & Motion PAC
• 2x CSI-2 (4 lane) x 2.5Gbps Camera interface
Multicore Shared DOF CRC • 1x CSI-2 TX Output interface
8 MB L3 RAM w/ECC STEREO
Memory Controller ESM • Multiformat encode/decode (H.264 Encode up to 180 MP/s for 1080P)
• DSS: Scale, Blend, Convert
RTI • 1x 2.5K, 1x 4K Display OTF composition, increased number of

Power & FFI Isolation

LPDDR4 GPU layers/flexibility
4266 32b GE8430 DCC • 4L DSI interfaces
BIST
DDR SUBSYSTEM w/ ECC Memory IO
Display SubSystem 2x ADC 12b • 1x 32b LP-DDR4X-4266
Video Acceleration • 1x MMC/SD/SDIO: 1x UHSI 4b, 1x eMMC v5.1
2K Blend DSI 1 MB 1x SDIO 4b SD s4.0, SATA: 1 lane
Video Video Scale SRAM • 1x OSPI (166 MHz SDR / 80MHz DDR) / 1x HyperBus™
Encode Decode Convert OTF CPZ
2x CAN-FD
High-Speed IO
• 4x PCIe Gen 3, USB3.1, USB2.0
SYSTEM SERVICES OSPI / 2xQSPI
EDMA MMU Mailboxes 3 PWM WDT GPIOs Spinlock Timers Security** Automotive IO
Hyper Flash • 16x CAN Controllers supporting CAN A&B, FD
• 8 Port Ethernet Switch
Capture / MIPI Vehicle connectivity Serial connectivity GEMAC
Safety
2x CSI2 4L RX MMC/ McSPI McASP
2.5 Gbps 4x PCIe 2DL USB2/3 X1 I2C, UART, • Up to ASIL D safety MCU
SD x1 x8 x12 SPI, GPIO • High Security** Version
CSI2 4L TX 8 Port eAVB UART I2C Package: 24x24mm BGA, 0.8mm pitch
2.5 Gbps SW 14x CAN FD GPMC x10 x7 Scratch
Power Dissipation Typical Range: 12 to 20W @ 125CTj

3
History of TI’s Integrated Safety MCU
Mature IP
• The MCU island leverages mature core and peripheral IP blocks (R5F, UART, SPI, RAM,ECC, DCC, etc) ,which are all well proven
on many devices within TI’s broad family of SoC’s.

ASIL D Heritage
• The MCU island is technology based on TI’s HerculesTM TMS570 stand-alone Safety MCU family, which has shipped millions of
automotive units over 15+ years. These devices are TÜV SÜD certified IEC61508 SIL3 and ISO26262 ASIL D microcontrollers for
automotive and industrial applications. TI is leveraging the same safety concept and ISO26262 design methodology in TDA4. See:
http://www.ti.com/microcontrollers/hercules-safety-mcus/overview.html

Robust Safety Case

• The MCU Island is already available on several 28nm processor derivatives addressing applications with heavy functional safety
requirements. The IP is validated, robust and delivering performance to spec.
• Safety documentation, MCAL, and AUTOSAR availability.
• AUTOSAR (R5F) and Adaptive AUTOSAR (A53) demo first shown on DRA804M at CES19.

Family Approach
• The Jacinto DRA82XX/TDA4x family of devices leverages the same IP in the 16FF process node, enabling software re-use and
scalability for functional safety with superset device first sampled in May 2019.

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Vehicle MCU requirements increasing over time
• Increased compute power, to satisfy higher compute needs
of complex software

• Increased embedded flash memory size to handle more

complex software.

• Increased high speed memories to accommodate large TI’s solution is to integrate the vehicle MCU
software (both data and instructions) Lower Cost

• Increased shared data with the system application Smaller Board Area
processor Higher Performance/Watt

• Multiple Ethernet ports to support multiple networks Higher CPU and Memory Capacity

• Greater number of I/O interfaces (such as CAN, LIN, ADC,

etc…)

• Up to ASIL-D safety support to meet the system safety

goals

• Autosar for integrated MCU

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Summary – External MCU vs TDA4 MCU integration
Features External MCU TDA4x MCU Integration
Microcontroller cores limited by embedded FLASH access Higher performance cores executing from RAM
Processing cores
time. Typically 300MHz max with proper wait states Multiple R5F cores @1GHz

IO support CAN, ADC, SPI, GPIO, PMW, Ethernet, I2C CAN, ADC, SPI, GPIO, PMW, Ethernet, I2C
Meets system level low power requirements.
Power Meets low-standby current Companion PMIC includes functionality to manage standby
current.

Wake-ups Large number of wakeup sources Multiple options to support wakeup sources

Provides significant system BOM saving due to integration of

System BOM Cost related to flash size, functional safety requirement etc.
external MCU and decreased PCB area
Can meet 50-100ms boot time for CAN response.
Boot Can meet 50-100ms boot time for CAN response • 30mS general purpose
• 42mS secure

Software development Separate software development kits Unified software development with application processor

External flash (QSPI, OSPI, Hyperflash)

Flash Internal flash XIP Supported. Can support cost effective larger external
flash
Apps processor
Serial port (i.e. SPI, I2C etc.) 128 bit wide internal bus interface with end to end ECC
communication

Up to ASIL-D, simplifies safety case for mixed criticality

Functional safety Up to ASIL-D
applications.
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Integration in TDA4
Typical ECU architecture Integrated micro with TDA4 - ECU architecture
PMIC VBATT PMIC VBATT
DC/DC DC/DC
Vcc + Reset Vcc + Reset
Vcc + reset Vcc + reset MCU
processor processor
MCU
TDA4 SoC
Application Processor MCU CAN
CAN
Transceiver CAN

Freedom from interference

CAN
Transceiver
ETH Main MCU
SPI RGMII
ETH
Transceiver Domain Island RGMII

Vehicle Bus
Transceiver

Vehicle Bus
Timer
Safe IPC PWM DAC
PWM DAC
GPIO
ADC Sensors
Internal ADC
Sensors
Flash GPIO
GPIO OSPI
EMIF CAN CANFD External
External WDG
WDG
EMIF
Sensors Sensors
DDR Flash
Sensors Flash Sensors
DDR Flash

Lower system BOM Parity with external micro

Safety and isolation Simplifies HW and SW arch

TDA4 MCU Island
Peripherals for vehicle and other External flash with 12 bit ADC ROM and Efuse Internal 12 MHz RC OSC
ECU component connectivity – SPI, on-the-fly security for Timers/RTI for memory for for fail safe mode
CAN, ETH, UART and ECC monitoring monitoring code and data
Temperature
monitor and internal

Voltage and Power

DMA engine for monitor
peripherals
DMSC
Resilient interconnect Separate power,
security and resource
manager. With Cortex
MCU safety DTK M3, internal memory,
clock monitoring AES accelerator
Error Signaling Module
On chip PBIST and
LBIST Primary OSC for
external crystal

Logical Modules for Security LockStep R5F with Wakeup, ESM, GPIO,
boundary of DMA, CRC and accelerator – AES, cache, internal UART and I2C for peripheral
MCU Island interrupt mgmt DES, PKA, SHA TCM, MPU communication and wakeup 8

Safety & Security Connectivity Power Performance

AUTOSAR highlights
AUTOSAR available now from multiple suppliers

• Vector and KPIT official releases in Q1’20

Multiple R5F subsystems allow for flexible architecture

• AUTOSAR on one pair, or across multiple pairs with core partitions

High capacity cores for large headroom

• 2-3x capacity of typical external MCU

• Up to 6GHz of R5F processing
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Vector AUTOSAR pre-integration on TDA4x
Vector TDA4 AUTOSAR eval package in definition today
DEMO APPLICATION •Subset of available AUTOSAR features to enable basic application
•Includes AUTOSAR OS for R5F, limited set of integrated MCAL drivers
VECTOR •MCAL drivers from Vector or from TI SDK
AUTOSAR
EVAL TI Linux and TI RTOS on processing cores
TI RTOS TI LINUX MCAL DRV •Enables quick path to Vector AUTOSAR evaluation

Simple AUTOSAR communication DEMO app in definition

TI TDA4 EVM
•Easily re-created by customers with SW packages from Vector and TI
AUTOSAR evaluation on TI EVM

Enabling Customer Eval on TDA4x – In work

Customer requests 1. Acquire Jacinto 7 Build instructions for
AUTOSAR Eval on processor EVM from TI AUTOSAR Eval from TI
Jacinto 7 processor 2. Download TI SDKs BEGIN customer
to Vector and TI AUTOSAR Eval on
Jacinto 7 processor
• Customer gets AUTOSAR Eval
bundle + license from Vector
KPIT AUTOSAR pre-integration on TDA4x

AVAILABLE
TODAY

AUTOSAR Classic
• Gateway (CAN TO ETH) on R5F Cluster (Main Domain)
• AUTOSAR Classic on R5F (Safety Island)
Adaptive AUTOSAR on A72
• OTA
• V2X stack and applications integration with Adaptive
• Onboard diagnostics services 11

IPC communication between Classic/Adaptive

Foundational Software | MCU Software
TI SDK
• Part of Processor SDK RTOS Automotive MCU Demos
without

Boot loader
SYS BIOS
• TI deliverables enable prototyping with MCAL and without AUTOSAR AutoSAR

PDK:
Complex Device
– Inter-Core communication using mailbox and SPI Drivers IPC
MCAL RTOS SDK HLOS SDK
– Routing/switching over CAN and Ethernet
PDK
– Reference bootloader for fast boot, XIP execution
– Other MCU functionality like ADC, PWM in application context Cortex R5F (MCU SS and/or Main SS) R5F, DSP, A72/53
– Measure CPU load / latency
• AutoSAR integration of TI MCAL available with most AutoSAR vendors
– Multi-core AutoSAR support also available
Applications TI SDK
• MCAL and Complex Device Driver (CDD) delivered by TI integrated
– ADC, CAN, ETH, ETHTRCV, GPT, PWM, SPI, DIO, WGT Run-time Environment with AutoSAR
– CDD: IPC (Inter Processor Communication) Services
– EB Configurator tool

AutoSAR OS
Complex

Boot loader
ECU Abstraction Device

PDK:
• TI MCAL support for functional safety IPC
Drivers
– TI MCAL developed with process certified to be compliant with RTOS SDK HLOS SDK Customer
MCAL
ISO 26262 2018. PDK
AutoSAR Vendor
– TI MCAL provided with Compliance Support Package
R5F, DSP, A72/53
TI SDK
Cortex R5F (MCU SS and/or Main SS)
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Customer SW architecture – recommended mapping for MCU/Main R5F
Customer Application

AUTOSAR

R5F Subsystem
MCU Domain

TCM CACHE

TCM OCM MSMC DDR XIP

• > 32MB XIP
64-128 KB • 512KB – • 1-2 MB MSMC
• >512 MB DDR
1MB as OCM
Code: Frequency of execution: Code: Frequency of execution: Code: Frequency of execution:
HIGH (ISR, Vector table, most MID (send/receive APIs of drivers LOW: (Initialization, status checks,
frequently executed code): <32KB and COM stack, OS): <512 KB safety checks) : 7MB

Data: Frequency of execution: Data: Frequency of access: Data: Frequency of access:

HIGH (stack), working buffers for MID (gateway tables, Buffers ) LOW (Initialization structures,
signal routing :<32KB < 250KB Buffers ) : 1.75 MB
TDA4 R5F 1x1GHz performance vs 4x300MHz Flash MCU
1 x lockstep R5F of TDA4 compared to
4 x lockstep cores of non-TI highest
TI TDA4 performing MCU
Typical Flash MCU
1 pair x R5F in Lockstep@ 1GHz ~ 2K DMIPs 4 pair cores in lockstep @ 300MHz ~ 2.4K DMIPS

AUTOSAR benchmark on TDA4 R5F Estimated AUTOSAR benchmark on Other MCU

Setup: RTOS, 16 task, I$ miss rate: 3.5M/sec Setup: RTOS, 16 task, I$ miss rate: 3.5M/sec
•DRA82x baseline MCU R5F
•R5F cache size (32KB) • Baseline configuration: Other MCU • Baseline configuration: Other MCU MCU R5F
•TCM 64KB have similar cache and TCM config OCM XIP have similar cache and TCM config
• Baseline performance: The time • Latency slightly better than TI as they
OCM XIP
taken to execute the benchmark 1 1.8 operate at lower frequency
code is normalized as 1 for OCM • Flash latency similar to OCM latency
0.7 0.8
RAM No for code access 30%
impact
degrade
•Performance impact due to
multiple core • No Impact • Impact of 30% due to function split
1 1.8 into multiple cores (Amdahl’s law) 0.91 1.04

Frequency of access
Frequency of access
• Code with higher frequency 75% 25% • Code with higher frequency
•SW Architecture – Code of access in TCM and OCM of access in TCM and OCM 75% 25%
RAM : 75% RAM : 75%
placement, DMA • Code with lower frequency of
1.2
•Lockstep TCM: 64 -> 128KB access in Flash/XIP 20% performance 1.0
degradation compared Similar performance
to OCM code execution compared to OCM code
execution
• 1 x lockstep R5F pair has XIP performance just 20% worse than 4 x lockstep cores
(highest performing external MCU)
• TI TDA4x has up to 3 x R5F lockstep cores: ~ 2.5x more performance than typical
high performing MCU
Software and tools - overview
AUTOSAR Bootloader Code Emulators
MCAL + Composer
Configurator Studio HW emulator for easy
QM Bootloader given as debug from multiple
ASIL D capable MCAL reference for device Code Composer Studio™ vendors- Spectrum Digital,
for AUTOSAR BSW boot sequence and IDE is an Eclipse-based BlackHawk, Lauterbach
integration operation development environment

Diagnostic Reference HW
Library MCU PDK Compiler Simulation
platform
ASIL D capable SW Reference PDK SW TI Compiler for various
diagnostic library for demonstrating MCU Island cores of MCU Island – VLAB SoC Simulator
checking the correctness operation and interaction used with CCS or from ASTC
of all checkers with Main Domain command line

Low level Compiler TI partner

Flash Network
Drivers Qualification
Programming
toolkit
ASIL D low level drivers Extensive 3P network for
Flash programming tool for AUTOSAR, Safety OS,
for peripherals, power Qualification tool kit for
external flash using Hypervisor, Services,
management and device meeting safety
standard interface Application
control requirements

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TI TDA4A MCU benefits
TDA4x for mainstream ADAS Safety Best cost of ownership
• Native Safety Support • Lower BOM with integration of safety MCU
– ASIL-D Systematic Capability
– Internal diagnostics (up to ASIL-D) • Reusable: Common micro and SW platform from L1 
– Certification and collateral L4, gateway/vehicle compute, cockpit
• Mixed Criticality • High performance MCU subsystems
– Firewalls, Voltage, Clocks, Interconnect
• Architected for lowest external DDR footprint
• MCU island
– High FFI • Low power to reduce thermal management costs
– External MCU replacement

• Extended MCU Automotive heritage

– More ASIL-D DMIPS
– DDR • TDA4x leverages TI’s extensive history in automotive
processors (15+ years across 35 OEMs, over 250
Lowest risk Munits)
• Proven technology node; reliable execution  • Automotive Safety heritage: Over a decade experience
development can start today! with ASIL-D processing (TMS570)
• TDA4x backed by a team of 600+ TI engineers & domain • System level solutions designed for Automotive: SoC,
experts interface and power
• Proven support in Automotive
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SLYP698
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