DIGITAL

SYSTEM
DESIGN
LAB
MANUAL

Verilog Programming

Madhu Babu.M
M.Tech(VLSI System Design)

Under the Guidance of

Dr. K. Rama Naidu
M.Tech, PhD(KGP)
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

DIGITAL SYSTEM DESIGN LAB MANUAL

(USING VERILOG HDL LANGUAGE)

M.TECH. I YEAR I SEMESTER (D.S.C.E & D.E.C.S)

JNTU COLLEGE OF ENGINEERING (AUTONOMOUS):: ANANTAPUR

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

ANANTAPUR-515 002. (A.P) INDIA

1
LIST OF PROGRAMS :

CYCLE 1:

1. Simulation and Verification of Logic Gates.

2. Design and Simulation of Half adder, Serial Binary Adder, Multi
Precession Adder, Carry Look Ahead Adder and Full Adder.
3. Simulation and Verification of Decoder, MUXs, Encoder using all
Modeling Styles.
4. Modeling of Flip-Flops with Synchronous and Asynchronous reset.
5. Design and Simulation of Counters- Ring Counter, Johnson Counter,
and Up- Down Counter, Ripple Counter.
6. Design of a N- bit Register of Serial-in Serial-out, Serial in Parallel out,
Parallel in Serial out and Parallel in Parallel Out.

7. Design of Sequence Detector (Finite State Machine- Mealy and Moore

Machines).
8. 4- Bit Multiplier, Divider. (for 4-Bit Operand)
9. Design ALU to Perform – ADD, SUB, AND-OR, 1’s and 2’s
COMPLIMENT, Multiplication, Division.

CYCLE 2: After completing cycle 1, Digital Circuit Description Using

Verilog/ VHDL.

1. Verification of the Functionality of the circuit using function

Simulators.
2. Timing Simulator for Critical Path time Calculation.
3. Synthesis of Digital Circuit.

4. Place and Router Techniques for FPGA’s like Xilinx, Altera, Cypress,
etc.,
5. Implementation of Design using FPGA and CPLD Devices.
2
Program 1:

Aim: To Simulate And Verify Of Logic Gates Operation.

Software Required: Active HDL 6.3 Version, Xilinx Web Pack.

(a) AND GATE:

Input Input Output
Data(A) Data(B) Result(y)

0 0 0

0 1 0

1 0 0
Fig: Symbolic Representation
1 1 1

Table: Represents Normal AND GATE Operation.

Verilog Primitive AND GATE

Output
Input Data(B)
(Y)

0 1 x z

0 0 0 0 0
Input
1 1 X X X
Data(A)
X X X X X

Z X X X X

Table: Represents Primitive AND GATE Operation.

Considering Positive Logic (Negative Logic):

„0‟ represents Low level (High Level).

„1‟ represents High level (Low level).
„X‟ represents undefined level.
„Z‟ represents High impedance state.
3
(b) OR GATE:

Input Input Output

Data(A) Data(B) Result(y)

0 0 0

0 1 1

Fig: Symbolic Representation 1 0 1

1 1 1

Table: Represents Normal AND GATE Operation.

Primitive OR GATE

Output
Input Data(B)
(Y)

0 1 X Z

0 0 1 X X
Input
1 1 1 1 1
Data(A)
X X 1 X X

Z X 1 X X

Table: Represents Primitive OR GATE Operation.

Considering Positive Logic (Negative Logic):

„0‟ represents Low level (High Level).

„1‟ represents High level (Low level).

„X‟ represents undefined level.

„Z‟ represents High impedance state.

4
(c) NOT GATE: Input Output
Data(A) Result(y)

0 1

1 0

Table: Represents normal NOT GATE Operation.

Primitive NOT GATE

Output
Output (Y) Result
(y)

Input Data(A) 0

0 0

1 1

X X

Z X

Table: Represents Primitive NOT GATE Operation.

Considering Positive Logic (Negative Logic):

„0‟ represents Low level (High Level).

„1‟ represents High level (Low level).

„X‟ represents undefined level.

„Z‟ represents High impedance state.

5
(d) NAND GATE:

Input Input Output

Data(A) Data(B) Result(y)

0 0 1

0 1 1

1 0 1
Fig: Symbolic Representation
1 1 0

Table: Represents Normal NAND GATE Operation.

Primitive NAND GATE

Output
Input Data(B)
(Y)

0 1 X z

0 1 1 1 1
Input
1 1 0 X X
Data(A)
X 1 X X X

Z 1 X X X

Table: Represents Primitive NAND GATE Operation.

Considering Positive Logic (Negative Logic):

„0‟ represents Low level (High Level).

„1‟ represents High level (Low level).

„X‟ represents undefined level.

„Z‟ represents High impedance state.

6
Input Input Output
(e) NOR GATE:
Data(A) Data(B) Result(y)

0 0 1

0 1 0

1 0 0

Fig: Symbolic Representation 1 1 0

Table: Represents Normal AND GATE Operation.

Primitive NOR GATE

Output
Input Data(B)
(Y)

0 1 X Z

0 1 0 X X
Input
1 0 0 0 0
Data(A)
X X 0 X X

Z X 0 X X

Table: Represents Primitive NOR GATE Operation.

Considering Positive Logic (Negative Logic):

„0‟ represents Low level (High Level).

„1‟ represents High level (Low level).

„X‟ represents undefined level.

„Z‟ represents High impedance state.

7
(f) XOR GATE:

Input Input Output

Data(A) Data(B) Result(y)

0 0 0

0 1 1
Fig: Symbolic Representation
1 0 1

1 1 0

Table: Represents Normal XOR GATE Operation.

Primitive XOR GATE

Output
Input Data(B)
(Y)

0 1 X Z

0 0 1 X X
Input
1 1 0 X X
Data(A)
X X X X X

Z X X X X

Table: Represents Primitive XOR GATE Operation.

Considering Positive Logic (Negative Logic):

„0‟ represents Low level (High Level).

„1‟ represents High level (Low level).

„X‟ represents undefined level.

„Z‟ represents High impedance state.

8
(g) XNOR GATE:

Input Input Output

Data(A) Data(B) Result(y)

0 0 1

0 1 0

1 0 0
Fig: Symbolic Representation
1 1 1

Table: Represents normal XNOR GATE Operation.

Primitive XNOR GATE

Output
Input Data(B)
(Y)

0 1 X Z

0 1 0 X X
Input
1 0 1 X X
Data(A)
X X X X X

Z X X X X

Table: Represents Primitive XNOR GATE Operation.

Considering Positive Logic (Negative Logic):

„0‟ represents Low level (High Level).

„1‟ represents High level (Low level).

„X‟ represents undefined level.

„Z‟ represents High impedance state.

9
Verilog HDL Code:

//-------------------------------------------------------------------------------------------

// Title : Logic Gates

// Design :Madhu
// Author : Madhu
// Company : JNTU
//-------------------------------------------------------------------------------------------

// File : logic_gates.v
// Generated : Thu Oct 29 23:04:06 2009
// From : interface description file
// By : Itf2Vhdl ver. 1.20
//-------------------------------------------------------------------------------------------

// Description :
//-------------------------------------------------------------------------------------------

`timescale 1 ns / 1 ps //used for representing time unit.

module logic_gates ( a ,b , c, d, e, f, g, h, i );
input a, b;
output c, d, e, f, g, h, i ;
wire a ,b;
wire c, d, e, f, g, h, i;
/*
assign c = a & b, //And operation
d = a |b, //OR operation
e = ~a, //NOT operation
f = ~(a & b), //NAND operation
g = ~(a | b), //NOR operation
h = a ^ b, //XOR operation
i = ~(a ^ b); //XNOR operation
*/
and U1(c,a,b); //Using Verilog Primitive
or U2(d,a,b); //Using Verilog Primitive
not U3(e,a); //Using Verilog Primitive
nand U4(f,a,b); //Using Verilog Primitive
nor U5(g,a,b); //Using Verilog Primitive
xor U6(h,a,b); //Using Verilog Primitive
xnor U7(i,a,b); //Using Verilog Primitive

endmodule
10
Output Waveforms:

Synthesis Report:

(a) Final Report Results:

RTL Top Level Output File Name : logic_gates.ngr

Top Level Output File Name : logic_gates
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 9
Cell Usage :
# BELS :7
# INV : 1
# LUT2 :6
# IO Buffers : 9
# IBUF :2
# OBUF :7

(b) Device utilization summary:

Selected Device : 3s50pq208-5

Number of Slices : 4 out of 768 0%
11
Number of 4 input LUTs : 7 out of 1536 0%
Number of IOs :9
Number of bonded IOBs : 9 out of 124 7%

(c) Timing Summary:

Speed Grade : -5
Minimum period : No path found
Minimum input arrival time before clock : No path found
Maximum output required time after clock: No path found
Maximum combinational path delay : 7.985ns

RTL Schematic View:

Fig: Block Diagram

Fig: Internal circuitry

Result:

Hence simulation, verification of logic gates operation is done successfully

and relevant RTL schematic, delays are observed after synthesis.
12
Program 2:
Aim: To Simulate and Verify Half adder, Serial Binary Adder, Carry Look
Ahead Adder and Full Adder.
Software Required: Active HDL 6.3 Version, Xilinx Web Pack.

(a) Half Adder:

Fig: Circuit diagram

Verilog HDL Code:

`timescale 1ns/1ps
module half_adder(sum,carry,a,b);
input a,b;
wire a,b;
output sum,carry;
wire sum,carry;
assign sum = a ^ b,
carry = a&b;
endmodule
Output Waveform:
13
(b) Serial Binary Adder:
Verilog HDL Code:

`timescale 1 ns / 1 ps
module serial_add ( a ,cin ,b ,cout ,s );
input [3:0] a, b ;

wire [3:0] a, b ;
input cin ;
wire cin ;
Fig: Block Diagram
output cout ;
wire cout ;
output [3:0] s ;
wire [3:0] s, c ;
assign s[0]=a[0] ^ b[0] ^ cin;
assign c[0]=(a[0] & b[0])|(b[0] & cin)|(cin & a[0]);
assign s[1]=a[1] ^ b[1] ^ c[0];
assign c[1]=(a[1] & b[1])|(b[1] & c[0])|(c[0] &
a[1]); assign s[2]=a[2] ^ b[2] ^ c[1];
assign c[2]=(a[2] & b[2])|(b[2] & c[1])|(c[1] &
a[2]); assign s[3]=a[3] ^ b[3] ^ c[2];
assign c[3]=(a[3] & b[3])|(b[3] & c[2])|(c[2] &
a[3]); assign cout=c[3];
endmodule
Output Waveform:
14
(c) Carry Look Ahead Adder:

Fig: Block Diagram Of Carry Look Ahead Adder.

Fig: Circuit Diagram Of Carry Look Ahead Generator.

15
Verilog HDL Code:
Data Flow Model:
//------------------------------------------------------------------------------------------
-
// Title : clah1
// Design : Madhu
// Author : ECEDEPT
// Company: JNTUCEA

//-------------------------------------------------------------------------------------------
// File : clah1.v
// Generated : Thu Nov 12 14:13:36 2009
// From : interface description file
// By : Itf2Vhdl ver. 1.20
//-------------------------------------------------------------------------------------------
// Description :
//-------------------------------------------------------------------------------------------
`timescale 1 ns / 1 ps
module clah1 ( a ,cin ,b ,cout ,sum );
input [3:0] a,b ;
wire [3:0]
a,b ; input cin
; wire cin ;
output cout ;
wire cout ;
output [3:0] sum ;
wire [3:0] sum ;
wire p0,p1,p2,p3,g0,g1,g2,g3,c0,c1,c2,c3;
assign p0= a[0]^b[0];
assign p1= a[1]^b[1];
assign p2= a[2]^b[2];
assign p3= a[3]^b[3];
assign g0=a[0]&b[0];
assign g1=a[1]&b[1];
assign g2=a[2]&b[2];
16
assign g3=a[3]&b[3];
assign c0=g0|(p0&cin);
assign c1= g1|(p1&(g0|(p0&cin)));
assign c2= g2|(p2&(g1|(p1&(g0|(p0&cin)))));
assign c3= g3|(p3&(g2|(p2&(g1|(p1&(g0|(p0&cin)))))));
assign sum[0]= p0^cin;
assign sum[1]= p1^c0;
assign sum[2]= p2^c1;
assign sum[3]= p3^c2;
assign cout=c3;

endmodule

Behavioral Model:
`timescale 1 ns / 1 ps
module clahadder ( a ,cin ,b ,cout ,sum );
input [3:0] a,b ;
wire [3:0]
a,b ; inout cin
; wire cin ;
output cout ;
reg cout ;
output [3:0] sum ;
reg [3:0] sum ;
wire [3:0] p, g;
integer i;
always @ (a or b or cin)
begin
for(i=0;i<4;i=i+1)
begin
p[i]= a[i]^b[i];
g[i]=a[i]&b[i];
cout=g[i]|
(p[i]&cin);
sum[i]=p[i]^cin;
17
cin=cout;
end
end
endmodule

Output Waveform:
18
(d) Full Adder:

Verilog HDL Code:

`timescale 1ns/1ps
module full_adder(a,b,c,sum,carry);
input a,b,c;
wire a,b,c;
output sum,carry;
wire sum,carry;
wire s1,c1,c2;
half_adder H1(s1,c1,a,b);
half_adder H2(sum,c2,c,s1);
or O1(carry,c1,c2);
endmodule

Output Waveforms:
19
Synthesis Report:

(a) Final Report Results:

RTL Top Level Output File Name : full_adder.ngr
Top Level Output File Name : full_adder
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :2
# LUT3 :2
# IO Buffers :5
# IBUF :3
# OBUF :2

(b) Device utilization summary:

Selected Device : 3s50pq208-5
Number of Slices :1 out of 768 0%
Number of 4 input LUTs : 2 out of 1536 0%
Number of IOs :5
Number of bonded IOBs : 5 out of 124 4%

(c) Timing Summary:

Speed Grade : -5
Minimum period : No path found
Minimum input arrival time before clock : No path found
Maximum output required time after clock: No path found
Maximum combinational path delay : 7.824ns
20
RTL Schematic View:

Fig: Block diagram Fig: Internal circuitary

Technology Schematic View:

21
Details of LUT3_E8:

Result:
Hence simulation, verification of Half adder, Serial Binary Adder, Carry Look
Ahead Adder and Full Adder operations are done successfully and Full
Adder’s RTL schematic, delays are observed after synthesis.
22
Program 3:

Aim: To Simulate and Verify Decoder, MUXs, Encoder using all Modeling
Styles.
Software Required: Active HDL 6.3 Version, Xilinx Web Pack.

(i) Decoder(2:4):

Fig: Circuit Diagram

Verilog HDL Code:

(a) Dataflow Model:

`timescale 1 ns / 1 ps
module decoder2 (d0,d1 ,d2 ,d3, en, a ,b);
input a, b, en ;
wire a, b, en ;
output d0,d1,d2,d3 ;
wire d0,d1,d2,d3 ;
wire abar, bbar;
assign d0 =(~a) & (~b )& (~en),
d1 = (~a) & b & (~en),
d2 = a & (~b) & (~en),
d3 = a & b & (~en);
endmodule
23
(b) Behavioral Model:

`timescale 1 ns / 1 ps module
decoder2 (d, en, a ,b);
input a, b, en ;
wire a, b, en ;
output [3:0]d ;
reg [3:0]d ;

wire abar, bbar;

always @*
begin
if(en == 1’b1)
d= 4’b1111;
else
case({b,a})
2’b00: d = 4’b0111;
2’b01: d = 4’b1011;
2’b10: d = 4’b1101;
2’b11: d = 4’b1110;
default: d = 4’b1111;
endcase
end
endmodule

(3) Structural Model:

`timescale 1 ns / 1 ps
module decoder2 (d0,d1 ,d2 ,d3, en, a ,b);
input a, b, en ;
wire a, b, en ;
output d0,d1,d2,d3 ;
wire d0,d1,d2,d3 ;
wire abar, bbar;
not(abar, a), //Using Verilog Primitive.
(bbar, b); //Labels are optional.
and(d0, en, abar, bbar), //Using Verilog Primitive.
24
(d1, en, abar, b),
(d2, en, a, bbar),
(d3, en, a, b),
endmodule

Output Waveform:

(ii) Multiplexer(4 x1):

Fig: Circuit Diagram:

25
Verilog HDL Code:

(a) Data flow Model:

`timescale 1 ns / 1 ps
module mux1 ( en ,s0 ,d0 ,s1 ,d1 ,d2 ,d3 ,z );
input en,s0,s1,d0,d1,d2,d3 ;
wire
en,s0,s1,d0,d1,d2,d3 ;
output z ;

wire z ;
assign z = (~s0&~s1&d0&en)|
(~s0&s1&d1&en)|
(s0&~s1&d2&en)|
(s0&s1&d3&en);
endmodule
(b) Behavioral Model:
`timescale 1 ns / 1 ps
module mux1 ( en ,s0 ,d0 ,s1 ,d1 ,d2 ,d3 ,z );
input en,s0,s1,d0,d1,d2,d3 ;
wire
en,s0,s1,d0,d1,d2,d3 ;
output z ;
reg z ;

always @*
begin
if(en ==1’b0) z=1’b0;
else
case({s1,s0})
2’b00: z=d0;
2’b01: z=d1;
2’b10: z=d2;
2’b11: z=d3;
default : z=1’bx;
endcase
endmodule

26
(c) Structural Model:
`timescale 1 ns / 1 ps
module mux3 ( en ,s0 ,d0 ,s1 ,d1 ,d2 ,d3
,z ); input en,d0,d1,d2,d3,s1,s0 ;
wire en, ,d0,d1,d2,d3,s1,s0 ;
output z ;

wire z ;
wire sbar0,sbar1,t1,t2,t3,t0;
not(sbar0,s0);
not(sbar1,s1);
and(t0,en,d0,sbar1,sbar0);
and(t1,en,d1,sbar1,s0);
and(t2,en,d2,s1,sbar0);
and(t3,en,d3,s1,s0);
or(z,t0,t1,t2,t3);
endmodule

Output Waveform:
27
(iii) Encoder(4:2):

Fig: Circuit Diagram

Verilog HDL Code:

(a) Dataflow Model:

`timescale 1 ns / 1 ps
module encod1 ( F0 ,F1 ,A0 ,A1, A2, A3 );
input A0 ,A1, A2, A3;
wire A0 ,A1, A2, A3;
output a, b ;
wire a, b ;
assign a= d2|d3;
assign b=d1|d3;
endmodule

(b) Behavioral Model:

`timescale 1 ns / 1 ps
module encod3 ( s ,en , A0 ,A1, A2, A3);
input en, A0 ,A1, A2, A3;
wire en, A0 ,A1, A2, A3;
output [1:0] s ;
reg [1:0] s ;

always @
* if(en)
case({A0 ,A1, A2, A3 })
4'b1000: s=2'b00;
28
4'b0100: s=2'b01;
4'b0010: s=2'b10;
4'b0001: s=2'b11;
default: s=2'bxx;
endcase
else
s=2'b00;

endmodule

(c) Structural Model:

`timescale 1 ns / 1 ps
module encod2 ( s , A0 ,A1, A2, A3);
input A0 ,A1, A2, A3;
wire A0 ,A1, A2, A3;
output [1:0]s ;
wire [1:0]s ; or(F0,
A1, A3);
or(F1, ~A0, ~A1);
endmodule
29
Output Waveforms:

Result:
Hence simulation, verification of Decoder, MUXs, Encoder using all Modeling
Styles are done successfully.
30
Program 4:

Aim: To Simulate and Verify Modeling of Flip-Flops with Synchronous and

Asynchronous reset.
.
Software Required: Active HDL 6.3 Version, Xilinx Web Pack.

(i) Synchronous Reset

(a) T Flip Flop:

Block diagram:

Truth Table:

rst t clk q qb
1 0 q qb
1 1 qb q
0 x 0 1

Verilog HDL Code:

module tff(q, qb, t, clk, rst);
input t, clk, rst;
output q, qb;
reg q, qb;
reg temp = 0;
31
always@(posedge clk)
begin
if (rst==0) begin
if(t==1) begin
temp=~
temp; end
else
temp=temp;

end
q=temp;
qb=~temp;
end
endmodule

Output Waveform:
32
(b) D Flip Flop:
Block Diagram:

Truth Table:
rst d clk q qb
1 0 0 1
1 1 1 0
0 x 0 1

Verilog HDL Code:

`timescale 1ns/1ps
module d_ff2_set( q ,clk ,reset,set,d);
input reset,set;
wire reset,set;
input clk,d ;
wire clk,d;
output q ; reg
q;
always @ (posedge clk)
if(~reset) q=1'b0;
else if(set)q=1'b1;
else q=d;
endmodule
Output Waveform:
(c) SR Flip Flop:

Block Diagram:

Truth Table:
rst s r clk q qb
1 0 0 q qb
1 0 1 0 1
1 1 0 1 0
1 1 1 x x
0 x x 0 1

Verilog HDL Code:

`timescale 1 ns / 1 ps
module sr_ff ( q , qbar, clk , s, r,
reset); input reset, clk, s, r;
wire reset, clk, s, r;
output q, qbar ;
reg q, qbar ;
always @ (posedge clk)
begin
if(reset) q=1'b0;
else
case({s, r}) //Concatenation operation.
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
34
2'b11:q=1’bx;
default: q = 1'bx;
endcase
qbar = ~q;
end
endmodule

Output Waveform:
35
(d) JK Flip Flop:

Truth Table:
rst j k clk q qb
1 0 0 q qb
1 0 1 0 1
1 1 0 1 0
1 1 1 qb q
0 x x 0 1

Verilog HDL Code:

`timescale 1 ns / 1 ps
module jk2 ( clk ,j ,k, reset ,q);
input k, j, clk, reset;
wire k, j, clk, reset;
output q ;

wire q, w ;
assign w = (j& ~q)|(~k & q);
d_ff U0(w, clk, reset, q); Block diagram:

endmodule
Output Waveform:
36
(ii)Asynchronous Reset

(a) T Flip Flop:

Block diagram:

Truth Table:

rst t clk q qb
1 0 q qb
1 1 qb q
0 x x 0 1

Verilog HDL Code:

`timescale 1 ns / 1 ps

//{{ Section below this comment is automatically maintained

// and may be
overwritten //{module
{t_ff1}}
module t_ff1 ( q ,clk ,reset,t );
input reset;
wire reset;
input clk ;
wire
clk ;
input t ;
wire t ;

37
output
q ; reg q ;
always @ (posedge clk, negedge
reset) if(~reset)
q=1'b0;
else

q=q^t;
endmodule

Output Waveform:
38
(b) D Flip Flop:
Block Diagram:

Truth Table:
rst d clk q qb
1 0 0 1
1 1 1 0
0 x x 0 1

Verilog HDL Code:

`timescale 1ns/1ps
module d_ff_asyn(d, clk, reset,
q); input clk, reset,d;
wire clk, reset,d;
output q;
reg q;
always @ (posedge clk, negedge rst )
if(~reset)
q=1'b0;
else q=d;
endmodule
Output Waveform:
39
(c) SR Flip Flop:
Block Diagram:

Truth Table:
rst s r clk q qb
1 0 0 q qb
1 0 1 0 1
1 1 0 1 0
1 1 1 x x
0 x x x 0 1

Verilog HDL Code:

`timescale 1 ns / 1 ps
module sr_ff ( q ,clk , s, r ,qbar ,reset);
input reset, clk, s, r;
wire reset, clk, s, r;
output q, qbar ;
reg q, qbar ;
always @ (posedge clk, negedge
rst ) begin
if(reset) q=1'b0;
else
case({s, r}) //Concatenation operation.
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=qbar;
40
default: q = 1'bx;
endcase
qbar =
~q; end
endmodule

Output Waveform:
41
(d) JK Flip Flop:

Block diagram:

Truth Table:
rst j k clk q qb
1 0 0 q qb
1 0 1 0 1
1 1 0 1 0
1 1 1 qb q
0 x x x 0 1

Verilog HDL Code:

`timescale 1 ns / 1 ps
module jk2 ( clk ,j ,k, reset
,q); input k, j, clk, reset;
wire k, j, clk, reset;
output q ;
wire q ;
wire w;
assign w = (j& ~q)|(~k & q);
d_ff_asyn U0(w, clk, reset, q);
endmodule
42
Output Waveform:

Result:
Hence simulation, verification of Half adder, Serial Binary Adder, Carry Look
Ahead Adder and Full Adder operations are done successfully and Full
Adder’s RTL schematic, delays are observed after synthesis.
43
Program 5:

Aim: To Design and Simulate of Counters- Ring Counter, Johnson Counter,

and Up-Down Counter, Ripple Counter.
Software Required: Active HDL 6.3 Version, Xilinx Web Pack.

(i) Ring Counter:

Block Diagram:

Set one state and Clear three states.

Truth Table:
QA QB QC QD
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
Repeat Sequence
44
Desired Waveforms:

Verilog HDL Code:

`timescale 1 ns / 1 ps
module ring_counter( Q,SET,CLOCK,RST);
input SET, CLOCK,RST;
wire SET, CLOCK,RST;
output [3:0] Q ;
wire [3:0] Q;//,F ;
//assign Q=F;
d_ff2_set U0(Q[0], CLOCK, RST, 0,Q[3]);
d_ff2_set U1(Q[1], CLOCK, RST, 0, Q[0]);
d_ff2_set U2(Q[2], CLOCK, RST, 0, Q[1]);
d_ff2_set U3(Q[3], CLOCK, RST, SET, Q[2]);
endmodule
Output Waveform:
45
(ii) Johnson Counter:
Block Diagram:

Truth Table:
QA QB QC QD
0 0 0 0
1 0 0 0
1 1 0 0
1 1 1 0
1 1 1 1
0 1 1 1
0 0 1 1
0 0 0 1
Repeat Sequence

Desired Waveform:
46
Note: 1.The switch-tail ring counter, also known as the Johnson counter,
overcomes some of the limitations of the ring counter.
2. Feedback connection is from QD bar to DA.
3. Recirculating a single 1 around a ring counter divides the input clock
by a factor equal to the number of stages. Whereas, a Johnson counter
divides by a factor equal to twice the number of stages. For
example, a 4-stage ring counter divides by 4. A 4-stage Johnson
counter divides by 8.
Verilog HDL Code:

`timescale 1 ns / 1 ps
module john_counter ( a ,rst ,clk );
input rst ;
wire rst ; input
clk ; wire clk ;
output [3:0] a ;
wire [3:0] a ;

d_ff2 dff1(a[0],clk,rst,~a[3]);
d_ff2 dff2(a[1],clk,rst,a[0]);
d_ff2 dff3(a[2],clk,rst,a[1]);
d_ff2 dff4(a[3],clk,rst,a[2]);
endmodule
Output Waveform:
47
Synthesis Report:

(i) Final Report Results:

RTL Top Level Output File Name : john_counter.ngr
Top Level Output File Name : john_counter
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :6
Cell Usage :
# BELS :2
# INV :2
# FlipFlops/Latches :4
# FDR :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers :5
# IBUF :1
# OBUF :4
(ii) Device utilization summary:
Selected Device : 3s50pq208-5
Number of Slices : 2 out of 768 0%
Number of Slice Flip Flops : 4 out of 1536 0%
Number of 4 input LUTs : 2 out of 1536 0%
Number of IOs :6
Number of bonded IOBs : 6 out of 124 4%
Number of GCLKs : 1 out of 8 12%

(iii) Timing Summary:

Speed Grade : -5
Minimum period: 2.707ns (Maximum Frequency : 369.372MHz)
Minimum input arrival time before clock : 3.546ns
48
Maximum output required time after clock : 6.280ns
Maximum combinational path delay : No path found

RTL Schematic:

Fig: Block diagram Fig: Internal Circuitary

Technology Dependent Schematic:

Fig: Block diagram Fig: Internal Circuitary

Power Analyzer:
49
(iii) Up-Down Counter:
Block Diagram:

Verilog HDL Code:

`timescale 1 ns / 1 ps
module ud_counter ( a ,rst ,ud ,clk );
input rst, ud, clk ;
wire rst, ud,
clk ; output [2:0]
a ; wire [2:0] a ;
T_ff1 tff0(1,clk,rst,a[0]);
T_ff1 tff1(ud^~a[0],clk, rst, a[1]);
T_ff1 tff2(((~ud) & ~a[1] & ~a[0])|(ud & a[1] &
a[0]),clk,rst,a[2]); endmodule
Output Waveform:
50
(iv) Ripple Counter:

Verilog HDL Code:

`timescale 1 ns / 1 ps
module ripple_cou ( a,rst,clk,t );
input rst,clk,t ;
wire rst,clk,t ;
output [3:0]a ;
wire [3:0]a ;

T_ff1 tff0(a[0],clk,rst,t);
T_ff1 tff1(a[1],a[0],rst,t);
T_ff1 tff2(a[2],a[1],rst,t);
T_ff1
tff3(a[3],a[2],rst,t); endmodule

Output Waveforms:

Result:
Hence simulation, verification of counters- Ring, Johnson, Up-down, Ripple
operations are done successfully and Johnson Counter’s RTL schematic,
Technology schematic ,Power analyzer & delays are observed after synthesis.
51
Program 6:

Aim: To design and Simulate N- bit Register of Serial-in Serial-out, Serial in

Parallel out, Parallel in Serial out and Parallel in Parallel Out.

Software Required: Active HDL 6.3 Version, Xilinx Web Pack.

(i) Serial-IN Serial-OUT:

Block diagram:

Desired Waveforms:

Verilog HDL Code:

`timescale 1 ns / 1 ps
module siso ( data_out, rst ,clock ,data_in );
input rst, clock, data_in ;
wire rst, clock, data_in ;
52
output data_out;
wire data_out;
wire d1,d2,d3;
d_ff2 dff1(d1, clock, rst, data_in);
d_ff2 dff2(d2,clock,rst,d1);
d_ff2 dff3(d3,clock,rst,d2);
d_ff2 dff4(dout,clock,rst,d3);

endmodule

Output Waveform:
53
(ii) Serial-IN Parallel-OUT:

Block diagram:

Desired Waveforms:

Verilog HDL Code:

`timescale 1 ns / 1 ps module
sipo ( q ,rst ,clk ,din );
input rst, clk, din ;
wire rst, clk, din ;
output [3:0] q ;
wire [3:0] q ;
d_ff2 dff1(q[0],clk, rst, din);
d_ff2 dff2(q[1],clk, rst, q[0]);
54
d_ff2 dff3(q[2],clk, rst, q[1]);
d_ff2 dff4(q[3],clk, rst, q[2]);
endmodule

Output Waveform:
55
(iii) Parallel-IN Serial-OUT:

Block diagram:

Desired Waveforms:
56
Verilog HDL Code:
`timescale 1 ns / 1 ps
module piso ( rst ,ls,clk ,dout ,d );
input rst, clk,ls;
wire rst, clk, ls;
input [3:0] d ;
wire [3:0] d ;
output dout ;
wire dout ;
wire q1,q2,q3;

d_ff2 dff1(q1,clk,rst,((ls & d[0])|(~ls & d[0])));

d_ff2 dff2(q2,clk,rst,((ls & d[1])|(~ls & q1)));
d_ff2 dff3(q3,clk,rst,((ls & d[2])|(~ls & q2)));
d_ff2 dff4(dout, clk, rst,((ls & d[3])|(~ls & q3)));
endmodule

Output Waveform:
57
(iv) Parallel-IN Parallel-OUT:

Block diagram:

Note:
1. LD/SH' controls the AND-OR multiplexer at the data input to the FF's.
2. If LD/SH'=1, the upper four AND gates are enabled allowing application of
parallel inputs DA DB DC DD to the four FF data inputs.
3. Inverter bubble at the clock input of the four FFs.
4. OC' must be low if the data needs to be available at the actual output pins as
opposed to only on the internal FFs.
5. previously loaded data may be shifted right by one bit position if LD/SH'=0
for the succeeding negative going clock edges.

Truth Table:
58
Verilog HDL Code:
`timescale 1 ns / 1 ps
module pipo ( q ,rst ,clk ,d );
input rst, clk ;
wire rst,clk ;
input [3:0] d ;
wire [3:0] d ;
output [3:0] q ;
wire [3:0] q ;

d_ff2 dff1(q[0],clk,rst,d[0]);
d_ff2 dff2(q[1],clk,rst,d[1]);
d_ff2 dff3(q[2],clk,rst,d[2]);
d_ff2 dff4(q[3],clk,rst,d[3]);
endmodule

Output Waveform:
59
Synthesis Report:

(i)Final Report Results:

RTL Top Level Output File Name : pipo.ngr
Top Level Output File Name : pipo
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 10
Cell Usage :
# BELS :1
# INV :1
# Flip Flops/Latches :4
# FDR :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers :9
# IBUF :5
# OBUF :4

(ii) Device utilization summary:

Selected Device : 3s50pq208-5
Number of Slices : 1 out of 768 0%
Number of Slice Flip Flops : 4 out of 1536 0%
Number of 4 input LUTs : 1 out of 1536 0%
Number of IOs : 10
Number of bonded IOBs : 10 out of 124 8%
IOB Flip Flops :4
Number of GCLKs : 1 out of 8 12%
60
(iii)Timing Summary:
Speed Grade : -5
Minimum period : No path found
Minimum input arrival time before clock : 3.546ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay: No path found
RTL Schematic:

Fig: Block Diagram Fig: Internal Circuitry

Technology Schematic:

Fig: Internal Circuitry

Result:
Hence simulation, verification of N- bit Register of Serial-in Serial-out, Serial
in Parallel out, Parallel in Serial out and Parallel in Parallel Out operations
are done successfully and Full Adder’s RTL schematic, delays are observed
after synthesis.
61
Program 7:

Aim: To design and Simulate Sequence Detector (Finite State Machine-Mealy

Or Moore Machines).

Software Required: Active HDL 6.3 Version, Xilinx Web Pack.

(i) Moore State Machine:

Fig: Moore State Machine Block Diagram

Fig: Moore FSM for Sequence Detector

62
Verilog HDL Code:
//Sequence detector “111” using Moore FSM.
1/ D:\JNTUCEA\VERILOG LAB MANUAL\ SEQ_DETECT.v
2/ Verilog created by Xilinx's StateCAD 10.1
3/ Thu Dec 24 11:33:24 2009
4/ This Verilog code (for use with Xilinx XST) was generated using:
5/ one-hot state assignment with boolean code format.
6/ Minimization is enabled, implied else is enabled,
7/ and outputs are manually optimized.

`timescale 1s/1s
module seq_detect(CLK,data_in,RESET,seq_detect);
input data_in,RESET, CLK;
output seq_detect;
reg seq_detect,next_seq_detect;
reg STATE0, next_STATE0, STATE1, next_STATE1,
STATE2, next_STATE2, STATE3, next_STATE3;
always @(posedge CLK)
begin
STATE0 = next_STATE0;
STATE1 = next_STATE1;
STATE2 = next_STATE2;
STATE3 = next_STATE3;
seq_detect = next_seq_detect;
end
always @ (data_in or RESET or STATE0 or STATE1 or STATE2 or
STATE3)
begin
if ( ~data_in & STATE0 | RESET )
next_STATE0=1; else next_STATE0=0;
if ( ~RESET & data_in & STATE0 | ~data_in & ~RESET &
STATE1 | ~data_in & ~RESET & STATE2 | ~RESET &
STATE3 ) next_STATE1=1;
else next_STATE1=0;
if ( ~RESET & data_in & STATE1 )
next_STATE2=1; else next_STATE2=0;
if ( ~RESET & data_in & STATE2 )
next_STATE3=1; else next_STATE3=0;
if ( ~RESET & data_in & STATE2 )
next_seq_detect=1; else next_seq_detect=0;
end
endmodule
63
(ii) Mealy State Machine:

Fig: Mealy Satae Machine Block Diagram

Fig: Mealy FSM for Sequence Detector

//Sequence detector “111” using Mealy FSM.

1/ D:\JNTUCEA\VERILOG LAB MANUAL\ SEQ_DETECT_MEALY_1.v
2/ Verilog created by Xilinx's State CAD 10.1
3/ Thu Dec 24 12:38:33 2009
4/ This Verilog code (for use with Xilinx XST) was generated using:
5/ binary encoded state assignment with structured code format.
6/ Minimization is enabled, implied else is enabled,
7/ and outputs are manually optimized.
64
`timescale 1s/1s
module
seq_detect_mealy_1(CLK,data_in,reset,seq_de
tect); input CLK;
input data_in,reset;
output seq_detect;
reg seq_detect,next_seq_detect;
reg [1:0] sreg;

reg [1:0] next_sreg;

`define STATE0 2'b00
`define STATE1 2'b01
`define STATE2 2'b10

always @(posedge CLK)

begin
sreg = next_sreg;
seq_detect = next_seq_detect;
end
always @ (sreg or data_in or reset)
begin
next_seq_detect = 0;
next_sreg=`STATE0;
if ( reset ) begin
next_sreg=`STATE0;
next_seq_detect=0;
end
else begin
case (sreg)
`STATE0 : begin
if ( data_in ) begin
next_sreg=`STATE1;
next_seq_detect=0;
end
65
else begin
next_sreg=`STATE0;
next_seq_detect=0;
end
end
`STATE1 : begin
if ( data_in ) begin
next_sreg=`STATE2;
next_seq_detect=0;
end

else begin
next_sreg=`STATE0;
next_seq_detect=0;
end
end
`STATE2 : begin
if ( data_in ) begin
next_sreg=`STATE0;
next_seq_detect=1;
end
else begin
next_sreg=`STATE0;
next_seq_detect=0;
end
end
endcase
end
end
endmodule
66
module seq_det (DATA, CLK, DETECT);
input DATA, CLK;
output DETECT;
integer COUNT;
reg DETECT;
initial
begin

COUNT = 0;
DETECT = 0;
end
always @(posedge CLK)
begin
if(DATA == 1)
COUNT = COUNT +1;
else
COUNT =
0; if(COUNT >= 3)
DETECT = 1;
else
DETECT = 0;
end
endmodule

Test Bench:
module TOP;
reg DATA,CLK;
integer OUT_FILE;
COUNTER3_LS
F1(DATA,CLK,DETECT); initial
begin
CLK = 0;
forever
#5 CLK = ~ CLK;
67
end

initial
begin
DATA = 0; #5
DATA = 1;
#40 DATA = 0;

#10 DATA = 1;
#20 DATA = 0;
#20 $stop; //STOP
simulation end
initial
begin
//Save monitor information in file.
OUT_FILE = $fopen(“results.vectors”);
$fmonitor(OUT_FILE, “CLK = %b, DATA = %b, DETECT = %b”,
CLK, DATA,
DETECT); end
endmodule

Output Waveforms:
68
Synthesis Report:
(i) Final Results Report:
RTL Top Level Output File Name : seq_det.ngr
Top Level Output File Name : seq_det
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# Ios :3
Cell Usage :
# BELS : 152
# GND :1
# INV :2
# LUT1 : 30
# LUT2 : 37
# LUT3 :2
# LUT4 :7
# MUXCY : 41
# VCC :1
# XORCY : 31
# FlipFlops/Latches : 33
# FD : 32
# FDR :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers :2
# IBUF :1
# OBUF :1

(ii) Device utilization summary:

Selected Device : 3s50pq208-5
Number of Slices : 43 out of 768 5%
Number of Slice Flip Flops : 33 out of 1536 2%
69
Number of 4 input LUTs : 78 out of 1536 5%
Number of Ios :3
Number of bonded IOBs : 3 out of 124 2%
Number of GCLKs : 1 out of 8 12%

(iii) Timing Summary:

Speed Grade : -5
Minimum period: 10.824ns (Maximum Frequency: 92.389MHz)
Minimum input arrival time before clock : 8.438ns
Maximum output required time after clock : 6.216ns
Maximum combinational path delay : No path found

(iv)Timing Detail:
All values displayed in nanoseconds (ns)
Timing constraint: Default period analysis for Clock 'CLK'
Clock period: 10.824ns (frequency: 92.389MHz)
Total number of paths / destination ports : 1088 / 33

RTL Schematic:

Fig: Block diagram

Fig: Internal circuitry

70
Technology Schematic:

Fig: Block Diagram

Fig: Internal circuitry

Power Analysis:

Result:
Hence simulation, verification of Sequence Detector operations are done
successfully.
71
Program 8:

Aim: To design and Simulate 4-Bit Multiplier, Divider(for 4-Bit Operand).

Software Required: Active HDL 6.3 Version, Xilinx Web Pack.

(i) 4-Bit Multiplier:

Block diagram:
72
Fig: Generated Algorithm for N Bit

Verilog HDL Code:

Model 1:
module mul4_4(x, y, z);
input [3:0] x, y;
wire [3:0] x, y;
output [7:0] z;
wire [7:0] z;
assign z = x *
y; endmodule
73
Model 2:
module multiplier (result, op_a, op_b);
input [3:0] op_a, op_b;
output [7:0] results;
reg [7:0] results; reg
[7:0] shift_opa; reg
[3:0] shift_opb;

always @ (op_a or op_b)

begin
result = 0;
shift_opa = op_a; // zero extend
left shift_opb = op_b;
repeat (4)
begin
if (shift_opb[0] )
result = result + shift_opa;
shift_opa = shift_opa << 1; // shift left
shift_opb = shift_opb >> 1; // shift right
end
endmodule
Test Bench:
module multiplication_tb
(); reg [3:0] x, y;
wire [7:0] z;
integer i,j;
initial
begin
for (i=0; i<8; i=i+1)
begin
x = i;
for (j=0; j<8; j=j+1)
begin
y = j;
74
#10;
end
end
end
multiplication multiplication_inst(.inputA(x),.inputB(y),.outputA(z));
initial
begin

$monitor ("inputA %h inputB %h outputA %h",x, y, z);

end
endmodule

Output Waveform:
75
(ii) Divider:

Dividend:

Verilog HDL Code:

module div4_4(x, y, z);
input [7:0] x;
input [3:0] y;
wire [7:0] x;
wire [3:0] y;
76
output [3:0] z;
wire [3:0] z;
assign z = x /
y; endmodule

Output Waveform:

Result:
Hence simulation, verification 4-Bit Multiplier, Divider operations are done
successfully.
77
Program 9:

Aim: To design and Simulate ALU to Perform – ADD, SUB, AND-OR, 1’s and
2’s COMPLIMENT, Multiplication, Division.

Software Required: Active HDL 6.3 Version, Xilinx Web Pack.

Verilog HDL Code:

`timescale 1ns/1ps
module ALU (input [3:0] OP_CODE, A, B, input
CLK,C_IN,EN, output reg [3:0] Y);
wire [5:0] OP_CODE_CI;
assign OP_CODE_CI = {OP_CODE,
C_IN}; always @(posedge CLK)
if(EN == 1’b1)
case(OP_CODE_CI)
5’b00000: Y=A;
5’b00001: Y=A+1;
5’b00010: Y=A+B;
5’b00011: Y=A+B+1;
5’b00100: Y=A+~B;
5’b00101: Y=A+~B+1;
5’b00110: Y=A-1;
5’b00111: Y=A;
5’b01000: Y=A & B;
5’b01001: Y=A | B;
5’b01010: Y=A ^ B;
5’b01011: Y=~A;
5’b01100: Y=4’b0;
default: Y=4’bx;
endcase
endmodule
78
Test Bench for Verilog HDL Code:
module ALU_tb;
// Inputs
wire [3:0] OP_CODE;
reg [3:0]A,B;
reg CLK,EN;
wire C_IN;

1/ Outputs
wire [3:0] Y;
reg [4:0] OP_CODE_CI_SIG;
2/ Instantiate the Unit Under Test (UUT)
ALU uut (
.OP_CODE(OP_CODE),
.A(A),
.B(B),
.CLK(CLK),
.C_IN(C_IN),
.EN(EN),
.Y(Y)
);
initial begin
3/ Initialize Inputs
A = 4'b0001;
B = 4'b1000;
CLK = 1'b0;
EN = 1'b1;
// Wait 100 ns for global reset to finish
#100;
end
assign OP_CODE =
OP_CODE_CI_SIG[4:1]; assign C_IN =
OP_CODE_CI_SIG[0]; always #10 CLK = ~
CLK;
79
always begin
#100 OP_CODE_CI_SIG = 5'b00000;
#100 OP_CODE_CI_SIG = 5'b00001;
#100 OP_CODE_CI_SIG = 5'b00010;
#100 OP_CODE_CI_SIG = 5'b00011;
#100 OP_CODE_CI_SIG = 5'b00100;
#100 OP_CODE_CI_SIG = 5'b00101;

#100 OP_CODE_CI_SIG = 5'b00110;

#100 OP_CODE_CI_SIG = 5'b00111;
#100 OP_CODE_CI_SIG = 5'b01000;
#100 OP_CODE_CI_SIG = 5'b01010;
#100 OP_CODE_CI_SIG = 5'b01100;
#100 OP_CODE_CI_SIG = 5'b01110;
#100 OP_CODE_CI_SIG = 5'b10000;
end
endmodule

Output Waveform:
80
Synthesis Report:
(i) Device utilization summary:
Selected Device : 3s50pq208-5
Number of Slices : 16 out of 768 2%
Number of 4 input LUTs : 29 out of 1536 1%
Number of IOs : 19
Number of bonded IOBs : 19 out of 124 15%
IOB Flip Flops :4
Number of GCLKs : 1 out of 8 12%

(ii)Advanced HDL Synthesis Report:

Macro Statistics
# Adders/Subtractors :2
4-bit adder carry in :1
4-bit subtractor :1
# Registers :4
Flip-Flops :4
# Multiplexers :1
4-bit 13-to-1 multiplexer :1
# Xors :1
4-bit xor2 :1

(iii)Timing Summary:
Speed Grade : -5
Minimum period : No path found
Minimum input arrival time before clock : 9.476ns
Maximum output required time after clock: 6.216ns
Maximum combinational path delay : No path found
81
RTL View :

Fig: Block diagram

Fig: Internal Circuitry

Result:
Hence simulation, verification of ALU to Perform – ADD, SUB, AND-OR, 1’s
and 2’s COMPLIMENT, Multiplication, Division operations are done
successfully and ALU’s RTL schematic, delays are observed after synthesis.
82