DEPARTMENT OF ELECTRICAL AND ELECTROINC

ENGINEERING
BANGLADESH UNIVERSITY OF ENGINEERING &
TECHNOLOGY
EEE 304 : Digital Electronics Laboratory

EXPERIMENT NO.1:INTRODUCTION TO BASIC GATES AND

LOGIC SIMPLIFICATION TECHNIQUES

Prelab work:
Submit your Prelab before starting the experiment

1. Form the truth table for three basic gates known as AND , OR and NOT
Gate (Inverter). Assume the number of inputs to be 3.

Required Instruments andICs

1) 2 input AND gate (74LS08)
2) 2 input OR gate (74LS32)
3) Not gate (74LS04)

Part A: introduction to most familiar gates:

While the three basic functions AND, OR, and NOT are sufficient to accomplish all
possible logical functions and operations, some combinations are used so commonly
that they have been given names and logic symbols of their own.

The NAND Gate

The NAND gate implements the NAND function, which is exactly inverted from the
AND function you already examined. With the gate shown in figure, both inputs
must have logic 1 signals applied to them in order for the output to be a logic 0. With
either input at logic 0, the output will be held to logic 1.
X Y Z=(X.Y)/
0 0 1
0 1 1
1 0 1
1 1 0

The circle at the output of the NAND gate denotes the logical inversion.Also in the
figure , note that the overbar is a solid bar over both input values at once. This shows
that it is the AND function itself that is inverted, rather than each separate input.

The NOR Gate

The NOR gate is an OR gate with the output inverted. Where the OR gate allows the
output to be true (logic 1) if any one or more of its inputs are true, the NOR gate inverts
this and forces the output to logic 0 when any input is true.
X Y (X+Y)/
0 0 1
0 1 0
1 1 0 0
1 1 0
In symbols, the NOR function is designated with a plus sign (+), with an overbar over
the entire expression to indicate the inversion. In logical diagrams, this is indicated by
an OR gate with a circle to designate the inversion.

The Exclusive-OR, or XOR Gate

The Exclusive-OR, or XOR function is an interesting and useful variation on the basic
OR function. Verbally, it can be stated as, "Either A or B, but not both." The XOR gate
produces a logic 1 output only if its two inputs are different. If the inputs are the same,
the output is a logic 0.
A B AB
0 0 0
1
3 0 1 1
2 1 0 1
1 1 0

The XOR symbol is a variation on the standard OR symbol. It consists of a plus (+)
sign with a circle around it. The logic symbol, as shown here, is a variation on the
standard OR symbol.

EXPERIMENT 1: Implement the following logic function with basic gates

F(A,B,C) = AC+BC
Write down the truth table and compare it with your experimental results.

Part B : Boolean Minimization_- an algebraic approach_

One of the primary requirements when dealing with digital circuits is to find ways to
make them as simple as possible. This constantly requires that complex logical
expressions be reduced to simpler expressions that nevertheless produce the same
results under all possible conditions. The simpler expression can then be implemented
with a smaller, simpler circuit, which in turn saves the price of the unnecessary gates,
reduces the number of gates needed, and reduces the power and the amount of space
required by those gates.
One tool to reduce logical expressions is the mathematics of logical expressions,
introduced by George Boole in 1854 and known today as Boolean Algebra. The rules
of Boolean Algebra are simple and straight-forward, and can be applied to any logical
expression. The rules of Boolean Algebra are:

2
AND Operations (·) OR Operations (+) NOT Operations (')
0·0 = 0 A·0 = 0 0+0 = 0 A+0 = A 0' = 1
1·0 = 0 A·1 = A 1+0 = 1 A+1 = 1 1' = 0
0·1 = 0 A·A = A 0+1 = 1 A+A = A A'' = A
1·1 = 1 A·A' = 0 1+1 = 1 A+A' = 1

Associative Law Distributive Law

(A·B)·C = A·(B·C) = A·B·C A·(B+C) = (A·B) + (A·C)
(A+B)+C = A+(B+C) = A+B+C A+(B·C) = (A+B) · (A+C)
Commutative Law Precedence
A·B = B·A AB = A·B
A+B = B+A A·B+C = (A·B) + C
A+B·C = A + (B·C)

DeMorgan's Theorem
(A·B)' = A' + B' (NAND)
(A+B)' = A' · B' (NOR)

Example:A given Boolean expression ( AB + AC + ABC ) can be solved by following

methods:
STEP1:Apply DeMorgan’s theorem to the first term
( AB ) ( AC ) + A B C

STEP2:Apply DeMorgan’s theorem to each term in parentheses

( A + B )( A + C ) + A B C
STEP3:Apply the distributive law to the two terms in parenthesis
A A+ AC + A B + B C + A B C
STEP4:Apply the AND operation( A A = A ) to the first term and OR operation
( A B (1 + C ) = A B )to the third and last term.

A+ AC+ A B+B C
STEP5: Apply OR operation ( A (1 + C ) = A ) to the first and second terms
A+ AB+BC
STEP5: Apply OR operation to the first and second terms
A+BC
Problem:
For the following logic function, find out the truth table, write down the logic
expression and simplify the logic expression as far as possible using Boolean
algebra.
F(A,B,C,D)=∑(5,7,10,11,13,14,15)

3
Draw the circuit diagrams both before and after simplification. Can you see the
effect of simplification?

Are you sure that further simplification is not possible ????

Is your simplified logic expression matches exactly with that of all your classmates?????

Part C: Karnaugh Maps(or in short k map): A Geometric Approach

K-Map: a truth table arranged so that terms which differ by exactly one variable are
adjacent to one another so we can see potential reductions easily.

RULES:
1)A group or sub-cube must
contain either 1,2,4,8 or 16
cells(i.e 2N cells ).
2) Each cell in a group must be
adjacent to one or more cells in
that same group, but all cells in
the group do not have to be
adjacent to each other.
3) Always include the largest
possible number of 1s in a group
in accordance with rule 1.
4) Each 1 on the map must be
included in at least one group.
The 1s already in a group can be
included in another group as long
as the overlapping groups include
noncommon 1s.

4
RULES:
1.Group the cells that have 1s.Each group of
cells containing 1s creates one product term
composed of all variables that occur in only
form(either uncomplemented or complemented
within the group are eliminated)

2.Determine minimum product terms for each

group

3.When all the minimum product terms

are derived from the Karnaugh map,
they are summed to form the minimum
SOP expression

EXPERIMENT 2:

(a) Simplify the problem as shown in Part B using K map and draw and construct
the circuit diagram. Which method provides better simplification? Implement
your simplified circuit in the breadboard and verify the functionality of the
circuit.

(b) Simplify the following problem using K map. Draw and construct the circuit
diagram
F(A,B,C,D)=Σ(5,6,7,9,13)
Is there only one solution or more?

Report:

1) For each of the experiment above, formulate the problem, show the
implemented circuit diagram and the measured truth table of your circuit.

5
2) Answer all the questions in the sheet including the additional questions asked
below.
3) Discussion

Additional questions:

1. It is possible to implement all the basic logic gates using only NAND gate. That is why
it is called universal gate. With necessary circuit diagram ,show how AND, OR,NOT
and XOR gates can be implemented using NAND gates only.

2. Simplify(circuit diagram not required) the following problem using K map .(note that
it is a 5 variable problem)
F(A,B,C,D,E)=Σ(1,4,5,13,20,21,22,28) +d(6,9,11,12,14,29,30)
Here, D means 'DONT CARE'
IC PIN Diagram

IC7408/7432 2 INPUT AND/OR GATE IC 7404 INVERTER

INPUT OUTPUT
INPUT OUTPUT
1-2 3 1 2
4-5 6 3 4
9-10 8 5 6
12-13 11 7 GND
7 GND
14 VCC

Reviewed By: Md. Imran Momtaz

6
DEPARTMENT OF ELECTRICAL AND ELECTROINC
ENGINEERING
BANGLADESH UNIVERSITY OF ENGINEERING &
TECHNOLOGY
EEE 304 : Digital Electronics Laboratory

EXPERIMENT NO. 2: INTRODUCTION TO DIGITAL CIRCUIT

DESIGN CONCEPT.

PRELAB

Submit your Prelab before starting the experiment.

1. Show the truth table of a two input AND, NAND, OR and NOR gate.
2. Show the truth table of the following function

F(A,B,C) = AC+BC
3. The function expressed above is in SOP form. Express the same function
in POS form.
4. What is a Complex Programmable Logic Device (CPLD) ? Show the
address and the corresponding data of the 16x1 SRAM look-up table which
will implement the following four variable function

F(A,B,C,D) = AB+CD
5. What are the differences between functional and timing simulation?

1. INTRODUCTION:

The design of a digital system begins with a set of specification. Here the essential
features of the product are identified. From a complete set of specification, a general
structure of the design is defined which is more commonly known as architecture
design. As the general structure is established, CAD tools are used to work out the
details. CAD tools enables the designer to simulate the behavior of incredibly complex
products, and such simulations are used to determine whether the obtained design
meets the required specifications. If errors are found, then appropriate changes are
made and the verification of the new design is repeated through simulation. When the
simulation indicates that the design is correct, a complete physical prototype of the
product is constructed. The prototype is thoroughly tested for conformation with the
specification. When the prototype passes all the tests, then the product goes to
production.

© A.B.M. Harun-ur Rashid 1 13/11/2006

Experiment 1

Design a two way multiplexer circuit such that the output will be connected to the data
source X1 when the control signal S is High, and the output will be connected to the
data signal X2 when the control signal S is low.

Simulate the design to verify its functionality and implement it in a FLEX10K

Complex Programmable Logic Device (CPLD) chip.

Experimental Procedure

In this experiment we will use ALTERA corporations Quartus II software for the
design, simulation and implementation of our design. We will go through the following
steps-

1. Design entry using schematic

2. Compilation and error location
3. Functional simulation
4. Floorplan
5. Design Compilation for the generation and conversion of configuration data
6. Download the design (configuration data) to LP2900 development board which
contain FLEX10K CPLD based design platform.
7. Test and verify the functionality of the circuit.

2. Design Entry Using Graphic Editor

The standard procedure for the schematic based design entry in Quartus II is as follows.

.
Create a New Project
1. In the menu bar select “File” and click “New Project Wizard”
2. Click Next and “Set working directory” and “Project Name”
3. In “Set the family and device you want to target for compilation” select the
device “FLEX10K”, select package “TQFP”, Pin “144”, speed category “3”
and select the device “EPF10K10TC144-3”.
4. Select “Next” click “Finish”.

Creating the Schematic file

1. Select “File > New > Block diagram/schematic file”. A new file with .bdf
extension will be opened. Save the file with same name as the project name.

Design Entry in the schematic file

When you are in blank spaces in Graphic Editor window, click the left mouse button
twice. The “../quartus60/libraries” will be open. Go to the “primitives/logic”
directory and enter the necessary gates and I/O pins. You may also enter the logic gates
from the left side icons of your schematic editor window.

© A.B.M. Harun-ur Rashid 2 13/11/2006

Fig. 1 The Schematic window

3. Synthesis

After design entry we have to perform analysis and synthesis. Analysis and synthesis
builds a single project database that integrates all the design files in a design entity or
project hierarchy. As it create the database, the Analysis stage of Analysis & Synthesis
examine the logical completeness and consistency of the project, and check for
boundary connectivity and syntax error. It also synthesize and performs technology
mapping on the logic in the design entity or project’s file.

To do analysis and synthesis go to Processing from the toolbar and click start. Go to
the submenu and perform Start Analysis and Synthesis.

4. Fitter

Fitter assignments allow you to achieve an optimal fit for the design and achieve timing
closure. In order to achieve timing closure, you may need to adjust the default settings
of the Fitter. A common use of fitting assignments is to control the use of different
resources on the device. For example, you may want to control the location for RAM
blocks in order for the design to fit in the device.
To perform fitting go through the following steps

“Processing> Start > Start Fitter”

© A.B.M. Harun-ur Rashid 3 13/11/2006

5. Assembler

The Assembler is the Compiler module that completes project processing by generating
a device programming image. For the FPGAs, this programming image is in the form
of one or more Programmer Object Files (.pof), SRAM Object Files (.sof), Hexadecimal (Intel-
Format) Output Files (.hexout), Tabular Text Files (.ttf), and Raw Binary Files (.rbf), from a
successful fit (that is, place and route).

To perform the assembly task go through the following steps

“Processing> Start > Start Assembler”

5. Timing Analysis

The Quartus II timing analyzers provide a method of analyzing, debugging, and

validating the performance of a design. Timing analysis measures the delay along the
various timing paths and verifies the performance and operation of the design. You can
specify constraints and assignments that help the design meet timing requirements. If
you specify constraints or assignments, the Fitter optimizes the placement of logic in
the device in order to meet those constraints.

To perform the assembly task go through the following steps

“Processing> Start > Start Timing Analyzer”

6. Simulation

i) Simulation
You can perform Functional and timing simulation of your design by using the Quartus
II simulator.

To perform the simulation task go through the following steps

“Processing> Start Simulation”

ii) Viewing result

The Waveform Editor is a tool for entering simulation vectors and viewing simulation
results in a graphical waveform format. You can use the Waveform Editor to create
Vector Waveform Files (.vwf) or Compressed Vector Waveform File (.cvwf) that contain input
vectors for simulation.

To view the simulation data in the waveform file, open a waveform file. Go through the
following steps –

File àNew àOther FileàVector Waveform File

Save the waveform file in the same name as the top level design name. To insert the
input and output signals on the waveform editor go through the following steps-

© A.B.M. Harun-ur Rashid 4 13/11/2006

1. Right click on the left column of waveform editor window.
2. Choose Insert Node or BUS
3. Click Node Finder
4. Choose Pins-all and click Select >>. All the input output signals will be loaded
on the Waveform file.

Now perform “Processing> Start Simulation” and the updated waveform will be
displayed in the simulation waveform.

Fig. Viewing the simulation result in the waveform editor

7. Floorplan and Design Compilation

Floorplan is the arrangement of circuit into CPLD chip, which includes chip
assignment, the assignment of input and output pins, and the assignment of Logic Array
Block (LAB) of the circuits etc. All Floorplans are managed by Floorplan Editor which
can be done by “Assignment > Timing Closure Floorplan”. Identify your signal pins
from “View Package Top”.

If you are not really satisfied with your pin arrangement or even would like to make
any change, you could re-plan the pin assignment by “Assignments>Assign Pins”
Make sure that the input Signal of your circuit i.e. signal X1, X2 and S are connected
to any three of the four pulse switches PS1( pin 54), PS2( pin 56), PS3( pin 124) and
PS4( pin 126). Also note down to which pin your output is connected.

© A.B.M. Harun-ur Rashid 5 13/11/2006

5. Device Programming and Circuit Testing

For ALTERA device programming, it requires users check what type of the
reconfigurable element is used in the selected device. The type of the reconfigurable
element could be EPROM, EEPROM, FLASH or SRAM. Different types will use
different programming approaches. Since we already used EPF10K10TC144-3 device
we will use it as our programming example. EPF10K10TC144-3 CPLD is an ALTERA
SRAM device. All the configuration data has to be installed into the circuit completely
after the system power is on. In another words, FLEX10K family offers users a great
flexibility to reconfigure different circuits with different re-configuration data.

Download circuit to the CPLD via printer parallel port:

We will use ByteBlaster connection bus to download the configuration data to the
target CPLD chip EPF10K10TC144. ByteBlaster connection bus can connect between
PC printer parallel ports and ByteBlaster plugs on the CPLD-EPF10K10 device board.
It also require Quartus II Programmer on PC to send “configuration data”. We will
follow the following procedure

1. Use connection bus to connect between PC printer parallel port and LP-
2900 experimental platforms.
2. After power on the experimental platform , LED D1 at the upper-left
corner is lightened up, and then press RESET button.
3. In Qurartus II, start programmer window by selecting “Tools >
Programmer”.
4. Open a chain description file (.cdf) which stores device name, device
order, and optional programming file name information for a design. You
can use CDFs to program or configure a device with one or more SRAM
Object Files (.sof), Programmer Object Files (.pof),
5. Add the file “mux.sof” in your cdf file.
6. Set “Hardware setup” to “ByteBlaserMV” set port to LPT1. Also set
mode to “JTAG” and give a tick to “Program/Configure”.
7. Press start in the programmer window. The circuit will be downloaded to
the CPLD chip.
8. Test the functionality of your circuit by giving different input through the
pulse switch and observing the output.

EXPERIMENT 2

Create a symbol of your 2 Way multiplexer. From the above design unit design a 4 way
multiplexer. Simulate the design to verify its functionality and implement it in a
FLEX10K Complex Programmable Logic Device (CPLD) chip. Compare the truth
table obtained in the simulation with that of the implemented chip.

EXPERIMENT 3

Suppose that there are 4 doors in a large room. There is a light in the middle of the
room. Design a digital logic circuit such that any person entering through any one of
the door will be able to ON or OFF the light.

© A.B.M. Harun-ur Rashid 6 13/11/2006

REPORT

Your report should also cover the following in addition to all the standard items.
· The schematic diagram of your circuit from Quartus II graphic editor.
· The waveform diagram from the Waveform editor of Quartus II
· The truth table obtained from the Waveform editor and the truth table obtained
from the prototype circuit built on the FLEX 10K chip.
· Discussions
· The answer of all the questions.

Reviewed By: Md. Imran Momtaz

© A.B.M. Harun-ur Rashid 7 13/11/2006

EEE 304
Experiment No. 03
Name Of The Experiment: Design and implementation of different adder, subtractor and
comparator circuits.

Important: Submit your Prelab at the beginning of the lab.

Objectives:
(i) Truth table, Boolean expression and implementation of half-adder and
half-subtractor circuits using gates.
(ii) Truth table, Boolean expression and implementation of full-adder and
full-subtractor circuits using gates.
(iii) 4-bit full-adder truth table and implementation using ICs.
(iv) 4-bit comparator design and implementation using ICs.

Apparatus:
(i) OR gate (IC 7432, 1 piece)
(ii) AND gate (IC 7408, 1 piece)
(iii) XOR gate (IC 7486, 1 piece)
(iv) IC 7483 (1 piece)
(v) IC 7485 (1 piece)
(vi) Wires, trainer board, etc.

Introduction:
Digital computers make extensive uses of adders, subtractors and comparators for
different mathematical calculations. In this experiment we will learn these operations in
detail. Binary addition, subtraction and comparison are done bit by bit. For example, two
binary digits are added in the following way:

0 + 0 = 0; 0 + 1 = 1; 1 + 0 = 1; 1 + 1 = 10

The first three operations produce 1-bit result (sum), but when both augend (to which
something is added) and addend (that which is added) are 1, the sum consists of two
digits. The higher significant bit of the result is called a carry. When augend and addend
consist of more than one bit, carry obtained from addition of two bits is added to the next
higher-ordered pair of significant bits, as shown below:

Carry from 2nd digit---->1 1<------ carry from 1st digit

11
0 1__
100

Half-Adder:
Now for the simple case of half-adder i.e. addition of two single bits, we need two input
bits and two output bits (sum and carry).
The corresponding truth table is shown below:

Table 1: Half-adder truthtable

x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

It is simple to obtain the Boolean expressions for S and C. The simplified sum of
products expressions are:

S = x ¢y + xy ¢
C = xy

Although there are a number of ways to implement the expressions using gates, the
simplest one consists of an XOR gate and an AND gate.

Prelab 1: Draw the half-adder in its simplest form.

Exercise 1: Implement the half-adder using gates.

Half-Subtractor:
The half-subtractor consists of two inputs (minuend, x; subtrahend, y) and two outputs
(difference, D; borrow, B). Its truth table is given below:

Table 2: Half-subtractor truthtable

x y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

Prelab 2: Find the D and B expressions from truth table 2 and draw the half-subtractor
using gates. Is there any similarity to half-adder?

Exercise 2: Implement the half-subtractor using gates.

Full-adder:
It consists of three inputs (augend, x; addend, y; and carry from previous digit, z) and two
outputs (sum, S and carry, C).

Prelab 3: Draw the truth table for the full-adder and find expressions of S and C from the
truth table.
Hint: Three inputs will have a total of eight combinations.

Prelab 4: Show with necessary circuit that a full adder can be implemented using two half
adder.

Prelab 5: The gate level diagram of a full-adder circuit (using two half-adders and an OR
gate) is given below. Verify that the S and C from the circuit match those found from the
truth table.

Exercise 3: Implement the full-adder.

Full-subtractor:
A-full-subtractor expressions are almost identical to those of the full-adder as given
below:
D = x¢y¢z + x¢yz ¢ + xy¢z ¢ + xyz
B = x¢y + x¢z + yz

Prelab 6: Draw the truth table for the full-subtractor.

Exercise 4: Implement the full-subtractor using gates.

4-bit Adder:
The IC 7483 is a fine implementation of a 4-bit parallel adder. It has the following pin
configuration:
The configuration is self-explanatory. C0 is input carry and C4 is output carry.

Prelab 7: How many entries will there be in the truth table of a 4-bit full-adder?

Exercise 5: Implement the 4-bit full-adder using IC 7483.

Comparator:
The comparison of two numbers is an operation that determines if one number is greater
than, less than, or equal to the other number. A magnitude comparator is a combinational
circuit that compares two numbers, A and B, and determines their relative magnitudes.
The outcome of the comparison is specified by three binary variables that indicate
whether A > B, A = B, or A < B. Consider two 4-bit binary numbers:

A = A4 A3 A2 A1
B = B4 B3 B2 B1

The following IC 7485 is a 4-bit comparator with provision for cascading.

For comparison of 4-bit numbers pins: 2,3,4 are don’t cares (i.e. their values don’t affect
output). They are required when comparing numbers having more than 4 bits. In this case
they output comparison result from lower 4-bits.

Prelab 8: You will have to compare two 12 – bit long number using comparators. Draw
the necessary circuit diagram.

Exercise 6: Implement a 4-bit comparator using IC 7485.

References:
1. Digital logic and computer design
-M. Morris Mano
Prentice Hall India
2. up to date
cmos
data and comparison tables
4000…74162244
integrated circuits
bpb publications

Reviwed By: Md. Imran Momtaz

EEE 304
Experiment No. 04
Name Of The Experiment: Design of Decoder/Encoder/Multiplexer
circuit
Important: Submit your Prelab at the beginning of the lab.

Objectives:
(i) Implementation of simple decoding technique
(ii) Introduction of priority concept in encoding/decoding
(iii) Study different aspects of MUX(Data Selector)

Apparatus:
(i) OR gate (IC 7432, 1 piece)
(ii) AND gate (IC 7408, 2 piece)
(iii) NOT gate (IC 7404, 1 piece)
(iv) IC 74150 (16X1 MUX)(1 piece)
(v) IC 74153 (dual 4X1 MUX)(1 piece)
(vi) IC 74154 (4 line to 16 line decoder)(1 piece)
(vii) Wires, trainer board, etc.

Introduction to decoder logic:

The basic function of a decoder circuit is to detect the presence of a specified combination of
bits(code) on its inputs and to indicate the presence of that code by a specified output level. In its
general form, a decoder has n input lines to handle n bits and from one to 2n output lines to
indicate the presence of one or more n-bit combinations.
Example:
Suppose we need to construct a decoder system which has A and B(i.e 2 bits) as its input and we
have to determine the presence of each combination of these inputs (22=4 combination)by
observing the output lines(one for each combination). The presence of AB=11 can be determined
by observing the output of an AND gate whose output is AB. Similarly logic equation for other 3
combinations can be found. Then , if we find out which output line is active ,we can determine
input. The complete circuit diagram is shown below:

Prepared by :Dr. A.B.M.H. Rashid, Md Abu Jafar Siddiq Date:16/12/06

Prelab 1:Develop the logic required to detect the binary code 10010 and produce an active
LOW output.

Exercise 1: Construct a decoder circuit which can detect the presence of 8 and 15 at the
input.

Exercise 2: Construct a 5 bit(i.e 5 line to 32 line)decoder circuit by cascading two 4

line to 16 line decoder(IC 74154).

The priority encoder circuit:

An encoder essentially performs a “reverse” decoder function. It accepts an active level on one
of its inputs representing a digit, such as a decimal or octal digit, and converts it to a coded
output, such as BCD or binary.

Example: The decimal to binary encoder

This type of encoder has ten inputs-one for each decimal digit-and four outputs corresponding to
the BCD code. The BCD code is listed in the following table:

Decimal Digit
BCD code
A3 A2 A1 A0
00 0 0 0
10 0 0 1
20 0 1 0
30 0 1 1
40 1 0 0
50 1 0 1
60 1 1 0
70 1 1 1
81 0 0 0
91 0 0 1

Note that A0 output should be high when any of 1,3,5,7,9 input lines is present at the input.
Hence the expression for A0 will be:
A0 =1+3+5+7+9
Similarly A1=2+3+6+7
A2=4+5+6+7
A3= 8+9

The input lines do not always exhibits same priority. There may be cases where some inputs
have higher priorities than others. In such cases ,when two input lines are active simultaneously,
the output choose to respond to the input line with highest priority. The encoder described above
can be modified to function as a priority encoder. In that case , the encoder will produce BCD
output corresponding to the highest order decimal digit input that is active and will ignore any
other active inputs.For instance, if the 6 and 3 inputs are both active, the BCD output is
0110(which represents decimal 6).

Now lets look at the requirements for the priority detection logic.This logic circuitry prevents a
lower order digit input from disrupting the encoding of a higher order digit. We want to examine

Prepared by :Dr. A.B.M.H. Rashid, Md Abu Jafar Siddiq Date:16/12/06

the output A0. Note that A0 is HIGH when 1,3,5,7 or 9 is high. Note that Digit 1 should activate
the A0 output only if no higher order digits other than those that also activate A0 are HIGH. The
requirements can be stated as follows:

1.A0 is HIGH if 1 is HIGH and 2,4,6 and 8 are LOW

2.A0 is HIGH if 3 is HIGH and 4,6 and 8 are LOW
3.A0 is HIGH if 5 is HIGH and 6 and 8 are LOW
4.A0 is HIGH if 7 is HIGH and 8 are LOW
5.A0 is HIGH if 9 is HIGH

A0 output is HIGH if any of the above 5 conditions occur. Hence,

- - - - - - - - - -
A0= 12 4 68 + 34 68 + 5 68 + 7 8 + 9

Prelab 2: For the above example of priority encoder, find the logic equations for A1,A2
and A3

Exercise 3: Construct a priority encoder which implement the encoding of 0,3,1,2 with
descending priority(i.e 0 has the highest priority and 2 has the lowest)

Multiplexer or Data Selector:

A multiplexer is a device that allows digital information from several sources to be routed onto a
single line for transmission over that line to a common destination. The basic multiplexer has
several data input lines and a single output line. It also has data selector inputs, which permit
digital data on any one of the inputs to be switched to the output line. Multiplexers are also
known as data selector.

*** C here stands for selector switch

Note from the table that when C is 1, output is connected to the input B and in that case the state
of input at A does not have any effect on the output Y. Similarly when C is 0, output is
connected to the input A.
Following is the top view of IC 74LS153 which is a dual 4 line to 1 line Multiplexer(i.e it
contains two 4 line to 1 line MUX). Its internal circuit diagram is also given.

Prepared by :Dr. A.B.M.H. Rashid, Md Abu Jafar Siddiq Date:16/12/06

Exercise 4: Implement the Multiplexing function using IC 74LS153
Combinational logic implementation using MUX:

A useful application of the data selector is in the generation of combinational logic functions in
sum of products form. When used in this way, the device can replace discrete gates, can often
greatly reduce the number of ICs and can make the design changes much easier. A good example
is given below.

Exercise 5: Implement the following logic using IC 74150

F (A,B,C,D)=∑(1,3,5,7,9,11,13,15)
C

Cascading of MUX to increase the number of input line:

We can cascade several MUXs to construct a single MUX with higher number of input lines.

Prepared by :Dr. A.B.M.H. Rashid, Md Abu Jafar Siddiq Date:16/12/06

In the following example we have constructed a 4 line to 1 line MUX using 3 two line to one line
MUX

S1 S0 Input connected
to the output
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Exercise 6: Implement a 8 line to 1 line MUX using two 4 line to 1 line MUX(found in IC
74153) and an OR gate.

Home work:
1. Design the same circuit as described in Exercise 6 using three 4 line to 1 line MUX
2. Implement a 10 line to 1 line MUX using two 4 line to 1 line MUX, one 2 line to 1 line MUX
and a 3 input or gate. Can you suggest any alternative design solution?
3. Explain Fan – in and Fan – out. Explain these effects for a n to 2n decoder.

Reviewed By: Md. Imran Momtaz

Prepared by :Dr. A.B.M.H. Rashid, Md Abu Jafar Siddiq Date:16/12/06

DEPARTMENT OF ELECTRICAL AND ELECTROINC
ENGINEERING
BANGLADESH UNIVERSITY OF ENGINEERING &
TECHNOLOGY
EEE 304 : Digital Electronics Laboratory

EXPT NO. 5: DESIGN OF ARITHMATIC CIRCUITS USING

VERILOG AND IMPLEMENTATION IN FPGA.

PRELAB

Submit your Prelab before starting the experiment.

1. Write verilog code to implement the function f(x1,x2,x3)=åm(1,2,3,6).

2. Write verilog code to describe the following functions

f1=x1x3+x2x3+x3x4+x1x4
f2=(x1+x3).(x1+x2+x4).(x2+x3+x4)

3. Write the structural verilog code for the one bit full adder circuit using
gate level primitives. (Hint : See article 5.5.2 page 265-270 of your text
book : Fundamentals of Digital Logic with Verilog Design by Stephen
brown and Zvonko Vranesic, Tata McGraw Hill)

4. Write the behavioral verilog code of the one bit full adder circuit. (Hint :
See article 5.5.2 page 265-270 of your text book : Fundamentals of
Digital Logic with Verilog Design by Stephen brown and Zvonko
Vranesic, Tata McGraw Hill)

1. INTRODUCTION:

Verilog is the most popular Hardware Description Language (HDL) for describing
digital circuits. It has also become popular for use in design entry in CAD systems. The
CAD tool synthesize the verilog code into a hardware implementation of the described
circuit. Verilog has a number of construct similar to the C programming Language.

Verilog Syntax

Identifier: Identifier are the names used to give for an object (such as signal name,
module name, instance name etc.) used in the design. It must start with a letter or under
score (a-z, A-Z, _)

Keyword: Verilog has a number of keywords or reserved words that can not be used as
identifiers or any other purpose than it is intended for. All keywords are used in lower

© A.B.M. Harun-ur Rashid 1 20/12/2006

case. Some examples of keywords are module, input, output, and, or, xor, assign,
always, if, else etc.
Comment: A comment begins with the double slash “//” and continue to the end of the
line.

Case Sensitivity: Verilog is a case sensitive language. All verilog keywords are lower
case.

Representation of Digital circuit in verilog

Verilog allows the designer to represent circuits in two fundamentally different ways as
follows-
1. Structural Representation: Here small circuits are represented by logic gates
or even with transistors. A large circuit is represented by writing code that
connects such element together.

For example a two input AND gate with inputs x1 and x2 and output y is
denoted by
and (y,x1,x2).

2. Behavioral Representation: In behavioral representation a circuit is described

by using logic expressions and programming constructs that define the behavior
of the circuit but not its actual structures in terms of gates. Behavioral
representation again can be done in the following two ways
i) Continuous assignments Here the circuit is defined using Boolean
expression. The assign keyword provides a continuous assignment for the
signal f. For example:
assign f=(x1 & x2)|(~x2 & x3);
The word continuous stems from the use of verilog for simulation; whenever
any signal on the right hand side change its state, the value of f will be re-
evaluated.
ii) Procedural assignment: If the complexity of circuit increases procedural
assignments are used. In procedural assignment approach, the functional
behavior of the circuit is described using the keyword ‘always’. Sensitivity list
is used with the always statement which contains list of specific input which
have effect on the outputs. Whenever any event (change) occurs in any of the
parameters in the sensitivity list, the always loop will execute.

For example:
always@(x1 or x2 or x3)
if (x2==1)
f=x1;
else
f=x3;

Problem 1

(a) Write the Verilog code for the full adder circuit using gate level primitives.
Simulate the circuit and observe the wave form.

© A.B.M. Harun-ur Rashid 2 20/12/2006

(b) Repeat the above experiment with the behavioral description of Verilog code and
name the module as fulladd.

Simulate the designs to verify its functionality and implement it in the FLEX10K Field
Programmable Gate Array (FPGA) chip of the Digital Logic Design Lab (LP-2900)
board.

Experimental Procedure

1. Create a new project file. Choose device EPF10K10TC144-3.

2. In the Quartus II window Select “File > New > Verilog HDL file

3. Write the Verilog code of the full adder. In order to observe the output through the
LEDs in the FPGA Digital Logic Design Lab board LP2900, the common anode of the
LEDs (pin 141) have to be connected to logic high. For this purpose use a signal (say
LED_COM) and assign it to logic 1.

4. Now perform Analysis and Synthesis, Fitter, Assembler and Timing Analyzer.

5. Create Vector Waveform File. Input Clock as input with time period of 100 ns, 200
ns and 300 ns for input 1, input 2 and carry in respectively. Observe the simulation
waveform output and verify the functionality.

6. Note that signals have been assigned arbitrarily to the pins of FLEX10K chip by the
fitter program. Now reassign the signals to the desired pins by using
“Assignments>Assign Pins”. Connect the input1, input2 and carryin to the data
switch SW1 (pin 47), SW2 (pin 48) and SW3 (pin 49) respectively. Observe the SUM
and the CARRY output in LED L2 (pin 8) and L1 (pin 7) respectively. Also connect
the common anode of the LEDs (LED_COM signal defined previously) to pin 141.

7. Download the design in FPGA. Verify the functionality of the chip and take
signature from the instructor in the data sheet.

Problem 2

Write the Verilog code of a 4-bit ripple carry adder by instantiating the fulladd module
designed in problem 1 as a subcircuit. Represent one of the four-bit numbers to be
added by the four signals x3(MSB),x2,x1,x0(LSB), and the other number as y3(MSB)
,y2,y1,y0(LSB). Represent the sum as s3,s2,s1,s0 and the carry output as carryout.
.
Assign the signals x0,x1,x2 and x3 into data switch SW4 (pin 51), SW3 (pin 49), SW2
(pin 48) and SW1 (pin 47) respectively. Similarly assign the signals y0,y1,y2,y3 into
the data switch SW8 (pin 63), SW7 (pin 62), SW6 (pin 60) and SW5 (pin 59)
respectively. Connect the output signals s0,s1,s2,s3 into the LEDs L12( pin 20), L11
(pin 19), L10 ( pin 18) and L9 (pin 17) respectively. Connect the carryin signal to SW9
(pin 64), carryout signal to L1 (pin 7) and the LED_COM signal to pin 141.

© A.B.M. Harun-ur Rashid 3 20/12/2006

Download the design in FPGA. Verify the functionality of the chip and take signature
from the instructor in the data sheet.

Problem 3

Write the Verilog code of a n-bit ripple carry adder using generic specification.
Synthesize your generic code for a 4-bit ripple carry adder by assigning n=4. Assign the
signals as in problem 2 and check the functionality of the chip and collect signature
from the instructor in the data sheet

Problem 4

Write the Verilog code of an adder/sub tractor circuit which will add two 4 bit numbers
when the control signal ctrl=0 and subtract the two 4-bit number when the control
signal ctrl=1. Assign the signals as in problem 2 and check the functionality of the chip
and collect signature from the instructor in the data sheet

REPORT

For each of the four problems above provide the following in your report.
· The verilog source code of the problem.
· The simulated waveform done in Quartus II
· The data sheet with signature from the instructor.
· Discussions and comment

Question:
1. Write the verilog code of a 4-bit ALU that would perform two arithmetic and two
logic functions that are selected by a 2-bit input. The four operations are add, subtract,
AND and OR.
2. What are 'BLOCKING' and 'NON – BLOCKING' statements? Differentiate them in
brief.

Reviewed By: Md. Imran Momtaz

© A.B.M. Harun-ur Rashid 4 20/12/2006

Program Listing

1. Structural description of one bit full adder

module fulladd (cin, x,y,s,cout);

input cin,x,y;
output s, cout;
wire z1,z2,z3;
xor (s,x,y,cin);
and (z1,x,y);
and(z2, x,cin);
and (z3,y,cin);
or (cout, z1,z2,z3);
endmodule

2. Behavioral description of one bit full adder

module fulladd_behav(cin,xx,yy,s,cout,LED_COM);
input cin,xx,yy;
output cout,s;
inout LED_COM;

assign s=xx^yy^cin;
assign cout=(xx&yy)|(xx&cin)|(yy&cin);
assign LED_COM=1;
endmodule

3. Four bit full adder

module adder4(carryin, x3,x2,x1,x0,y3,y2,y1,y0,s3,s2,s1,s0,carryout,

LED_COM);
input carryin, x3,x2,x1,x0,y3,y2,y1,y0;
output s3,s2,s1,s0,carryout;
inout LED_COM;
wire c1,c2,c3;

fulladd stage0 (carryin, x0,y0,s0,c1);

fulladd stage1 (c1, x1,y1,s1,c2);
fulladd stage2 (c2, x2,y2,s2,c3);
fulladd stage3 (c3, x3,y3,s3,carryout);
assign LED_COM=1;
endmodule

module fulladd(cin,xx,yy,s,cout);
input cin,xx,yy;
output cout,s;

assign s=xx^yy^cin;
assign cout=(xx&yy)|(xx&cin)|(yy&cin);
endmodule

3. Four bit adder_Subtractor

module adder_sub4(carryin,
x3,x2,x1,x0,y3,y2,y1,y0,s3,s2,s1,s0,carryout, LED_COM);
input carryin, x3,x2,x1,x0,y3,y2,y1,y0;
output s3,s2,s1,s0,carryout;

© A.B.M. Harun-ur Rashid 5 20/12/2006

inout LED_COM;
wire c1,c2,c3,yy0,yy1,yy2,yy3;

add_sub (carryin,y0,y1,y2,y3,yy0,yy1,yy2,yy3);

fulladd stage0 (carryin, x0,yy0,s0,c1);

fulladd stage1 (c1, x1,yy1,s1,c2);
fulladd stage2 (c2, x2,yy2,s2,c3);
fulladd stage3 (c3, x3,yy3,s3,carryout);
assign LED_COM=1;
endmodule

module fulladd(cin,xx,yy,s,cout);
input cin,xx,yy;
output cout,s;

assign s=xx^yy^cin;
assign cout=(xx&yy)|(xx&cin)|(yy&cin);
endmodule

module add_sub(ctrl,y0,y1,y2,y3,yy0,yy1,yy2,yy3);
input ctrl, y0,y1,y2,y3;
output yy0,yy1,yy2,yy3;
xor xor0(yy0,ctrl,y0);
xor xor1(yy1,ctrl,y1);
xor xor2(yy2,ctrl,y2);
xor xor3(yy3,ctrl,y3);
endmodule

© A.B.M. Harun-ur Rashid 6 20/12/2006

DEPARTMENT OF ELECTRICAL AND ELECTROINC
ENGINEERING
BANGLADESH UNIVERSITY OF ENGINEERING &
TECHNOLOGY
EEE 304 : Digital Electronics Laboratory

EXPT NO. 6: DESIGN, SIMULATION AND TEST OF

COMIBNATION CIRCUITS USING VERILOG AND
IMPLEMENTATION IN FPGA.

PRELAB

Submit your Prelab before starting the experiment.

1. Write verilog code of a 8/1 Multiplexer.

2. Write verilog code of a 1/8 Demultiplexer

3. Write the verilog code of BCD to Seven Segment Decoder

4. Write the verilog code of a 4 bit priority encoder with the MSB to LSB
bit in order of decreasing priority.
5. Is it possible to implement a demux using a decoder? If yes, how? If no,
why?
6. Is it possible to implement a mux using an encoder? If yes, how? If no,
why?

Problem 1

Write the verilog code of 8:1 multiplexer. Simulate and test the circuit using Quratus II
software. The timing diagram must be checked after Fitter and Assembler is run.
Implement the circuit in FPGA. Assign the pins according to the following table.

Signal Pin of FPGA chip Signal Pin of FPGA chip

S0 Pin 67 (SW9) D0 Pin 47 (SW1)
S1 Pin 65 (SW10) D1 Pin 48 (SW1)
S2 Pin 64 (SW11) D2 Pin 49 (SW1)
D3 Pin 51 (SW1)
D4 Pin 59 (SW1)
D5 Pin 60 (SW1)
D6 Pin 62 (SW1)
D7 Pin 63 (SW1)
f Pin 7 (L1)
LED_COM Pin 141

© A.B.M. Harun-ur Rashid 1 20/12/2006

Here S0,S1 and S2 are the select bit and D0..D7 are the input signal line and f is the
output signal.

Problem 2 Design, simulation and implementation of a 8/1 DEMUX

Write the verilog code of 1:8 demultiplexer. Simulate and test the circuit using Quratus
II software. The timing diagram must be checked after Fitter and Assembler is run.
Implement the circuit in FPGA. Assign the pins according to the following table

Signal Pin of FPGA chip Signal Pin of FPGA chip

S0 Pin 67 (SW9) D Pin 47 (SW1)
S1 Pin 65 (SW10) Y0 Pin 7 (L1)
S2 Pin 64 (SW11) Y1 Pin 8 (L2)
Y2 Pin 9 (L3)
Y3 Pin 10 (L4)
Y4 Pin 11 (L5)
Y5 Pin 12 (L6)
Y6 Pin 13 (L7)
Y7 Pin 14 (L8)
LED_COM Pin 141

Here S0,S1 and S2 are the select bit and Y0..Y7 are the input signal and D is the output
signal.

Problem 3 Design, simulation, test and implementation of a 8 line MUXDEMUX

Write the verilog code of 8 input multiplexer-demultiplexer circuit. Simulate and test
the circuit using Quratus II software. The timing diagram must be checked after Fitter
and Assembler is run. Implement the circuit in FPGA. Assign the pins according to the
following table

Signal Pin of FPGA chip Signal Pin of FPGA chip

S0 Pin 67 (SW9)
S1 Pin 65 (SW10) Y0 Pin 7 (L1)
S2 Pin 64 (SW11) Y1 Pin 8 (L2)
D0 Pin 47 (SW1) Y2 Pin 9 (L3)
D1 Pin 48 (SW2) Y3 Pin 10 (L4)
D2 Pin 49 (SW3) Y4 Pin 11 (L5)
D3 Pin 51 (SW4) Y5 Pin 12 (L6)
D4 Pin 59 (SW5) Y6 Pin 13 (L7)
D5 Pin 60 (SW6) Y7 Pin 14 (L8)
D6 Pin 62 (SW7) LED_COM Pin 141
D7

© A.B.M. Harun-ur Rashid 2 20/12/2006

Problem 4 Design, simulation , test and implementation of a BCD to Seven Segment
Decoder.

Write the verilog code of a BCD to Seven Segment decoder. Simulate and test the
circuit using Quratus II software. The timing diagram must be checked after Fitter and
Assembler is run. Implement the circuit in FPGA. Assign the pins according to the
following table.

Signal Pin of FPGA chip Signal Pin of FPGA chip

BCD[0] Pin 51 (SW4) A Pin 23
BCD[1] Pin 49 (SW3) B Pin 26
BCD[2] Pin 48 (SW2) C Pin 27
BCD[3] Pin 47(SW1) D Pin 28
E Pin 29
F Pin 30
G Pin 31
De1 Pin 33
De2 Pin 36
De3 Pin 37

Here BCD[0]..BCD[3] are the BCD input. A,B,C,D,E,F and G are the Seven LEDs of
the seven segment display.
The signals De1 De2 and De3 are connected to a 74138 3to8 Decoder whose fist six
outputs (Y0..Y6) are connected to the common cathodes of the six seven segment
display in LP2900 board. Assign De1=1 De2=0 and De3=1 so that the rightmost seven
segment display is activated. Test your decoder with all the BCD inputs.

Problem 5 Design, simulation , test and implementation of a Priority encoder.

Write the verilog code for the priority encoder defined in the following table

W3 W2 W1 W0 Y1 Y0 Z
0 0 0 0 d d 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 x X 1 0 1
1 x x x 1 1 1

Simulate and test the circuit using Quratus II software. The timing diagram must be
checked after Fitter and Assembler is run. Implement the circuit in FPGA.

REPORT
For each of the four problems above provide the following in your report.
· The verilog source code of the problem.
· The simulated waveform done in Quartus II
· The data sheet with signature from the instructor.
· Discussions and comment
wed By: Md. Imran Momtaz

© A.B.M. Harun-ur Rashid 3 20/12/2006

EEE 304
Experiment No. 07

Name Of The Experiment: Sequential circuit design –Latch, Flip-flop and Registers

Important: Submit your Prelab at the beginning of the lab.

Prelab 1: Construct a S-R Latch and a Gated S-R Latch circuit using NAND gate and NOR gate.
Also draw the truth table for them.

Prelab 2: Construct a Gated D Latch circuit using Universal gate and draw the truth table for
them. Can you construct a Gated D Latch out of a Gated S-R Latch?

Prelab 3: What is the problem of using edge triggered S-R flip flop? How is this problem
solved in edge triggered J-K flip-flop and D type flip flop?

Part A:Introduction to Latch and Flip- Flop:

While gates had to be built directly from transistors, latches can be built from gates, and flip-flops can be
built from latches. This fact will make it somewhat easier to understand latches and flip-flops. Both
latches and flip-flops are circuit elements whose output depends not only on the current inputs, but also
on previous inputs and outputs. The difference between a latch and a flip-flop is that a latch does not have
a clock signal, whereas a flip-flop always does.

How can we make a circuit out of gates that is not combinatorial? The answer is feed-back, which means
that we create loops in the circuit diagrams so that output values depend, indirectly, on themselves. If
such feed-back is positive then the circuit tends to have stable states, and if it is negative the circuit will
tend to oscillate.
A latch has positive feedback. Here is an example of a simple latch:

This latch is called SR-latch, which stands for set and reset.

Latches are asynchronous, which means that the output changes very soon after the input changes. Most
computers today, on the other hand, are synchronous, which means that the outputs of all the sequential
circuits change simultaneously to the rhythm of a global clock signal.

On the other hand, Flip-flops are synchronous bistable devices. The term synchronous means the output
changes state only when the clock input is triggered. That is, changes in the output occur in
synchronization with the clock.

In this experiment, the three basic categories of bistable elements are emphasized: edge-triggered flip-
flop, pulse-triggered (master-slave) flip-flop, and data lock-out flip-flop. Each type will be associated
with both D and J-K configuration.

Edge Triggered flipflop :

If the Enabler node of a gated latch is fed with a clock pulse, then the effect of input change will show up
at the output when the clock goes high. But the high time of clock is not a very short one. During this
time, any change in input will go to the output. It may not always be desirable. To provide a very short

1
window for output state transition, we use the edge of the clock pulse. Flip Flops using this edge
transition is known as edge triggered flipflop.

An edge triggered flip flop changes state either at the positive edge (rising edge) or at the negative
edge(falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock. The
three basic types are introduced here: S-R, J-K and D.

The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to
the flip-flop's output only on the triggering edge of the clock pulse.On the other hand, the direct set (SET)
and clear (CLR) inputs are called asynchronous inputs, as they are inputs that affect the state of the flip-
flop independent of the clock. For the synchronous operations to work properly, these asynchronous
inputs must both be kept LOW.

Edge-triggered S-R flip-flop :

The basic operation is illustrated below, along with the truth table for this type of flip-flop. The
operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except
that the falling edge of the clock pulse is the triggering edge.

Note that the S and R inputs can be changed at any time when the clock input is LOW or HIGH (except
for a very short interval around the triggering transition of the clock) without affecting the output. This is
illustrated in the timing diagram below:

Edge-triggered J-K flip-flop :

The J-K flip-flop works very similar to S-R flip-flop. The only difference is that this flip-flop has NO
invalid state. The outputs toggle (change to the opposite state) when both J and K inputs are HIGH. The
truth table is shown below.

Edge-triggered D flip-flop :
The operations of a D flip-flop is much more simpler. It has only one input addition to the clock. It is very
useful when a single data bit (0 or 1) is to be stored. If there is a HIGH on the D input when a clock pulse
is applied, the flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock pulse is
applied, the flip-flop RESETs and stores a 0. The truth table below summarize the operations of the

2
positive edge-triggered D flip-flop. As before, the negative edge-triggered flip-flop works the same
except that the falling edge of the clock pulse is the triggering edge.

Exercise 1: Construct a negative edge triggered D type flip flop using universal gate

Exercise 2: Modify the circuit in exercise 1 to a positive edge triggered J-K flipflop
with active low preset and clear

Pulse-Triggered (Master-Slave) Flip-flops :

The term pulse-triggered means that data are entered into the flip-flop on the rising edge of the
clock pulse, but the output does not reflect the input state until the falling edge of the clock
pulse. As this kind of flip-flops are sensitive to any change of the input levels during the clock
pulse is still HIGH, the inputs must be set up prior to the clock pulse's rising edge and must not
be changed before the falling edge. Otherwise, ambiguous results will happen.

The three basic types of pulse-triggered flip-flops are S-R, J-K and D. Their logic symbols are
shown below. Notice that they do not have the dynamic input indicator at the clock input but
have postponed output symbols at the outputs.

The truth tables for the above pulse-triggered flip-flops are all the same as that for the edge-triggered
flip-flops, except for the way they are clocked. These flip-flops are also called Master-Slave flip-
flops simply because their internal construction are divided into two sections. The slave section is
basically the same as the master section except that it is clocked on the inverted clock pulse and is
controlled by the outputs of the master section rather than by the external inputs. The logic diagram
for a basic master-slave S-R flip-flop is shown below.

Data Lock-Out Flip-flops

The data lock-out flip-flop is similar to the pulse-triggered (master-slave) flip-flop except it has a
dynamic clock input. The dynamic clock disables (locks out) the data inputs after the rising edge of
the clock pulse. Therefore, the inputs do not need to be held constant while the clock pulse is HIGH.
The master section of this flip-flop is like an edge-triggered device. The slave section becomes a

3
pulse-triggered device to produce a postponed output on the falling edge of the clock pulse.
The logic symbols of S-R, J-K and D data lock-out flip-flops are shown below. Notice they all have
the dynamic input indicator as well as the postponed output symbol.

Exercise 3: Construct a master slave J-K flip flop

Frequency Division (application of flip-flop):

When a pulse waveform is applied to the clock input of a J-K flip-flop that is connected to toggle, the
Q output is a square wave with half the frequency of the clock input. If more flip-flops are connected
together as shown in the figure below, further division of the clock frequency can be achieved.

The Q output of the second flip-flop is one-fourth the frequency of the original clock input. This is
because the frequency of the clock is divided by 2 by the first flip-flop, then divided by 2 again by
the second flip-flop. If more flip-flops are connected this way, the frequency division would be 2 to
the power n, where n is the number of flip-flops.

Exercise 4: Construct a divide by 8 device using IC 7476.

Part B : Introduction to registers:

Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a
group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the
next flip-flop. Most of the registers possess no characteristic internal sequence of states. All the flip-
flops are driven by a common clock, and all are set or reset simultaneously. In this chapter, the basic
types of shift registers are studied, such as Serial In - Serial Out, Serial In - Parallel Out, Parallel In -
Serial Out, Parallel In - Parallel Out, and bidirectional shift registers. A special form of counter - the
shift register counter, is also introduced.

Serial In - Serial Out Shift Registers :

4
A basic four-bit shift register can be constructed using four D flip-flops, as shown below. The
operation of the circuit is as follows. The register is first cleared, forcing all four outputs to zero. The
input data is then applied sequentially to the D input of the first flip-flop on the left (FF0). During
each clock pulse, one bit is transmitted from left to right. Assume a data word to be 1001. The least
significant bit of the data has to be shifted through the register from FF0 to FF3.

In order to get the data out of the register , they must be shifted out serially. This can be done
destructively or non-destructively. For destructive readout, the original data is lost and at the end of the
read cycle, all flip-flops are reset to zero. To avoid the loss of data, an arrangement for a non-
destructive reading can be done by adding two AND gates, an OR gate and an inverter to the system.
The construction of this circuit is shown below.

The data is loaded to the register when the control line is HIGH (ie WRITE). The data can be shifted
out of the register when the control line is LOW (i. e READ). This is shown in the animation below

Serial In - Parallel Out Shift Registers :

For this kind of register, data bits are entered serially in the same manner as discussed in the last
section. The difference is the way in which the data bits are taken out of the register. Once the data are
stored, each bit appears on its respective output line, and all bits are available simultaneously. A
construction of a four-bit serial in - parallel out register is shown below.

Parallel In - Serial Out Shift Registers :

A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-flops and NAND
gates for entering data (ie writing) to the register.

5
D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least
significant bit. To write data in, the mode control line is taken to LOW and the data is clocked in. The
data can be shifted when the mode control line is HIGH as SHIFT is active high. The register
performs right shift operation on the application of a clock pulse

Parallel In - Parallel Out Shift Registers

For parallel in - parallel out shift registers, all data bits appear on the parallel outputs immediately
following the simultaneous entry of the data bits. The following circuit is a four-bit parallel in - parallel
out shift register constructed by D flip-flops.

The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the
data at the D inputs appear at the corresponding Q outputs simultaneously.
Exercise 5: A computer or microprocessor-based system commonly requires incoming data to be in
parallel format. But frequently, these systems must communicate with external devices that send or
receive serial data. Construct a circuit that converts a serial data into 3 bit parallel data(use IC 7474).

Exercise 6: Construct a circuit that first read a 3 bit parallel data and then converts it to serial data.

Reference: Digital Fundamentals- Floyd

Your report should cover
· All circuit diagrams for the constructed circuits
· Truth Table
· Relevant discussions

Reviewed By: Md. Imran Momtaz

6
DEPARTMENT OF ELECTRICAL AND ELECTROINC
ENGINEERING
BANGLADESH UNIVERSITY OF ENGINEERING &
TECHNOLOGY
EEE 304 : Digital Electronics Laboratory

EXPT NO. 8: DESIGN, SIMULATION AND TEST OF

SEQUENTIAL CIRCUITS USING VERILOG AND
IMPLEMENTATION IN FPGA.

Objective: The objective of this experiment is to design sequential circuit with

CAD tools by using verilog HDL. We will learn various techniques to write
verilog codes for sequential circuits.

PRELAB

Submit your Prelab before starting the experiment.

1. Write the verilog code of a D type Flip-flop with asynchronous reset.

Also draw its logic circuit diagram.
2. Write the verilog code of a D type Flip-flop with synchronous reset. Also
draw its logic circuit diagram.
3. Write the verilog code of a T type flip-flop with synchronous reset. Also
draw its logic circuit diagram.
4. Write the verilog code of a 4 bit up counter with asynchronous reset. Also
draw its logic circuit diagram.
5. Write down the verilog code of a 4-bit counter which has three control
inputs for operations: Up, Down and Load. The order of precedence is
Load, Up and Down.

Problem 1 Design, simulation and implementation of basic flip-flop’s

in FPGA.

Write a verilog program which will generate a D fillip flop with asynchronous reset &
negative edge clock, a D flip-flop with synchronous reset & positive edge clock, and a
T flip flop with synchronous reset & positive edge clock as shown below.

D0 Q0 D1 Q1 T Q2
47 7 48 8 49 9
RST RST RST
56 62 63
clk0 clk1 clk2
54 124 126

© A.B.M. Harun-ur Rashid 1 20/12/2006

Simulate and test the circuit using Quartus II software. Select the Flex 10K device
EPF10K10TC144-4. The timing diagram must be checked after Fitter and Assembler is
run. Implement the circuit in FPGA board LP2900. Assign the pins as shown in the
diagram above. .

Show the functionality of the fabricated circuit to your instructor and take signature in
the data sheet.

Problem 2 Design, simulation and FPGA implementation of a 4-bit binary up

counter.

Write a verilog program which will generate a 4-bit up counter with negative edge
asynchronous reset and positive edge clock. Simulate and test the circuit using Quratus
II software. Select the Flex 10K device EPF10K10TC144-4. The timing diagram must be
checked after Fitter and Assembler is run. Implement the circuit in FPGA board
LP2900. Assign the pins as shown in the figure below.

Q3:Q0
RST
5 7,8,9,10
4
CLK
124
Show the functionality of the fabricated circuit to your instructor and take signature in
the data sheet.

Problem 3 Design, simulation , test and FPGA implementation of a 4 bit binary up-
down counter.

Write the verilog code of a binary up-down counter with provision to load data. The
order of precedence is Load, Up and Down. Simulate and test the circuit using Quratus
II software. Select the Flex 10K device EPF10K10TC144-4. The timing diagram must be
checked after Fitter and Assembler is run. Implement the circuit in FPGA board
LP2900. Assign the pins as shown in the figure below.

In3 : In0
47,48,49,51
Q3:Q0
Load
59 7,8,9,10
Up
60
Down
62
CLK
63

© A.B.M. Harun-ur Rashid 2 20/12/2006

Show the functionality of the fabricated circuit to your instructor and take signature in
the data sheet.

Problem 4 Design, simulation, test and FPGA implementation of a 4-bit end around
shift register.

Write the verilog code of a 4-bit end around shift register. The register right shift the
data one bit at the positive edge of the clock when the load signal L is low. It load data
at the positive edge of the clock when the L signal is high. Simulate and test the circuit
using Quratus II software. Select the Flex 10K device EPF10K10TC144-4. The timing
diagram must be checked after Fitter and Assembler is run. Implement the circuit in
FPGA board LP2900. Assign the pins as shown in the figure below.
D3 D2 D1 D0

D3 Q3 D2 Q2 D1 Q1 D0 Q0
47 7 48 8 49 9 51 10
L L L L
6
CLK CLK CLK CLK
26
3

REPORT

For each of the four problems above`` provide the following in your report.
· The verilog source code of the problem.
· The simulated waveform done in Quartus II
· The data sheet with signature from the instructor.
· Discussions and comment

Additional questions

(1) Write the verilog code of a n-bit end around shift register with provision to load
data depending on a control signal sel.
(2) Propose a digital scheme which will detect the number of 1’s in a 4-bit number and
it will do end around left shift total number of 1s’ times. e. g. If the number is 0101, it
will do end around left shift twice. If it is 1011, it will end around left shift thrice. This
is NOT a verilog problem. You will have to draw logic circuit.

Reviewed By: Md. Imran Momtaz

© A.B.M. Harun-ur Rashid 3 20/12/2006

Problem-1

module DT(D0,D1,T,RST0,CLK0,RST1,CLK1,RST2,CLK2,Q0,Q1,Q2,LED_COM);
input D0,D1,T,RST0,RST1, RST2,CLK0,CLK1,CLK2;
output Q0,Q1,Q2;
inout LED_COM;

D_FFASYN(D0,RST0,CLK0,Q0);
D_FFSYN(D1,RST1,CLK1,Q1);
T_FFSYN(T,RST2,CLK2,Q2);
assign LED_COM=1;
endmodule

module D_FFASYN(D0,RST0,CLK0,Q);
input D0, RST0, CLK0;
output Q;
reg Q;
always@(negedge CLK0 or negedge RST0)
begin
if(RST0==0) Q=0;
else Q=D0;
end
endmodule

module D_FFSYN(D1,RST1,CLK1,Q);
input D1, RST1, CLK1;
output Q;
reg Q;
always@(posedge CLK1)
begin
if(RST1==0) Q=0;
else Q=D1;
end
endmodule

module T_FFSYN(T,RST2,CLK2,Q);
input T, RST2, CLK2;
output Q;
reg Q;
always@(posedge CLK2)
begin
if(RST2==0) Q=0;
else begin
if (T)Q=~Q;
else Q=Q;
end
end
endmodule

© A.B.M. Harun-ur Rashid 4 20/12/2006

Problem-2

module upcounter(rst, clk, Q, LED_COM);

input rst, clk;
output [3:0] Q;
inout LED_COM;
reg [3:0] Q;
always@(posedge clk or negedge rst) begin
if (rst==0)Q=0;
else Q=Q+1;
end
assign LED_COM=1;
endmodule

Problem-3
module counter (up,down,load,clk,In,Q,LED_COM);
input up,down,load,clk;
input [3:0]In;
output [3:0]Q;
reg [3:0] Q;
inout LED_COM;
always@(posedge clk)
begin
if(load)
Q=In;
else if (up)
Q=Q+1;
else if (down)
Q=Q-1;
else
Q=Q;
end
assign LED_COM=1;
endmodule

Problem-4
module ShiftR4(D,L,Clock,Q,LED_COM);
input [3:0]D;
input L,Clock;
output [3:0]Q;
reg [3:0] Q;
inout LED_COM;
assign LED_COM=1;

always@(posedge Clock)
if (L)
Q=D;
else
Q[3:0]={Q[0],Q[3:1]};
endmodule

© A.B.M. Harun-ur Rashid 5 20/12/2006