KONERU LAKSHMAIAH EDUCATION FOUNDATION

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

COURSE HANDOUT FOR II/IV Year B. Tech Program

A.Y.2017-18 Semester II

LAB MANUAL
COURSE NAME : COMPUTER ORGANIZTION AND ARCHITECTURE
COURSE CODE : 15 EM 2001

L-T-P STRUCTURE : 3-0-2

COURSE CREDITS :4

COURSE CORDINATOR : Dr. SRINIVAS PRASAD

COURSE INSTRUCTORS:

Dr.B.VIJAYA BABU Mr.MD.AR.QUADRI

Dr.K.V.V.SATYANARAYANA Mrs.M.KAVITHA
Dr.G.PRADEEPINI Mr.J.KUMAR
Mr.B.TIRAPATHI REDDY Mr.G.SUBBA RAO
Dr.G.KRISHNA MOHAN Mrs.M.SAI PRASANTHI
Dr.SRINIVAS PRASAD Mr.P.YELLAMMA
Dr.M.JAYAKAMESWA RAO Ms.VAISHALI RAVINDRA THAKARE
Dr.MD.ASDAQUE HUSSIAN Mr.BHAVANI SANKAR PANDA
DR. MOHAMMED ISMAIL Mr.OMKAR PATTNAIK
Mr.V.HARI KIRAN Mr.G.SRAVAN KUMAR
Mr.K.KARTHIK Mr.RAHUL SHAHANE
Mr.M.TANOOJ KUMAR Mr.U.VIGNESH
Mr.P.V.V.S.SRINIVAS Mr.K.CHIRANJEEVI

Signature of Course Coordinator Signature of HOD, CSE

List of Experiments

1. Introduction To Lab , Design of Basic Logic Gates, Combinational & Sequential Circuits

Using Logisim (2 Sessions 4 Hrs)

2. Design of ALU Using Logisim

3. Design of 1 Bit Memory Operation with Working Model of ROM & RAM

4. Implementation of 8085 Arithmetic Instructions Using Gnusim8085

5. Implementation of 8085 Data Transfer Instructions Using Gnusim8085

6. Implementation of 8085 Rotate and Jump Instructions Using Gnusim 8085

7. Implementation of 8085 Logical instructions for sorting and masking data Using Gnusim

8085

8. Design of ALU Using Virtual Lab

9. Design of Direct Mapped Cache using Virtual Lab

10. Design of hardware Interaction programs using C

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

KONERU LAKSHMAIAH EDUCATION FOUNDATION

Course: COMPUTER ORGANIZTION AND ARCHITECTURE Code: 15 EM 2001

LAB MANUAL
Objective:
The Objective is to expose the students to the various key aspects of Computer Organization &
Architecture by enabling them to perform on simulator like LOGISIM Tool, GNUSim 8085 &
Virtual Labs.

1. Introduction To Lab , Design of Basic Logic Gates,

Combinational & Sequential Circuits Using Logisim

Study of Logic Gates

Aim/objective:
1. To Study and verify the logic gates with the help of its Logi Sim simulation tool and
truth table.
2. To design and construct Adder / Subtractor (combinational) circuits by using gates
and to verify their operation
3. To design and construct the 4 to 1 MUX and 1 to 4 DEMUX using gates and verify
the truth table .
4. To study the sequential circuits like SR , JK and D flip flops using basic gates

Components Required
S. No Description Quantity
1 OR gate As needed
2 AND gate As needed
3 NOR gate As needed
4 NAND gate As needed
5 XOR gate As needed
6 NOT gate As needed
Procedure:
1. Connect the circuit as per the circuit diagram in the canvas of logisim
2. Select logical inputs as per the respective truth table.
3. Observe the logical output and verify with their truth table.

Theory:
OR Gate:

The OR Gate performs logical addition, commonly Known as OR Function. The OR

gate has two or more inputs and only one output. The operation of OR gate is such that a
HIGH (1) on the output is produced when any one of the inputs is HIGH (1). The output is LOW
(0) only when all the inputs are LOW (0).

AND Gate:
The AND Gate performs logical multiplication, commonly known as AND function. The AND
gate has two or more inputs and a single output. The output of an AND gate is HIGH only when
all the inputs are HIGH. Even if any one of the inputs is LOW, the output will be LOW(0).

NOT Gate:

The NOT performs the basic logical function called inversion or complementation.
The purpose of this logic gate is to convert one logic to the opposite logic level. It has one
input and one output. When HIGH input is applied to an inverter, a LOW output appears at
its output and vice versa.

NAND Gate:

NAND gate is a contraction of the NOT-AND gates. It has two or more inputs and
only one output. When all the inputs are HIGH, the output is LOW. If any one or both the
inputs are LOW, then the output is HIGH. The NAND called as Universal Gate

NOR Gate:

NOR gate is a contraction of the NOT-OR gates. It has two or more inputs and only
one output. When all the inputs are LOW, the output is HIGH. If any one or both the inputs
are HIGH, then the output is LOW. The NOR gate called as Universal Gate

EX-OR Gate:

An Exclusive-OR gate is a gate with two or more inputs and one output. The output
of a gate is HIGH when odd numbers of HIGH inputs are applied. If Even number of HIGH
inputs or all the inputs are LOW the output will be LOW.
ADDER / SUBTRACTOR
Theory:
Half-Adder:
The simplest combinational circuit, which performs the arithmetic addition of two
binary digits, is called a Half- adder. The half-adder has two inputs and two outputs. The
two inputs are two 1-bit numbers A and B, and the two outputs are Sum (S) of A and B
and the Carry bit denoted by C. From the truth table we can understand that the Sum
output is 1 when either of the inputs (A or B) is 1, or the carry outputs is 1 when both the
inputs(AandB)are1.

Full –Adder:

A half-adder has only two inputs and there is no provision to add a carry coming from
the lower order bits when multibit addition is performed. For this purpose, a full-adder is
designed. A Full-adder is a combinational circuit that performs the arithmetic sum of three
input bits and produces a Sum output and a Carry. It consists of three inputs and two
outputs. The two input variables denoted by X (Augend bit) and Y (Addend bit) represent
the two significant bits to be added. The third input, Z , represents the carry from the previous
lower significant position. The outputs are designated by the symbols S (for sum)
and C (for Carry).
Half-Subtractor:
The half subtractor is a combinational circuit which is used to perform subtraction of
two bits. It has two inputs, X (Minuend) and Y (Subtrahend) and two outputs D (difference)
and B (Borrow). From the truth table, it is clear that the difference output is 0 if X=Y and 1
if the X Y; the borrow output B is 1 whenever X<Y. If X is less than Y, then subtraction
is done by borrowing from the next higher order bit.

Full-Subtractor:

A full subtractor is a combinational circuit that performs subtraction involving three

bits, namely minuend bit, subtrahend bit and the borrow from the previous stage. It has
three inputs, X (minuend), Y (Subtrahend) and Z (borrow from the previous stage) and two
outputs D (difference) and B (borrow).

Multiplexer & De multiplexer

Circuit Diagram (4-to-1 Channel Multiplexer)

The Demultiplexer

The data distributor, known more commonly as a Demultiplexer or “Demux” for short, is the
exact opposite of the Multiplexer.

The demultiplexer takes one single input data line and then switches it to any one of a number of
individual output lines one at a time. The demultiplexer converts a serial data signal at the input
to a parallel data at its output lines as shown below.
1-to-4 Channel De-multiplexer

The Boolean expression for this 1-to-4 Demultiplexer above with outputs A to D and data select
lines a, b is given as above.

The function of the Demultiplexer is to switch one common data input line to any one of the 4
output data lines A to D in our example above. As with the multiplexer the individual solid state
switches are selected by the binary input address code on the output select pins “a” and “b” as shown.

Demultiplexer Output Line Selection

4 Channel Demultiplexer using Logic Gates

Flip Flops
Theory:
Flip flop:
The memory cell has only two states. It can be either 0 or 1. Such two state
sequential circuits are called flip-flops, because they flip from one state to another and then
flop back. A flip-flop is also known as bistable multivibrator, latch or toggle.

Types of flip-flop:
There four different types of flip-flop. They are S-R, J-K, D and T flip flop.
SET-RESET (S-R) FLIP-FLOP:
The S-R flip-flop has two inputs, namely SET and RESET and two outputs Q and
Q’. The two outputs are complement to each other. The S-R flip-flop can be easily
implemented using NOR gates or NAND gates.

NOR-based S-R Flip-flop:

The S-R flip-flop can be constructed using two NOR gates connected back to back.
The cross-coupled connections from the output of one gate to the input of the other gate
constitute a feedback path. The output of the NOR gate is 0 if any input is 1 and output is 1
only when all inputs are 0.
DESIGN QUESTIONS/TEST CASES

1) Design NOR gate using NAND gate?

2) Design NOT gate using NOR gate?

3) Show that a three input AND gate and four input AND gate can be made out of two

input AND gates?

4) Show that a four input OR gate can be made out of two input OR gates.

5) Design AND gate using NAND gate.

6) Design OR gate using NAND and NOR gates separately.

7) Implement 1:8 Demultiplexer.

8) Implement 8:1 Multiplexer.

9) Verify the D , S-R and J-K flip flop truth tables using logisim inbuilt blocks.

10) Verify two bit adder operation using logisim inbuilt blocks.

RESULTS: 1.All logic gates are studied and verified through its truth tables
2. Adder and Subtractor are designed and verified with their truth tables.
3. Mux & Demux circuits are implemented on Logisim
4.Flip-flops are studied and designed and verified with their truth tables using
Logisim
2. Design of ALU Using Logisim

AIM/OBJECTIVES
1.Understanding behavior of 1 bit arithmetic logic unit from working module and the module
designed by the student as part of the experiment

2. Designing an arithmetic logic unit for given parameter

COMPONENTS REQUIRED

One bit adder, 3 bit mux with 6 select bits, Logic gates AND, OR, NOR, XOR, 3 Input Select
Lines

THEROY

ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,
subtraction, division, multiplication and logical operations like AND, OR, NOR, XOR, NAND,
etc. A simple block diagram of a 4 bit ALU for operations AND, OR, XOR and ADD is shown
here

CIRCUIT
PROCEDURE

OPERATION:

Select lines form the control signals for various operations as shown in table

Sl.no Select inputs Operation

1 0 0 0 And
2 0 0 1 OR
3 0 1 0 NOR
4 0 1 1 EXOR
5 1 0 0 ADD/SUB
6 1 0 1 LESS

TEST CASES/DESIGN QUESTIONS

1. Design the above circuit for Inverse operation at select line 100

2. Design above ALU circuit for NAND & NOR Universal gates

3. Design the above ALU Circuit operations with only NAND GATES

4. Implement the above ALU circuit adding NOT gate

5. Implement the above ALU circuit adding Increment and decrement operations

6. Modify the above circuit for only arithmetic operations with INC & DEC operations

7. Implement ONLY the logical unit of ALU For 3 BIT inputs

8. Design with only two select inputs any 3 basic gate operations with a two bit adder

9. Design a 4 bit ALU with 4 select lines to operate like a 74181 IC

10.Design for 2 bit adder with the above circuit

3. Design of 1 Bit Memory Operation with Working Model
of ROM & RAM
AIM/OBJECTIVES:

1. To design memory unit and understand how it operates during read and write operation using
Logisim

2. Understanding behavior of memory from working module and the module designed by the
student as part of the experiment

3. Designing a working model of RAM/ROM memory

COMPONENTS REQUIRED

SR Flip Flop, 3 Input NAND gates, NOT Gates, Counter random generator, RAM, ROM, Clock,
Controller buffer, TTY Display & Bit Extender

THEROY

The binary cell has 3 inputs and one output. The select input enables the cell for reading or
writing. Read /Write input 1 provides read operation by forming a path from the flip-flop to the
output terminal and 0 provides write operation by forming a path from the input terminal to the
flip flop.

CIRCUIT DIAGRAM OF MEMORY UNIT

PROCEDURE

1. Draw the circuit on the canvas using Logisim by selecting 3 inputs and one output
2. The select input enables the circuit for reading or writing and the read/write input
determines the operation of reading data from flip flop to the output terminal if selected
as 1 and write operation for 0 selection.

For examining the write behavior:

1. Initialize for Loading the data into the memory select=1 and R/W=0
2. Give input as= 1 For examining the read behavior: .Initialize select=1 & R/W'=1
Check output: output =1, it will give the value which was previously written

ROM AND WORKING MODEL OPERATION

RAM AND WORKING MODEL OPERATION.

TEST CASES/ASSIGNMENT QUESTIONS

1. Do read operations by varying select and input lines by properly setting the R/W', memory
enable then give input and check the output.

2. Do write operation by properly setting the R/W', memory enable then give input and check the
output.

3.Do read operation without setting the memory enable but properly setting the R/W' then give
input and check the output.

4.Use Display units for checking output. Try to use minimum number of components to build 1
bit RAM

5.Design a binary RAM cell using a S-R flipflop, AND gates, NOT gates having select,
read/write, input, output and test it by giving proper input.

6. Using 2:4 ROM/Decoder Implement the following Boolean function F1(A1,A0)=∑m(1,2)

7. Using 2:4 RAM/Decoder Implement the following Boolean function F2(A1,A0)=∑n(1,2,3)

8. Design a 64 bit ROM USING 4:16 Decoder for the following Truth Table

INPUTS OUTPUTS
X1 X2 X3 X4 Z1 Z2 Z3 Z4
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
4. Implementation of 8085 Arithmetic Instructions
Using Gnusim8085

AIM/OBJECTIVES:

1. Design and implement an 8085 assembly language program in GNUsim8085 to implement

a) Addition of two 8 bit numbers with and without carry
b) Subtraction of two 8 bit numbers with and without carry
c) Multiplication of two 8 bit numbers with and without carry

SOFTWARE REQUIREMENTS: GNU Sim 8085

THEROY:

Add two 8-bit numbers without considering the carry.

Explanation:
 This program adds two operands stored in memory location 3000H and 3001H, without
considering the carry produced (if any).

 Let us assume that the operands stored at memory location 3000H is 04H and 3001H is
02H.

 Initially, H-L pair is loaded with the address of first memory location.

 The first operand is moved to accumulator from memory location 3000H and H-L pair is
incremented to point to next memory location.

 The second operand is moved to register B from memory location 3001H.

 The two operands are added and the result is stored in accumulator.

H-L pair is again incremented and the result is moved from accumulator to memory location
3002H.

PROGRAME
Mnemonics Operand Remarks
LXI H, 3000H Load H-L pair with address 3000H.
Lower-order of 3000H.
Higher-order of 3000H.
MOV A, M Move the 1st operand from memory to reg. A.
INX H Increment H-L pair.
MOV B, M Move the 2nd operand from memory to reg. B.
ADD B Add B with A.
INX H Increment H-L pair.
MOV M, A Move the result from reg. A to memory.
HLT Halt.

Output:
Before Execution:
3000H: 04H
3001H: 02H

After Execution:
3002H: 06H

Add two 8-bit numbers along with considering the carry

Explanation:

 This program adds two operands stored in memory location 3000H and 3001H, along
with considering the carry produced (if any).

 Let us assume that the operands stored at memory location 3000H is FAH and 3001H is
28H.

 Initially, H-L pair is loaded with the address of first memory location.

 The first operand is moved to accumulator from memory location 3000H and H-L pair is
incremented to point to next memory location.

 The second operand is moved to register B from memory location 3001H.

 Register C is initialized to 00H. It stores the carry (if any).

 The two operands stored in register A and B are added and the result is stored in
accumulator.

 Then, carry flag is checked for carry. If there is a carry, C register is incremented.

 H-L pair is incremented and the result is moved from accumulator to memory 3002H.

H-L pair is again incremented and carry (either 0 or 1) is moved from register C to memory
location 3003H.

PROGRAM

Mnemonics Operand Remarks

LXI H, 3000H Load H-L pair with address 3000H.
Lower-order of 3000H.
Higher-order of 3000H.
MOV A, M Move the 1st operand from memory to reg. A.
INX H Increment H-L pair.
MOV B, M Move the 2nd operand from memory to reg. B.
MVI C, 00H Initialize reg. C with 00H.
Immediate value 00H.
ADD B Add B with A.
JNC 200D Jump to address 200DH if there is no carry.
Lower-order of 200DH.
Higher-order of 200DH.
INR C Increment reg. C.
INX H Increment H-L pair.
MOV M, A Move the result from reg. A to memory.
INX H Increment H-L pair.
MOV M, C Move carry from reg. C to memory.
HLT Halt.

Output:
Before Execution:
3000H: FAH 3001H: 28H

After Execution:
3002H: 22H 3003H: 01H

Subtract two 8-bit numbers along with considering the borrow

Mnemonics Operand Remarks
LXI H, 3000H Load H-L pair with address 3000H.
Lower-order of 3000H.
Higher-order of 3000H.
MOV A, M Move the 1st operand from memory to reg. A.
INX H Increment H-L pair.
MOV B, M Move the 2nd operand from memory to reg. B.
MVI C, 00H Initialize reg. C with 00H.
Immediate value 00H.
SUB B Subtract B from A.
JNC 200D Jump to address 200DH if there is no borrow.
Lower-order of 200DH.
Higher-order of 200DH.
INR C Increment reg. C.
INX H Increment H-L pair.
MOV M, A Move the result from reg. A to memory.
INX H Increment H-L pair.
MOV M, C Move borrow from reg. C to memory.
HLT Halt.

Explanation:
 This program subtracts two operands stored in memory location 3000H and 3001H,
along with considering the borrow taken (if any).

 Let us assume that the operands stored at memory location 3000H is 05H and 3001H is
02H.

 Initially, H-L pair is loaded with the address of first memory location.

 The first operand is moved to accumulator from memory location 3000H and H-L pair
is incremented to point to next memory location.

 The second operand is moved to register B from memory location 3001H.

 Register C is initialized to 00H. It stores the borrow (if any).

 The two operands stored in register A and B are subtracted and the result is stored in
accumulator.

 Then, carry flag is checked for borrow. If there is a borrow, C register is incremented.

 H-L pair is again incremented and borrow (either 0 or 1) is moved from register C to
memory location 3003H.

Output:
Before Execution:
3000H: 05H
3001H: 02H
After Execution:
3002H: 03H
3003H: 00H

Multiply two 8-bit numbers.

Mnemonics Operand Remarks

LXI H, 3000H Load H-L pair with address 3000H.
Lower-order of 3000H.
Higher-order of 3000H.
MOV B, M Move the 1st operand from memory to reg. B.
INX H Increment H-L pair.
MOV C, M Move the 2nd operand from memory to reg. C.
MVI A, 00H Initialize accumulator with 00H.
Immediate value 00H.
ADD B Add B with A.
DCR C Decrement reg. C (counter).
JNZ 2008H Jump back to address 2008H if C ≠ 0.
Lower-order of 2008H.
Higher-order of 2008H.
INX H Increment H-L pair.
MOV M, A Move the result from accumulator to memory.
HLT Halt.

Explanation:

 This program multiplies two operands stored in memory location 3000H and 3001H,
using successive addition method.

 In successive addition method, the second operand is considered as counter, and the
first number is added with itself until counter decrements to zero.
 Let us assume that the operands stored at memory location 3000H is 02H and 3001H is
05H.
 Then, by using successive addition method, we get 02H + 02H + 02H + 02H + 02H =
0AH.
 Initially, H-L pair is loaded with the address of first memory location.
 The first operand is moved to register B from memory location 3000H and H-L pair is
incremented to point to next memory location.
 The second operand is moved to register C from memory location 3001H to act as
counter.
 Accumulator is initialized to 00H.
 Register B is added with accumulator and the result is stored in accumulator.
 Register C (counter) is decremented by 1.
 Then, counter is checked for zero. If it hasn’t become zero yet, then register B is again
added with accumulator, and counter is again checked for zero.
 If counter becomes zero, then H-L pair is incremented and the result is moved from
accumulator to memory location 3002H.

Output:
Before Execution:

3000H: 02H

3001H: 05H

After Execution:

3002H: 0AH

TEST CASES /DESIGN QUESTIONS

1. Add two 8-bit numbers and show the result in decimal number system.
2. Write Test cases for 16 bit addition of two numbers in the above programe
3. Subtraction of two 8 bit numbers with carry
4. Implement subtraction of two 16 bit numbers with carry and without carry
5. Implement multiplication of two 8 bit numbers with carry
6. Implement 1's Complement for an 8 bit number
7. Implement 2's Complement for an 8 bit number

RESULTS

Implementation of Arithmetic instructions is performed for addition, subtraction and

multiplication using GNUsim8085
5. Implementation of 8085 Data Transfer Instructions
Using Gnusim8085

AIM/OBJECTIVES:

1. Design and implement an 8085 assembly language program in GNUsim8085 to implement

a) Data Transfer block of N-bytes from source to destination.

b) Transfer block of N-bytes in reverse order from source to destination

Transfer block of N-bytes from source to destination

Explanation:

 This program transfers block of N-bytes from source to destination. The source bytes
startsfrom memory location 3000H and needs to be transferred to memory locations
3500H onwards.
 In order to transfer these bytes, first the counter must be initialized to the number of
bytes to transfer.
 Then, H-L pair is initialized to point to the source memory location and D-E pair is
initialized to point to destination memory location.
 The first byte is moved from source to accumulator and then from there to destination.
 The H-L pair and D-E pair are incremented to point to the next respective memory
locations.
 The counter is decremented and checked whether it has become zero.
 If it hasn’t become zero, it means that there are bytes remaining to be transferred. In
this case, the control jumps back to move the next byte from source to destination.

This process continues until counter becomes zero, i.e. all the bytes have been transferred.

Mnemonics Operand Remarks

MVI C, 05H Initialize reg. C to 05H, i.e. number of bytes.
Immediate value 05H
LXI H, 3000H Initialize H-L pair to source memory location.
Lower-order of 3000H.
Higher-order of 3000H.
Initialize D-E pair to destination memory
LXI D, 3500H
location.
Lower-order of 3500H.
Higher-order of 3500H.
MOV A, M Move the byte from source to accumulator.
STAX D Store the byte from accumulator to destination.
INX H Increment the source pointer H-L pair.
INX D Increment the destination pointer D-E pair.
DCR C Decrement counter C.
JNZ 2008H Jump to address 2008H if counter is not zero.
Lower-order of 2008H.
Higher-order of 2008H.
HLT Halt.

Output:

Before Execution: After Execution:

3000H: 05H 3500H: 05H
3001H: 02H 3501H: 02H
3002H: 04H 3502H: 04H
3003H: 03H 3503H: 03H
3004H: 02H 3504H: 02H
Transfer block of N-bytes in reverse order from source to destination

Explanation:

 This program transfers block of N-bytes in reverse order from source to destination.
The source bytes start from memory location 3000H and needs to be transferred to
memory locations 3504H in reverse order.
 In order to transfer these bytes, first the counter must be initialized to the number of
bytes to transfer.
 Then, H-L pair is initialized to point to the source memory location and D-E pair is
initialized to point to destination memory location.
 The first byte is moved from source to accumulator and then from there to destination.
 The H-L pair is incremented and D-E pair is decremented to point to the next
respective memory locations.
 The counter is decremented and checked whether it has become zero.
 If it hasn’t become zero, it means that there are bytes remaining to be transferred. In
this case, the control jumps back to move the next byte from source to destination.
 This process continues until counter becomes zero, i.e. all the bytes have been
transferred.

Mnemonics Operand Remarks
MVI C, 05H Initialize reg. C to 05H, i.e. number of bytes.
Immediate value 05H.
LXI H, 3000H Initialize H-L pair to source memory location.
Lower-order of 3000H.
Higher-order of 3000H.
Initialize D-E pair to destination memory
LXI D, 3504H
location.
Lower-order of 3504H.
Higher-order of 3504H.
MOV A, M Move the byte from source to accumulator.
STAX D Store the byte from accumulator to destination.
INX H Increment the source pointer H-L pair.
DCX D Decrement the destination pointer D-E pair.
DCR C Decrement counter C.
JNZ 2008H Jump to address 2008H if counter is not zero.
Lower-order of 2008H.
Higher-order of 2008H.
HLT Halt.

Output:
Before Execution: After Execution:
3000H: 05H 3500H: 02H
3001H: 02H 3501H: 03H
3002H: 04H 3502H: 04H
3003H: 03H 3503H: 02H
3004H: 02H 3504H: 05H

DESIGN QUESTIONS/TEST CASES

1.Write test cases for transferring 2 bytes of Data in reverse order
2. Implement above code for 10 bytes of Block data transfer
3. Implement ALP To add n consecutive numbers

RESULTS
Implementation of data transfer instructions is performed for block transfer of data using
GNUsim8085

6. Implementation of 8085 Rotate and Jump

Instructions Using Gnusim 8085

AIM/OBJECTIVES:

1. Design and implement an 8085 assembly language program in GNUsim8085 to

implement Shift and Rotate instructions
2. Design and implement an 8085 assembly language program using Jump instructions for
GNUsim8085 to find smallest or largest number in an array

Shift left 8-bit number by 1 bit.

Explanation:

 This program performs the left shift operation on an 8-bit number by one bit stored in
memory location 3000H.
 Let us assume that the operand stored at memory location 3000H is 05H.
 The operand is moved to accumulator from memory location 3000H.
 Then, shift left operation is done by using RAL instruction.
 The result is stored at memory location 3001H.

Mnemonics Operand Remarks

LDA 3000H Load H-L pair with data from 3000H.
Lower-order of 3000H.
Higher-order of 3000H.
RAL Shift left accumulator.
STA 3001H Store the result at memory location 3001H.
Lower-order of 3001H.
Higher-order of 3001H.
HLT Halt.

Output:
Before Execution:
3000H: 05H
After Execution:
3001H: 0AH

Program to Shift Right 8-bit Number by 2 Bit

Mnemonics Opcode Remarks

LDA 3A Load A with data from 3000 H
00
30
RAR 1F Shift Right Accumulator
RAR 1F Shift Right Accumulator
STA 32 Store the result at location 3001 H
01
30
HLT 76 Halt

Before Execution:

3000: 05 H

After Execution:

3001: C1 H

Smallest from an array.

Explanation:

 This program finds the smallest number in an array.

 Initially, the counter is initialized with the size of an array.
 Then, two numbers are moved to registers A and B, and compared.
 After comparison, the smallest of two must be in accumulator. If it is already in
accumulator, then its fine, otherwise it is moved to accumulator.
 Counter is decremented and checked whether it has reached zero. If it has, the loop
terminates otherwise, the next number is moved to register and compared.
 Let us assume that the memory location 3000H stores the counter. The next memory
locations store the array.
 Initially, H-L pair is loaded with the address of the counter and is moved to register C.
 Then, H-L pair is incremented to point to the first number in the array.
 The first number is moved from memory to accumulator and counter is decremented by
one.
 H-L pair is again incremented and second number is moved to register B.
 The two numbers are compared.
 After comparison, if A > B, then CF = 0, and if A < B, then CF = 1.
 Carry flag is checked for carry. If there is no carry, it means B is smaller than A and it is
moved to accumulator.
 Counter is decremented and checked whether it has become zero.

 If it hasn’t become zero, it means there are numbers left in the array. In this case, the
control jumps back to increment the H-L pair and moves the next number to register B.
 This process continues until counter becomes zero, i.e. all the numbers in the array are
compared.
 At last, H-L pair is incremented and the smallest number is moved from accumulator to
memory.

Mnemonics Operand Remarks

LXI H, 3000H Load H-L pair with address 3000H.
Lower-order of 3000H.
Higher-order of 3000H.
MOV C, M Move counter from memory to reg. C.
INX H Increment H-L pair.
MOV A, M Move the 1st number from memory to reg. A.
DCR C Decrement counter.
INX H Increment H-L pair.
MOV B, M Move the next number from memory to reg. B.
CMP B Compare B with A.
JC 200EH Jump to address 200EH if there is no carry.
Lower-order of 200EH.
Higher-order of 200EH.
MOV A, B Move smallest from reg. B to reg. A.
DCR C Decrement counter.
JNZ 2007H Jump to address 2007H if counter is not zero.
Lower-order of 2007H.
Higher-order of 2007H.
INX H Increment H-L pair.
MOV M, A Move the result from reg. A to memory.
HLT Halt.

Output:
Before Execution:
3000H: 05H (Counter)
3001H: 15H
3002H: 01H
3003H: 65H
3004H: E2H
3005H: 83H

After Execution:
3006H: 01H
Largest from an array.

Explanation:

 This program finds the largest number in an array.

 Initially, the counter is initialized with the size of an array.
 Then, two numbers are moved to registers A and B, and compared.
 After comparison, the largest of two must be in accumulator. If it is already in
accumulator, then its fine, otherwise it is moved to accumulator.
 Counter is decremented and checked whether it has reached zero. If it has, the loop
terminates otherwise, the next number is moved to register and compared.
 Let us assume that the memory location 3000H stores the counter. The next memory
locations store the array.
 Initially, H-L pair is loaded with the address of the counter and is moved to register C.
 Then, H-L pair is incremented to point to the first number in the array.
 The first number is moved from memory to accumulator and counter is decremented by
one.
 H-L pair is again incremented and second number is moved to register B.
 The two numbers are compared.
 After comparison, if A > B, then CF = 0, and if A < B, then CF = 1.
 Carry flag is checked for carry. If there is a carry, it means B is greater than A and it is
moved to accumulator.
 Counter is decremented and checked whether it has become zero.
 If it hasn’t become zero, it means there are numbers left in the array. In this case, the
control jumps back to increment the H-L pair and moves the next number to register B.
 This process continues until counter becomes zero, i.e. all the numbers in the array are
compared.
 At last, H-L pair is incremented and the largest number is moved from accumulator to
memory
Program
Mnemonics Operand Remarks
LXI H, 3000H Load H-L pair with address 3000H.
Lower-order of 3000H.
Higher-order of 3000H.
MOV C, M Move counter from memory to reg. C.
INX H Increment H-L pair.
MOV A, M Move the 1st number from memory to reg. A.
DCR C Decrement counter.
INX H Increment H-L pair.
MOV B, M Move the next number from memory to reg. B.
CMP B Compare B with A.
JNC 200EH Jump to address 200EH if there is no carry.
Lower-order of 200EH.
Higher-order of 200EH.
MOV A, B Move largest from reg. B to reg. A.
DCR C Decrement counter.
JNZ 2007H Jump to address 2007H if counter is not zero.
Lower-order of 2007H.
Higher-order of 2007H.
INX H Increment H-L pair.
MOV M, A Move the result from reg. A to memory.
HLT Halt.
Output:
Before Execution:
3000H: 05H (Counter)
3001H: 15H
3002H: 01H
3003H: 65H
3004H: E2H
3005H: 83H

After Execution:
3006H: E2H
DESIGN QUESTIONS/TEST CASES
1. Implement program to Shift Left 8-bit Number by 2 Bits
2. Implement program to Shift Right 8-bit Number by 4 Bits
3. Implement program to find Smallest of two 8-bit numbers.
4. Implement program to find Largest of two 8-bit numbers.

RESULTS
Implementation of shift & Control instructions is performed using GNUsim8085
7. Implementation of 8085 Logical instructions for
sorting and masking data Using Gnusim 8085

AIM/OBJECTIVES:

1. Design and implement 8085 logical instructions in GNUsim8085 for sorting and
masking of data.
2. Mask the lower nibble of an 8-bit number.
Explanation:
 This program masks the lower nibble of an 8-bit number stored in memory location
3000H.
 Let us assume that the operand stored at memory location 3000H is 45H.
 The operand is moved to accumulator from memory location 3000H.
 Then, AND operation of F0H is performed with accumulator. This results in the
masking of lower nibble.
 The result is stored at memory location 3001H.

Address Mnemonics Operand Opcode Remarks

2000 LDA 3000H 3A Load H-L pair with data from 3000H.
2001 00 Lower-order of 3000H.
2002 30 Higher-order of 3000H.
2003 ANI F0H E6 AND Immediate F0H with reg. A.
2004 F0 Immediate value F0H.
2005 STA 3001H 32 Store the result at memory location 3001H.
2006 01 Lower-order of 3001H.
2007 30 Higher-order of 3001H.
2008 HLT 76 Halt.
Output:
Before Execution:
3000H: 45H
After Execution:
3001H: 40H
Mask the higher nibble of an 8-bit number

Explanation:

 This program masks the higher nibble of an 8-bit number stored in memory location
3000H.
 Let us assume that the operand stored at memory location 3000H is 45H.
 The operand is moved to accumulator from memory location 3000H.
 Then, AND operation of 0FH is performed with accumulator. This results in the
masking of higher nibble.

 The result is stored at memory location 3001H.

Address Mnemonics Operand Opcode Remarks

2000 LDA 3000H 3A Load H-L pair with data from 3000H.
2001 00 Lower-order of 3000H.
2002 30 Higher-order of 3000H.
2003 ANI 0FH E6 AND Immediate 0FH with reg. A.
2004 0F Immediate value 0FH.
2005 STA 3001H 32 Store the result at memory location 3001H.
2006 01 Lower-order of 3001H.
2007 30 Higher-order of 3001H.
2008 HLT 76 Halt.
Output:

Before Execution:

3000H: 45H

After Execution:

3001H: 05H
Sort the array in ascending order

Explanation:
 This program sorts an array in ascending order.

 Let us assume that there are five numbers in the array and its starting address is 3000H.

 Initially, counter-1 and counter-2 are initialized with the size of the array.

 H-L pair is pointed to the starting address of the array.

 In the first iteration, first number is compared with the second number.

 If first number < second number, then do not interchange them. Otherwise, if first
number > second number, then swap them.

 In the next iteration, first number is compared with the third number.

 If first number < third number, then do not interchange them. Otherwise, if first number >
third number, then swap them.

 In the next iteration, first number is compared with the fourth number and the process
continues until counter-2 becomes zero.

 When counter-2 becomes zero, counter-1 is decremented and the process continues until
all the numbers are arranged in ascending order.

Address Mnemonics Operand Opcode Remarks

2000 MVI B, 05H 06 Initialize counter-1.
2001 05 Immediate value 05H.
2002 MVI C, 05H 0E Initialize counter-2.
2003 05 Immediate value 05H.
2004 LXI H, 3000H 21 Load H-L pair with address 3000H.
2005 00 Lower-order of 3000H.
2006 30 Higher-order of 3000H.
2007 MOV A, M 7E Move the number from memory to reg. A.
2008 INX H 23 Increment H-L pair.
2009 CMP M BD Compare the number with next number.
200A JC 2015H DA Don’t interchange if number < next number.
200B 15 Lower-order of 2015H.
200C 20 Higher-order of 2015H.
200D JZ 2015H CA Don’t interchange if number = next number.
200E 15 Lower-order of 2015H.
200F 20 Higher-order of 2015H.
Otherwise, swap the numbers. Move next
2010 MOV D, M 56
number from memory to D.
2011 MOV M, A 77 Move first number from A to memory.
2012 DCX H 2B Decrement H-L pair.
2013 MOV M, D 72 Move next number from D to memory.
2014 INX H 23 Increment H-L pair.
2015 DCR C 0D Decrement counter 2.
2016 JNZ 2007H C2 If counter-2 ≠ 0, repeat.
2017 07 Lower-order of 2007H.
2018 20 Higher-order of 2007H.
2019 DCR B 05 Decrement counter-1.
201A JNZ 2002 C2 If counter-1 ≠ 0, repeat.
201B 02 Lower-order of 2002H.
201C 20 Higher-order of 2002H.
201D HLT 76 Halt.

Output:
Before Execution: After Execution:
3000H: 05H 3000H: 01H
3001H: 15H 3001H: 05H
3002H: 01H 3002H: 15H
3003H: 65H 3003H: 32H
3004H: 32H 3004H: 65H

Sorting the array in descending order

Explanation:
 This program sorts an array in descending order.
 Let us assume that there are five numbers in the array and its starting address is 3000H.
 Initially, counter-1 and counter-2 are initialized with the size of the array.
 H-L pair is pointed to the starting address of the array.
 In the first iteration, first number is compared with the second number.
 If first number > second number, then do not interchange them. Otherwise, if first
number < second number, then swap them.
 In the next iteration, first number is compared with the third number.
 If first number > third number, then do not interchange them. Otherwise, if first number <
third number, then swap them.
 In the next iteration, first number is compared with the fourth number and the process
continues until counter-2 becomes zero.
 When counter-2 becomes zero, counter-1 is decremented and the process continues until
all the numbers are arranged in descending order.

Mnemonics Operand Remarks

MVI B, 05H Initialize counter-1.
Immediate value 05H.
MVI C, 05H Initialize counter-2.
Immediate value 05H.
LXI H, 3000H Load H-L pair with address 3000H.
Lower-order of 3000H.
Higher-order of 3000H.
MOV A, M Move the number from memory to reg. A.
INX H Increment H-L pair.
CMP M Compare the number with next number.
JNC 2015H Don’t interchange if number > next number.
Lower-order of 2015H.
Higher-order of 2015H.
JZ 2015H Don’t interchange if number = next number.
Lower-order of 2015H.
Higher-order of 2015H.
Otherwise, swap the numbers. Move next
MOV D, M
number from memory to D.
MOV M, A Move first number from A to memory.
DCX H Decrement H-L pair.
MOV M, D Move next number from D to memory.
INX H Increment H-L pair.
DCR C Decrement counter 2.
JNZ 2007H If counter-2 ≠ 0, repeat.
Lower-order of 2007H.
Higher-order of 2007H.
DCR B Decrement counter-1.
JNZ 2002 If counter-1 ≠ 0, repeat.
Lower-order of 2002H.
Higher-order of 2002H.
HLT Halt.

Output:

Before Execution: After Execution:

3000H: 05H 3000H: 65H

3001H: 15H 3001H: 32H

3002H: 01H 3002H: 15H

3003H: 65H 3003H: 05H

3004H: 32H 3004H: 01H

DESIGN QUESTIONS/TEST CASES

1. Implement ALP for Generation of Fibonacci series

2. Implement ALP to count number of 1’s in a given 8 bit number
8. Design of ALU Using Virtual labs

AIM/OBJECTIVES:

1. Design ALU using Virtual Lab

2. Write C Program for hardware interaction for Shut downing the system and display
CPU Load

COMPONENTS REQUIRED:

COA Virtual Lab from IITK

The 4-bit ALU block is combined using 4 1-bit ALU block

Design Issues:

The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S1 and
S0 the circuit operates as follows:
for Control signal S1 = 0 , S0 = 0, the output is A And B,
for Control signal S1 = 0 , S0 = 1, the output is A Or B,
for Control signal S1 = 1 , S0 = 0, the output is A Xor B,
for Control signal S1 = 1 , S0 = 1, the output is A Add B.

The truth table for 16-bit ALU with capabilities similar to 74181 is shown here:
Required functionality of ALU (inputs and outputs are active high)
Mode Select Fn for active HIGH operands
Inputs Logic Arithmetic (note 2)
S3 S2 S1 S0 (M = H) (M = L) (Cn=L)
L L L L A' A
L L L H A'+B' A+B
L L H L A'B A+B'
L L H H Logic 0 minus 1
L H L L (AB)' A plus AB'
L H L H B' (A + B) plus AB'
L H H L A⊕B A minus B minus 1
L H H H AB' AB minus 1
H L L L A'+B A plus AB
H L L H (A ⊕ B)' A plus B
H L H L B (A + B') plus AB
H L H H AB AB minus 1
H H L L Logic 1 A plus A (Note 1)
H H L H A+B' (A + B) plus A
H H H L A+B (A + B') plus A
H H H H A A minus 1

The L denotes the logic low and H denotes logic high.

Procedure

1. Start the simulator as directed.This simulator supports 5-valued logic.

2. To design the circuit we need 4 1-bit ALU, 11 Bit switch (to give input,which will toggle
its value with a double click), 5 Bit displays (for seeing output), wires.
3. The pin configuration of a component is shown whenever the mouse is hovered on any
canned component of the palette. Pin numbering starts from 1 and from the bottom left
corner (indicating with the circle) and increases anticlockwise.
4. For 1-bit ALU input A0 is in pin-9,B0 is in pin-10, C0 is in pin-11 (this is input carry),
for selection of operation, S0 is in pin-12, S1 is in pin-13, output F is in pin-8 and output
carry is pin-7
5. Click on the 1-bit ALU component (in the Other Component drawer in the pallet) and
then click on the position of the editor window where you want to add the component (no
drag and drop, simple click will serve the purpose), likewise add 3 more 1-bit ALU (from
the Other Component drawer in the pallet), 11 Bit switches and 5 Bit Displays (from
Display and Input drawer of the pallet,if it is not seen scroll down in the drawer), 3 digital
display and 1 bit Displays (from Display and Input drawer of the pallet,if it is not seen
scroll down in the drawer)
6. To connect any two components select the Connection menu of Palette, and then click on
the Source terminal and click on the target terminal. According to the circuit diagram
connect all the components. Connect the Bit switches with the inputs and Bit displays
component with the outputs. After the connection is over click the selection tool in the
pallete.
7. See the output, in the screenshot diagram we have given the value of S1 S0=11 which
will perform add operation and two number input as A0 A1 A2 A3=0010 and B0 B1 B2
B3=0100 so get output F0 F1 F2 F3=0110 as sum and 0 as carry which is indeed an add
operation.you can also use many other combination of different values and check the
result. The operations are implemented using the truth table for 4 bit ALU given in the
theory.
Circuit Diagram

Circuit diagram of 4 bit ALU:

Screenshot of Design of 4 bit ALU:

Guidelines for using the simulator

1. Start the simulator as directed. For more detail please refer to the manual for using the
simulator The simulator supports 5-valued logic
2. To add the logic components to the editor or canvas (where you build the circuit) select
any component and click on the position of the canvas where you want to add the
component
3. The pin configuration is shown when you select the component and press the 'show
pinconfig' button in the left toolbar or whenever the mouse is hovered on any canned
component of palette
4. To connect any two components select the connection tool of palette, and then click on
the source terminal and then click on the the target terminal
5. To move any component select the component using the selection tool and drag the
component to the desired position
6. To give a toggle input to the circuit, use 'Bit Switch' which will toggle its value with a
double click
7. Use 'Bit Display' component to see any single bit value. 'Digital Display' will show the
output in digital format undo/redo, delete, zoom in/zoom out, and other functionalities
have been given in the top toolbar for ease of circuit building
8. Use start/stop clock pulse to start or stop the clock input of the circuit. Clock period can
be set from the given 'set clock' button in the left toolbar
9. Use 'plot graph' button to see input-output wave forms
10. Users can save their circuits with .logic extension and reuse them
11. After building the circuit press the simulate button in the top toolbar to get the output
12. If the circuit contains a clock pulse input, then the 'start clock' button will start the
simulation of the whole circuit. Then there is no need to again press the 'simulate' button

TEST CASES:
Set inputs 0101 and 0011 and check output for all possible select input combinations.

Set any two 16-bit number and check output for all possible select input combinations.

Use Display units for checking output. Try to use minimum number of components to build. The
pin configuration of the canned components are shown when mouse hovered over a component.

Test Case 1 : Loading data in the arithmetic logic unit

load the two input numbers as:

A(A3 A2 A1 A0): A3=1, A2=1, A1=0, A0=0

B(B3 B2 B1 B0): B3=1, B2=0, B1=0, B0=1

carry in(C0)=0

Test Case 2 : Examining the AND behaviour:

load data in select input as:

S1=0, S0=0 `

check output:
F3=1, F2=0, F1=0, F0=0

cout=0 `

Test Case 3: Examining the OR behaviour:

load data in select input as:

S1=0, S0=1 `

check output:

F3=1, F2=1, F1=0, F0=1

cout=0 `

Test Case 4 : Examining the XOR behaviour:

load data in select input as:

S1=1, S0=0 `

check output:

F3=0, F2=1, F1=0, F0=1

cout=0 `

Test Case 5: Examining the ADD behaviour:

load data in select input as:

S1=1, S0=1 `

check output:

F3=0, F2=1, F1=0, F0=1

cout=1 `

RESULT: A 4 bit ALU is designed using Virtual Labs

9. Design of Direct Mapped Cache using Virtual Lab

AIM/ OBJECTIVES:

1. Understand behaviour of direct mapped cache from working module

2. To Design a direct mapped cache for given parameters

COMPONENTS REQUIRED: COA Virtual Lab from IITK

Theory
Direct Mapped Cache
A given memory block can be mapped into one and only cache line.

Block identification: let the main memory contains n blocks (which require log2(n)) and cache
contains m blocks, so n/m different blocks of memory can be mapped (at different times) to a
cache block. Each cache block has a tag saying which block of memory is currently present in it,
each cache block also contain a valid bit to ensure whether a memory block is in the cache block
currently.

 Number of bits in the tag: log2(n/m)

 Number of sets in the Cache: m
 Number of bits to identify the correct set: log2(m)
The memory address is divided into 3 parts- tag(most MSB), index, block offset(most LSB) in
order to do the cache mapping.

 Select set using index, block from set using tag.

 Select location from block using block offset.
 tag + index = block address

Diagram of a direct mapped cache (here main memory address is of 32 bits and it gives a data
chunk of 32 bits at a time):

If a miss occur CPU bring the block from the main memory to the cache, if there is no free block
in the corresponding set it replaces a block and put the new one. CPU uses different replacement
policies to decide which block is to replace. The disadvantage of the direct mapped cache is that
it is easy to build, but suffer the most from thrashing due to the 'conflict misses' giving more miss
penalty.

Design issues:
Below is a simple cache which holds 1024 words or 4KB, memory address is 32 bits. The tag
from the cache is compared against the most significant bits of the address to determine whether
the entry in the cache corresponds to the requested address as the cache has 2 10 or 1024 words
and a block size of one word, 10 bits are used to index the cache, leaving 32-10-2=20 bits to be
compared against the tag. If the tag and the most significant 20 bits of the address are equal and
the valid bit is on then the request hits in the cache otherwise miss occurs. No replacement policy
has been implemented in the circuit.

The comparator Circuit through which tag is compared with specified bits of address:
Procedure to perform the experiment:
Direct mapped cache on the existing component 'Direct Mapped Cache' component is available
in the 'other components' drawer in the simulator. This simulator supports 5-valued logic.

Below is a schematic diagram of the 'Direct Mapped Cache' component in the 'other components'
drawer in the simulator:

1. Click on the 'Direct Mapped Cache' component (in the 'other components' drawer in the
pallet) and then click on the position of the editor window where you want to add the
component (no drag and drop, simple click will serve the purpose), likewise add 15 Bit
switches and 3 Bit Displays (from Display and Input drawer of the pallet,if it is not seen
scroll down in the drawer)
2. 'Direct Mapped Cache' component in the 'other components' drawer in the simulator
supports both writing in the cache and the cache mapping. No replacement policy has
been implemented. Initially the cache is empty, user has to give inputs. the component
contains 4 sets, each set has 5 bits, the left most bit is the valid bit, next 2 bits are tags,
next bits are data bits, also it contains a one dimensional array of memory with 4 bit to
store the memory address, user has to give this address input also. The cache reads all the
data bits at a time so block offset is not required.

3. The pin configuration of the component can be seen whenever the mouse is hovered on
any canned component of the palette or press the 'show pinconfig' button. Pin numbering
starts from 1 and from the bottom left corner(indicating with the circle) and increases
anticlockwise.
For a 'Direct Mapped Cache' component pin configuration is:

 Pin-32= S (selects whether user wants to perform cache write or cache mapping)
 pin-31= R/W'A (selects whether user wants to input the address or cache mapping)
 pin-30=A3, pin-29=A2, pin-28=A1, pin-27=A0 (these 4 pins are used to give address
input). A3 is the most significant bit and A0 is the least significant bit. A3 and A2 will be
compared with the tag. A1 and A0 will select the corrsponding set.
 pin-26= R/W'D(selects whether user wants to input in the set of cache or cache mapping)
 pin-25= M1, pin-24=M0 (M1 is the most significant bit and M0 is the least significant
bit). thiese two bits are used for cache write purpose, it selects the particular set of which
user wants to give inputs to the valid bit, tag bits and data bits.
 pin-23= Den (this is an enable input which has to set for any write purpose in the cache).
 pin-21= valid bit
 pin-20= T1, pin-19=T0 (T1 is the most significant bit and T0 is the least significant bit).
These are tag bits.
 pin-18= D1, pin-17=D0 (D1 is the most significant bit and D0 is the least significant bit).
These are data bits.
 pin-14= Hit/Miss bit (if it gives 1 then hit otherwise miss)
 pin-15= F1, pin-16=F0 (F1 is the most significant bit and F0 is the least significant bit).
These are output data bits and will be given only when there is a hit.
 Essential pin configurations for writing in the cache: S=1, R/W'A=0, R/W'D=0, Den= 1
 Essential pin configurations for cache mapping: S=0, R/W'A=1, R/W'D=1, Den= 0

To connect any two components select the Connection menu of Palette, and then click on the
Source terminal and click on the target terminal. According to the circuit diagram connect all the
components. After the connection is over click the selection tool in the pallete.

See the output, Bit switches are used to give input so that you can toggle its value with a double
click and see the outputs with different inputs.

Screenshot of the experiment :

Guidelines to use the simulator for the experiment

1. Start the simulator as directed. For more detail please refer to the manual for using the
simulator The simulator supports 5-valued logic
2. To add the logic components to the editor or canvas (where you build the circuit) select
any component and click on the position of the canvas where you want to add the
component
3. The pin configuration is shown when you select the component and press the 'show
pinconfig' button in the left toolbar or whenever the mouse is hovered on any canned
component of palette
4. To connect any two components select the connection tool of palette, and then click on
the source terminal and then click on the the target terminal
5. To move any component select the component using the selection tool and drag the
component to the desired position
6. To give a toggle input to the circuit, use 'Bit Switch' which will toggle its value with a
double click
7. Use 'Bit Display' component to see any single bit value. 'Digital Display' will show the
output in digital format
8. undo/redo, delete, zoom in/zoom out, and other functionalities have been given in the top
toolbar for ease of circuit building
9. Use start/stop clock pulse to start or stop the clock input of the circuit. Clock period can
be set from the given 'set clock' button in the left toolbar
10. Use 'plot graph' button to see input-output wave forms
11. Users can save their circuits with .logic extension and reuse them
12. After building the circuit press the simulate button in the top toolbar to get the output
13. If the circuit contains a clock pulse input, then the 'start clock' button will start the
simulation of the whole circuit. Then there is no need to again press the 'simulate' button

Test Plan :
Give some valid input initially in the cache then give such address so that hit occurs then alter
the address content or the tag or valid bit to get a miss.

Use Display units for checking output. Try to use minimum number of components to build. The
pin configuration of the canned components is shown when mouse hovered over a component.

TEST CASES:
Test Case 1: Examining behaviour of given direct mapped cache
Number of tag bits: 2
Modulus value arising from given tag bits: 22=4
Number of bits in set component of address: 2
Number of bits in block component: 0
Test Case 2 : Loading data in the cache

Global initialisation: (S=1, R/W'A=0, R/W'D=0, Den=1)

In cache line 0, load as follows:
data= "11" (D1=1, D0=1)
tag= "10" (T0=0, T1=1)
valid bit= "1" (valid=1)
in cache line 1, load as follows:
valid bit= "0" (valid=1)
Test Case 3: Examining hit behaviour

Load data in address latch as:

set: "00" (A0=0, A1=0),
tag= "10" (A3=1, A2=0)
initiate cache mapping:
S=0, R/W'A=1, R/W'D=1, Den= 0
Check output:
F0=1, F1=1, hit/miss=1
Test Case 4: Examining miss behaviour due to mismatch of tag:
Load data in address latch as:
set: "00" (A0=0, A1=0),
tag= "11" (A3=1, A2=1)
initiate cache mapping:
S=0, R/W'A=1, R/W'D=1, Den= 0
check output:
F0=0, F1=0, hit/miss=0
Test Case 5: Examining miss behaviour due to valid bit not set:
Load data in address latch as:
set: "01" (A0=1, A1=0),
tag= "11" (A3=1, A2=1)
initiate cache mapping:
S=0, R/W'A=1, R/W'D=1, Den= 0
check output:
F0=0, F1=0, hit/miss=0
RESULTS: Behavior of associative cache from working module is studied and designed for
various parameters

10. Design of Hard Ware Interaction Programs

AIM/ OBJECTIVES:

1. To Design & Implement a C program for shut downing the system

2. To Design & Implement a C program for For Displaying the CPU load of the
system

COMPONENTS REQUIRED: C Compiler

a) For shut downing the system

Procedure :

1) Open a C file.
2) insert the command in system function
3) compile the code using gcc.
4) run the code.

C Code:

#include <stdio.h>
#include <stdlib.h>
int main()
{
// Running Linux OS command using system
system("sudo shutdown -P now");

return 0;
}

Note : Change the parameters after shutdown command listed below.

RESULT : System Shutdown.

TEST CASES:

1) Reboot after shutdown

2) Halt or power off after shutdown
3) Halt after shutdown (implies -h)
4) Power off after shutdown (implies -h)
5) Cancel a running shutdown
6) Only send warnings, don't shutdown
7) Reduce output to errors only
8) Increase output to include informational.

b) For Displaying the CPU load of the system.

PROCEDURE :

1) Open a C file.
2) Insert the command in system function.
3) Compile the code using gcc.
4) Run the code.

C Code:

Calculating load of CPU

#include <stdio.h>
#include <stdlib.h>

int main()
{
// Running Linux OS command using system
system("top -b -d1 -n1|grep -i "Cpu(s)"|head -c21|cut -d ' ' -f3|cut -d '%' -f1");

return 0;
}

Output : Displays the CPU load.

TEST CASES:

1. CPU hardware information.

2. To count the number of processing units use grep with wc.
3. To get the actual number of cores, check the core id for unique values.
Print the cpu hardware details in a user-friendly format.
Prints out the number of processing units available.
4. Information about the cpu, which includes the socket type, vendor name and various
flags.
5. Program to generate a well structured easy to read report about various hardware
components on the system.
6. Fetch CPUID information about Intel and AMD x86 processors.

RESULT: Hardware interaction is performed using C program for shut downing the system and
displaying the CPU Load