Logic Design LAB Manual

III SEMESTER

LOGIC DESIGN
LABORATORY
MANNUAL
10ESL38

K.L.E.s
K.L.E. Institute of Technology,
Hubli-31
DEPARTMENT OF ELECTRICAL AND ELECTRONICS

Prepared by:
Prof. Kumarswamy V
Prof. Chaitanya K J

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Logic Design LAB Manual

Lab Syllabus

NOTE: Use discrete components to test and verify the logic gates. Lab View can be used for
designing the gates along with the above.

1. Simplification, realization of Boolean expressions using logic gates/Universal gates.

2. Realization of Half/Full adder and Half/Full Subtractors using logic gates.
3. (i) Realization of parallel adder/Subtractors using 7483 chip.
(ii) BCD to Excess-3 code conversion and vice versa.
4. Realization of Binary to Gray code conversion and vice versa
5. MUX/DEMUX use of 74153, 74139 for arithmetic circuits and code converter.
6. Realization of One/Two bit comparator and study of 7485 magnitude comparator.
7. Use of a) Decoder chip to drive LED display and b) Priority encoder.
8. Truth table verification of Flip-Flops: (i) JK Master slave (ii) T type and (iii) D type.
9. Realization of 3 bit counters as a sequential circuit and MOD N counter design
(7476, 7490, 74192, 74193).
10. Shift left, Shift right, SIPO, SISO, PISO, PIPO operations using 74S95.
11. Wiring and testing Ring counter/Johnson counter.
12. Wiring and testing of Sequence generator.

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Logic Design LAB Manual

CONTENTS
Lab Experiments
1. Simplification, realization of Boolean expressions using logic gates/Universal gates.
1a. Basic logic gates 1-3
1b. Universal Gates 4-5
1c. Boolean Expression
2. Realization of Half/Full adder and Half/Full Subtractors using logic gates
2a. Half adder & Full adders 11-14
2b. Half subtractor & Full subtractor
3. (i) Realization of parallel adder/Subtractors using 7483 chip.
(ii) BCD to Excess-3 code conversion and vice versa 15-1
3a. Parallel adder/Subtractor 19-20
3b. BCD to Excess-3 & vice versa
4. Realization of Binary to Gray code conversion and vice versa
5. MUX/DEMUX use of 74153, 74139 for arithmetic circuits and code converter
6. Realization of One/Two bit comparator and study of 7485 magnitude comparator.
6a.One/Two bit comparator 30-3
6b. Magnitude comparator
7. Use of a) Decoder chip to drive LED display and b) Priority encoder 40-44
7a. BCD to 7-segment Decoder 45-4
7b. Priority encoder 47-49
8. Truth table verification of Flip-Flops: (i) JK Master slave (ii) T type and (iii) D type.
9. Realization of 3 bit counters as a sequential circuit and MOD N counter design
(7476, 7490, 74192, 74193).
10. Shift left, Shift right, SIPO, SISO, PISO, PIPO operations using 74S95.
11. Wiring and testing Ring counter/Johnson counter.
12. Wiring and testing of Sequence generator.

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Logic Design LAB Manual

Expt No: 1a BASIC LOGIC GATES

AIM: To study operation of logic gates

1. AND GATE
2. OR GATE
3. NOT GATE
4. EX-OR GATE
5. NAND GATE
6. NOR GATE

COMPONENTS REQUIRED: IC7404, 7408, 7432, 7486, 7400, 7402,

IC Trainer kit and patch chords

THEORY :

AND GATE:
An AND GATE is a logic circuit with two or more than two inputs and one output. The output of an
AND GATE is logic 1 only when all of its inputs are in logic 1 state. In all other cases, the output is
logic 0.

OR GATE:
An OR GATE is a logic circuit with two or more than two inputs and one output. The output of an OR
GATE is 0 only when all of its inputs are at logic0. For all other possible input combinations, the
output is logic 1.

NOT GATE:
A NOT-CIRCUIT is a one input one output logic gate whose output is always the complement of the
input. That is, logic0 at the input produces logic1 at the output and vice-versa.

EX-OR GATE:
Ex-OR gate means exclusive OR gate. This gate has a high output only when an odd number of inputs
is high ; or, in other words, the EX-OR gates produces a logic 1 whenever either one of the inputs is
1, but not when both are 1. The EX-OR operator is the sign + , as indicated in the pin details.

NAND GATE:
An AND GATE followed by a NOT circuit make it as an NAND GATE. NAND GATE is a logic
circuit having two or more than two inputs and one output. The output of an NAND GATE is logic 0
only when all of its inputs are in logic 1 state. In all other cases, the output is logic 1

NOR GATE
An OR GATE followed by an NOT circuit make it as an NOR GATE. NOR GATE is a logic circuit
having two or more than two inputs and one output. The output of an NOR GATE is logic 1 only
when all of its inputs are in logic 0 state. In all other cases, the output is logic 0.
PROCEDURE
1. Check all the components and patch-chords whether they are in good condition.
2. Insert the appropriate IC into the IC base.
3. Make connection as shown in pin details.
4. Give supply to the trainer kit.
5. Verify the truth table and observe the outputs
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Logic Design LAB Manual

1. AND Gates:
Logic Symbol Truth Table
IC 7408 Vcc

1 14 13
2 12
7 A Input Output
3
4 11 Y A B Y
0
B
4
5 10 0 0 0
8 9
0 1 0
6
Y=A.B
7
8
1 0 0
Gnd 1 1 1

2. OR Gates

IC 7432 Vcc
Logic Symbol Truth Table

1
2
14 13
12
Input Output
7 A A B Y
4 Y
3
3
11 B 0 0 0
4 2 0 1 1
5 10
9
Y=A+B 1 0 1
6 1 1 1
8
7

Gnd
3. Not Gates

IC 7404 Truth Table

Logic Symbol
1 14 13

7 Input Output
2 12
Y
3 4 11 A Y
0
4 4 10 0 1
5
9
1 0
Y=
6

7
8 A
Gnd

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Logic Design LAB Manual

NAND Gates: Logic Symbol Truth Table

IC 7400 Vcc

1 14 13 Input Output
2 12 A
7 Y A B Y
3 4 11 B 0 0 1
0
4
0
0 1 1
5 10
1 0 1
6
9
AB 1 1 0
8
7

Gnd

XOR Gates:

IC 7486 Vcc Truth Table

1 14 13
2 12
Input Output
7 A
3 4 11 Y A B Y
8 B 0 0 0
4
5 6 10 0 1 1

9
1 0 1
6
8 1 1 0
7

Gnd

NOR Gates

IC 7402
Vcc
Logic Symbol Truth Table

1 14 13 Input Output
A A B Y
7 Y
2 4 12 0 0 1
B
3
4
0 11
0 1 0
2 10 1 0 0
Y=
1 1 0
5
6 9 A +B
7 8

Gnd

Result : The basic gates are verified.

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Logic Design LAB Manual

Expt No: 1b TRUTH TABLE VERIFICATION OF LOGIC GATES USING NAND

AND NOR GATES (UNIVERSAL GATES)

AIM : To verify the logic gates using universal gates.
Components required :IC 7400,IC 7402,Patch chords and trainer kit
Theory: About NAND and NOR GATES :
The NAND and NOR gates is termed as Universal gates (or Universal Block ) , because almost any
logic function can be made by suitably interconnecting NAND gates or NOR GATES. For Ex :
different combinations of the NAND gate or NOR gate can be employed to produce any one of the
basic three functions of AND, OR and INVERT (NOT) gates.

PROCEDURE
1. Make connection as shown in logic diagram.
2. Give supply to the trainer kit.
3. Provide the input data to the circuit Via switches.
4. Verify the truth table sequence and observe the outputs.

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Truth Table Varification of Logic gates using NAND and NOR Gates

Function Using NAND Gates Using NOR Gates

NOT Gate
7404 IC A Y
A Y

A A

AND Gate
7408 IC A
A
Y Y
B

Y=A.B B
Y=A.B
OR Gate
7432 IC A A
Y Y
B
B
Y=A+B Y=A+B

A
X-OR Gate A
B
Y Y
7486 IC

B Y=A
B

Result: The basic gates are verified using universal gates.

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Logic Design LAB Manual

Expt No: 1c Simplification and Realization of Boolean Expression

Aim: To Simplify and realize the given Boolean expressions using Logic Gates/Universal Gates.
Components required: IC 7408,IC 7432, IC 7400,IC 7402, IC 7410,7404, Patch chords and trainer
kit

Theory :
Boolean Expression consists of variables, which can have one of the two possible values. Either one or
zero. There are two methods to minimize Boolean expression
1. Boolean Algebra
2. Karnaugh map

Boolean algebra: Boolean algebra provides a means by which logic circuitry may be expresses
symbolically, manipulated and reduced .Use of Boolean algebra in logic circuits lead to following
results:
* Minimizes the number of logic gates in a circuit
* Minimizes the cost of a circuit
* A circuit which uses only one type of basic logic gates such as NAND gate becomes possible.
* A circuit having parallel, redundant gates with minimum propagation delay can be designed.

Demorgan suggested two theorems that form an important part of Boolean algebra that is
1. Sum of Product
2. Product of sum

Procedure:
1. Verify all the components and the Patch Chords whether they are in good condition.
2. Fix the IC on the base board.
3. Connections are made as shown in the logic diagram.
4. Verify the truth Table for each expression.

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Logic Design LAB Manual

LOGIC EXPRESSIONS:
Truth Table
Using Basic Gates
1) Y1=(A+BC)(B+A C ) A B C Y1
0 0 0 0
Simplification: 0 0 1 0
0 1 0 0
C 0 1 1 1
Y1=(A+BC)(B+A ) 1 0 0 1
= AB+ A C +BC 1 0 1 0
1 1 0 1
1 1 1 1

A B C

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Logic Design LAB Manual

Using NAND Gates

Y1= AB+ A C +BC

= AC
A B C

10 Y1

Using Nor Gate :

Y1= ( A+BC)(B+ A C )
= (A+B)(A+C)(B+A)(A+ C )

= ( A +C )( A +B)( B+C )

= ( A +C ) ( A +B) B+C )
( (Using only NOR gates)
A B C

Y11

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2) Z= A B C +AB C + A B C+ABC

Using Basic Gates:

Z= A B (C+ C )+AB(C+ C )

= A B +AB

A B

Truth Table

A B C Y
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
Y 1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

Using Nand Gates

Z= B
A B

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Using only NOR Gates

Z= (A+ B )+( A +B)

A B

Result : The given Boolean expression is verified using basic and universal gates.

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VIVA QUESTIONS :

1. What is Number System? Classify

2. Define Base of a number or Radix of a number system.
3. What is logic gate? Classify
4. Why NAND and NOR are called as Universal gates.
5. What is the difference between Binary addition and Boolean addition
6. Define truth table.
7. What is the need for simplification of Boolean expression?
8. What are the methods followed to simplify a given Boolean expression.
9. Which is the best method to perform simplification.
10. Using K-map, to haw many variables maximum can be simplified.
11. Define cell.
12. What is the difference between Prime implicants and essential prime implicants?
13. Difference between Minterm and Maxterm.
14. What is SOP and POS
15. In K-Map what type of coding is used? Why other codes are not used.
16. What do you mean by ORing of AND terms and ANDing of OR terms
17. Realize the XNOR function using only XOR gates.
18. What do and indicate.
19. How do you convert SOP into POS and vice versa
20. Does NAND gate obey the commutative, associative and distributive laws? Justify.
21. Why NAND & NOR gates are called universal gates?
22. Realize the EX OR gates using minimum number of NAND gates.
23. Give the truth table for EX-NOR and realize using NAND gates?
24. What are the logic low and High levels of TTL ICs and CMOS ICs?
25. Compare TTL logic family with CMOS family?
26. Which logic family is fastest and which has low power dissipation?
27. What are the different methods to obtain minimal expression?
28. What is a Min term and Max term
29. State the difference between SOP and POS.

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Logic Design LAB Manual

Expt No: 2a Half Adder and Full Adder using Logic Gates

Aim: Realization of Half /Full Adder using Logic Gates

Components required: IC 7400,, IC 7486, IC 7408, 7404, Patch chords and trainer kit

Theory:
About Nand And Nor Gates: The NAND and NOR gates is termed a universal gates (or universal
block), because almost any logic function can be made by suitable inter connecting NAND gates or NOR
gates. For ex: different combinations of the NAND GATE or NOR gate can be employed to produce any
one of the basic three functions of AND, OR and INVERT (NOT) gates.

Ex-Or Gate: Ex-or gate means Exclusive OR gate. This gate has a high output only when an odd number
of inputs are high: or in other words, the Ex-or gate produces a Logic1. Whenever either one of the
inputs is one, but not when both are 1. The Ex-or operator is the Sign +, as indicated in the figure.

Half Adder and Full Adder: The simplest binary adder is called a half adder. Half adder has two input
bits and two output bits. One bit is the sun and the other is carry. S and C represent these respectively in
the logic symbol.
A half adder has no provision to add a carry from the lower order bits when binary numbers are
added. When two input bits and a carry are to be added, the number of input bits becomes three and the
input combination increases to eight. For this, a full adder is used. Like half adder, it also has a sum bit
and carry bit. New carry generated is represented by Cn and carry generated from the previous addition is
represented by Cn 1.

The expression for half adder is as follows,

Sum = A B
Carry = AB
The expression for full adder is as follows,
Sum = A B C
Carry = AB+C(A B)

Procedure:
1. Verify all the components and patch chords whether they are in good condition.
2. Make connections as shown in logic diagram.
3. Give supply to the trainer kit.
4. Provide the input data to the circuit via switches.
5. Verify the truth table sequence and observe the outputs.

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Half Adder:
a) Half Adder using Basic gates

A

B

C=AB

b) Half Adder using NAND Gates

S= A B

C=AB

Truth Table :

A B SUM CARRY
(S) (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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FULL ADDER:

a) Full Adder using Basic Gates

B
C

b) Full Adder using NAND Gates only

Truth Table:
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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K-Map Simplification

1) SUM
AB
00 01 11 10

0 1 1
1

2) CARRY
AB
00 01 11 10

0
1

Result: The half adder and full adder circuits are verified using basic and universal gates.

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Logic Design LAB Manual

Expt No: 2b Half Subtractor and Full Subtractor using Logic Gates

Aim: Realization of Half /Full Subtractor using Logic Gates

Components required: IC 7400,, IC 7486, IC 7408, 7404,IC 7432, Patch chords and trainer kit
Theory:
Half subtractor :
Half subtractor is a combinational circuit that subtracts 2 bits and produces their difference. It also has an
output to specify if a one has been borrowed. Half subtractor can be implemented by using basic gates or
by using only Nand gates.

Full subtractor :
Full subtractor circuit performs subtraction between 2 bits, taking into account that a one may have been
borrowed by a lower significant stage. The circuit has 3 inputs and 2 outputs. The truth table and the logic
expressions are given below in the observation.

The expression for half subtractor is as follows,

Difference = A B
Borrow = AB
The expression for full subtractor is as follows,
Difference = A B C
Borrow = A B+C(A B)

Procedure:

1 Verify all the components and patch chords whether they are in good condition.
2 Make connections as shown in logic diagram.
3. Give supply to the trainer kit.
4. Provide the input data to the circuit via switches.
5. Verify the truth table sequence and observe the outputs.

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b.Half Subtractor using NAND Gates

C= A
B

Truth Table

A B Diff(D) Borrow
(B)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Full Subtractor:

C. Full Subtractor using Basic Gates

A
B
C

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D.Full Subtractor using NAND Gates only

B0= A B+C(A

Truth Table:

A B C Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map Simplification

1) Diff
AB
00 01 11 10

0 1 1
1

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2) Borrow

AB
00 01 11 10

0
1

Result: The half and full subtractor are verified using basic and universal gates

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VIVA QUESTIONS :

1. What is a half adder?

2. What is a full adder?
3. What are the applications of adders?
4. What is a half subtractor?
5. What is a full subtractor?
6. What are the applications of subtractors?
7. Obtain the minimal expression for above circuits.
8. Realize a full adder using two half adders
9. Realize a full subtractors using two half subtractors
10. What is the internal structure of 7483 IC?
11. How do you realize a subtractor using full adder?
12. What is a ripple Adder? What are its disadvantages?
13. Define the function of half adder, Full adder, half Subtractor, and full Subtractor.
14. What is the difference between carry and overflow?
15. What is the function of Parallel adder and subtractor?
16. Give the pin configuration of IC 7483.
17. What is the need for complements?
18. Classify the types of complements.
19. How the twos complement operation is achieved using IC 7483.
20. What is the need for XOR gates in Parallel adder and subtractor?
21. What are the conditions required to perform Parallel addition, 1s complement parallel subtraction,
and 2s complement parallel subtraction.
22. What is the largest decimal number that can be added with a parallel adder consisting of four full
adders?
23. To perform addition of two 6-bit numbers, we need a parallel adder having ---------- full adder
circuits
24. Can addition of two BCD numbers be performed using IC 7483? If yes, what are the changes to be
made in the circuit?
25. While adding two BCD numbers, if the sum is not a BCD number, what is to be done?

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Expt No: 3a PARALLEL ADDER/SUBTRACTOR USING 7483 CHIP

Aim: To realize a parallel adder/subtractor using 7483 chip

Components required: , IC 7483, IC 7404, Patch chords and trainer kit

THEORY:
The 7483 is a TTL IC with four full adders in it. This means that it can add nibbles. To add bytes, we
need to use two 7483 ICs.

4-bit binary adder A3 A2 A 1 A0 and B3 B2 B1 B0 are inputs and Cout S3 S2 S1 S0 is the output CARRY IN
Pin is grounded.

4-bit add/subtract circuit:

The circuit is setup and shown in figure. To add the nibbles, C in is to be made 0. To subtract B 3 B2 B1 B0
from A3 A2 A 1 A0 Cin is to be made 1. EX-OR gates function as controlled inverters.

When Cin = 1, B3 B2 B1 B0 is complemented. Now A3 A2 A 1 A0 complemented version of B3 B2 B1 B0

and Cin pin are added together. Cout is ignored. By this, the 2s complement of subtrahend is added with
minuend. If minuend is less than subtrahend, the obtained output will be the 2s complement of
difference.

For example :
10 (Minued) Binary equivalent of 10 1010 +
9 (Subtrahend) 2s complement 9 0111

-1 (result) Result 1 0001

Carry omitted

When Minued < Subtrained :

9 Binary equivalent of 9 1001 +

10 2s complement of 10 0110

-1 2s complement 1 1111

Procedure:
1. Check all the components and IC Packages.
2. Set Up7483 for parallel adder circuit and verify the Truth Table.
3. Set up Parallel adder/Subtractor as shown in logic diagram.
4. For C-in=0, the circuit works as a parallel adder. For C-in=1 it acts as a parallel subtractor. Verify
the truth tables for both.

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4 Bit Adder/Subtractor Circuit

B3 B2 B1 B0

Ctrl
=0 to add
A3 A2 A1 A0 =1 to subtract

1 3 8 10 16 4 7 11
VCC
13
5
IC 7483 Cin
GND
12
14 15 2 6 9

Cout S3 S2 S1 S0

Truth Table:

Addition:

Decima Binary Eq no 1 Binary Eq no 2 Output Sum

l no
A B A3 A2 A1 A0 B3 B2 B1 B0 Co S3 S2 S1 S0
9 5 1 0 0 1 0 1 0 1 0 1 1 1 0
12 8 1 1 0 0 1 0 0 0 1 0 1 0 0

Subtraction:

Decima Binary Eq no 1 Binary Eq no 2 Output Sum

l no
A B A3 A2 A1 A0 B3 B2 B1 B0 Co S3 S2 S1 S0
8 14 1 0 0 0 1 1 1 0 0 1 0 1 0
8 2 1 0 0 0 0 0 1 0 1 0 1 1 0

Result : The parallel adder and subtractor circuit is realized using 7483 IC
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Expt No: 3b BCD TO EXCESS-3 CODE CONVERSION AND VICE VERSA

Aim: To perform the following code conversions

a. BCD to Excess-3 code

b. Excess-3 to BCD Code conversions

Components required: IC 7486, 7483, Trainer kit, patch chords.

Theory:
Natural BCD Code: In these code decimal digits 0 to 9 are represented (coded) by their natural binary
equivalents using 4 bits and each decimal digit of a decimal number is represented by four bit code
individually. For ex: (23)10 is represented by 0010 0011using BCD code, rather than (10111) 2. From this it
is observed that it requires more number of bits to code a decimal number using BCD code than using the
straight binary code. However, in spite of this disadvantage it is very convenient and useful code for input
and output digital systems.

This code is also known as 8-4-2-1 code or simply BCD code. 8, 4, 2, and 1 are the weights of the four
bits of the binary codes of each decimal digit similar to straight binary number system. Therefore this is a
weighted code and arithmetic operations can be performed using this code.

Excess-3 Code: Excess-3 code is another form of BCD code, in which each decimal digit is coded into a
4-bit binary code. This code for each decimal digit is obtained by adding decimal 3 to the natural BCD
code of the digit. For example decimal 2 is coded as 0010+0011=0101 in Excess-3 code. It is not a
weighted code. This code is a self complementing code, which means 1s complement of the coded
number yields 9s complement of the number itself. for example Excess-3 code of a decimal 2 is 0101,
its 1s complement is 1010 which is Excess-3 code for decimal 7,which is 9s, complement of 2. the self
complementing property of this code helps considerably in performing subtraction operation in digital
systems.

Procedure:
1. Verify all the components and patch chords whether they are in good condition.
2. Make connections as shown in logic diagram.
3. Give supply to the trainer kit.
4. For different Excess-3 codes inputs, verify the corresponding BCD data outputs according to
the truth table.
5. And also for different BCD data inputs verify the corresponding Excess-3 code outputs
according to the truth table.

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Truth Table:
BCD i/p Excess i/p
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

Logic diagram for BCD to Excess-3 Code Conversion

Vcc
Gnd

B3 B2 B1 B0

Ctrl
=0 to add
A3 A2 A1 A0 =1 to subtract

1 3 8 10 16 4 7 11
VCC
13
5
IC 7483 Cin
GND
12
14 15 2 6 9

Cout S3 S2 S1 S0

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Truth table for Excess-3 to BCD Conversion

Excess 3 i/p BCD o/p

B3 B2 B1 B0 E3 E2 E1 E0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

Result: The BCD to Excess-3 conversion and vice versa is realized using IC-7483.

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VIVA QUESTIONS:

1. Explain the need for code conversion.

2. What are the steps involved to convert a binary number into a Gray Code?
3. What are the steps involved to convert a Gray number into a binary Code?
4. Is gray code a weighted code?
5. What is weighted code? Give examples
6. What is Non weighted codes, give example?
7. What are reflected codes give examples?
8. What are self-complementary codes give examples?
9. What is BCD code?
10. Where are BCD codes used?

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Expt No: 4 BINARY TO GRAY CONVERSION AND VICE VERSA

Aim: To perform the following code conversions

1. A four bit Binary data to gray code converter using only NAND gates
2. A four bit Gray data to binary code converter using only NAND gates
3. A four bit Binary data to gray code converter using only EX-OR gates
4. A four bit Gray code to Binary data converter using only EX-OR gates

Components required: IC 7486, 7400, Patch chords, Trainer kit

Theory:
Gray Code: Gray code is an un-weighted code which means that there are no specific weights assigned to
the bit positions. The gray code exhibits only a single bit change from one code number to the next. Gray
code is not an arithmetic code.

Binary Data: The binary number system is simply another way to count. It is less complicated than the
decimal system, because it is composed of only 2 digits. The two binary digits are 1 and 0. The
position of the 1 or 0 in a binary number indicates its weights or value within the number. The weight
of each successively higher position (to the left) in a binary number is an increasing power of two.

Binary to gray conversion:

The conversion between Binary code and Gray code is sometime useful. The following are the steps to
convert a Binary number to a Gray code number
1. The most significant digit (left most) in the Gray code is the same as the corresponding digit in the
Binary number.
2. Going from left to right, add each adjacent pair of binary digits to get the next gray code digit.
Disregard carries.

Gray to Binary conversion:

To convert from Gray code to Binary a similar method is used but there are some differences. The
following are the steps to convert a Gray code number to the Binary number
1. The most significant digit (left most) in the binary code is the same as the corresponding digit in
the gray code.
2. Add each binary digit generated to the gray digit in the next adjacent position. Disregard carries.

Procedure:
1. Verify all the components and patch chords whether they are in good condition.
2. Make connections as shown in logic diagram.
3. Give supply to the trainer kit.
4. For different Binary data inputs, verify the corresponding Gray code outputs according to the truth
table.
5. And also for different Gray code inputs verify the corresponding Binary data outputs according to
the truth table.

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Truth Table:
Binary i/p Gray code o/p
B B2 B1 B0 G3 G2 G1 G0
3
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
K-Map Simplification
G3= B3 G2= B2 B3
B1B0
B1B0
00 01 11 10
00 01 11 10 B3B2
B3B2
00
00
01
01
11
11
10
10

G1= B1 B2 B1B0 G0= B0 B1

B1B0 00 01 11 10
B3B2
B3B2
00 01 11 10
00
00
01 01
Logic diagram for Binary to G
11 11
10
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10
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Logic diagram for Binary to Gray Code Conversion using NAND gates

Bo
Go

B1

G1

B2

G2

B3
G3

Logic diagram for Binary to Gray Code Conversion using basic gates
B3 G3

G2
B2

G1
B1

G0
B0

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Gray to binary conversion

Truth Table:
Gray i/p Binary o/p
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

K-Map

G1G0 G1G0

00 01 11 10 00 01 11 10
G3G2 G3G2

00 00

01 01

11 11

10 10

B3= G3 B2= G2 G3

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G1G0
G1G0
00 01 11 10
G3G2 00 01 11 10
G3G2
00
00
01
01
11
11
10
10

B1= G1 G2 G3 B0= G0 G1 G2 G3

Logic diagram for GRAY to Binary Code Conversion using basic gates
G3 B3

B2
G2

B1
G1

B0
G0

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Logic diagram for GRAY to Binary Code Conversion using NAND gates

Go

Bo

G1

B1

G2

B2

G3

B3

Result: The binary code to gray code and vice versa is realized using basic gates and universal gates.

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VIVA QUESTIONS :

1. What do you mean by code conversion?

2. What are the applications of code conversion?
3. What are code converters?
4. What is the necessity of code conversions?
5. What is gray code?
6. Realize the Boolean expressions for

a) Binary to gray code conversion

b) Gray to binary code conversion

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Expt No: 5 Multiplexer and Demultiplexer

Aim: To realize a 4:1 Mux using IC 74153 and verify its Truth Table

Components Required: IC 74153, 7404, 74139, 7400 Trainer kit, patch chords.

Theory:
Multiplexer:
The multiplexer is a special combination circuit that is one of the most widely used standard circuits in
digital designs. The multiplexer(Data selector) is a logic circuit that gets one out of several inputs to a
single output. The input selected is controlled by a set of select inputs.

DeMultiplexer:
The Demultiplexer performs the reversed operation of a multiplexer. it accepts a single input and
distributes it over several outputs . The select input code determines to which output the data input will be
transmitted.

IC74LS153: This IC is a dual 4-input multiplexer that can select 2-bits of data from up to 8-sources under
control of the common select inputs(S0 & S1).The two 4-input multiplexer circuits have individual active
low enables(Ea & Eb) which can be used to store the outputs independently. Outputs are forced low when
the corresponding enables are high.

IC74LS139: This IC is a high speed dual 1-input decoder/Demultiplexer. This dev ice has 2-independent
decoders each accepting 2-binary weighted inputs (X & Y) and providing 4 mutually exclusive active low
outputs (Y0 to Y3). Each decoder has an active low enable (E). When E=1 every output is forced high.

Procedure:
1. Verify all the components and patch chords whether they are in good condition.
2. Make connections as shown in logic diagram.
3. Give supply to the trainer kit.
4. Provide the input data to the circuit via switches.
5. Record and verify the output sequence for each combination of the select lines and verify that
it functions as multiplexers, Demultiplexers, Adders and sub tractors.

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Pin Diagram:
VC
C Vcc
Ea

e) on
bl cti
na ele
(E (S

b
E
S1
)

S0
I3
1 I2

2 I3 2 I2
1

IC 74153
I/Ps
J11
I1

I/Ps

I1
2
0
1I

o/p

I0
2
1Y
16

o/p

2Y
D
GN

Truth table for 74153 IC

215

314

413

512

710
611

89
1

Select I/p Enable I/p O/p

S1 S0 E I0 I1 I2 I3 Y
X X 1 X X X X 0
0 0 0 0 X X X 0
0 0 0 1 X X X 1
0 1 0 X 0 X X 0
0 1 0 X 1 X X 1
1 0 0 X X 0 X 0
1 0 0 X X 1 X 1
1 1 0 X X X 0 0
1 1 0 X X X 1 1

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Half Adder using 74153

`

Vcc 1 Y
=Su
m
2Y
=Ca
1
1I
rry
2
1I

a
E
C
3
1I

b
E
0
2I

4
J1

1
5
3
S1
16

14 2
S0

B
2I18

2I2

2I3
1I0

15
7

Truth Table of Half Adder

A B Sum Carry Y
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Design :
Sum : 1I0A+1I1A Carry :2I1A

1I0 1I1 2I0 2I1

A 0 1 A 0 0
A 1 0 A 0 1

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Full Adder

Logic diagram :

A Vcc

I0
1

m
=Su
1Y
I1
1
I

rry
=Ca
2Y
I2
1
C
7

a
E
I3
1
4
1

b
E
J1

I0
2

5
3

Vcc
16

S0S1

B C in
2I18

2I2

2I3
15

Truth Table:
7

A B C S CY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1

1 1 1 1 1

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Design:

Sum : (1I1+1 I2)A +(1I0+1I3)A Carry: (2I1+2I2)A +2I3

1I0 1I1 1I2 1I3 2I0 2I1 2I2 2I3

A 0 1 1 0 A 0 0 0 1
A 1 0 0 1 A 0 1 1 1

II Realization of Half and Full Subtractor Circuit using multiplexer IC 74153.

Half Subtractor Circuit using 74153

Truth Table
A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Design:
Difference Carry

1I0 1I1 2 I0 2I1

A 0 1
A 0 1
A 1 0
A 1 0
Diff =1I1A +1I0A Carry =2I1A

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Logic diagram :

`
A
Vcc

I0
1

ff
=Di
1Y
I1
1

w
rro
=Bo
2Y
I2
1
I3 7
1

b
E
4
1

a
E
5
J1

I0
2

Vcc
16

S1

B Cin
2I18

S0
2I2

2I3
15
7

Full Subtractor Circuit using 74153

Truth Table for Full Subtractor:

A B Cin Diff Borr

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0

1 1 1 1 1

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Design:

Difference Borrow

1I0 1I1 1I2 1I3 2I0 2I1 2I2 2I3

A 0 1 1 A0 0 1 1 1
A 1 0 0 1 0 0 0 1
A
Diff: A(1I1+1I2)+A(1I0 +1I3) Borrow : A(2I1+2I2) +2I3

Logic diagram:
A Vcc
I0
1

ff
=Di
1Y
I1
1

w
rro
=Bo
2Y
I2
1

a
E
I3
1

b
E
I0
2

Vcc
16

S1

B C in
S0
2I18

2I2

2I3
15
7

Result : The adder and subtractor circuits are realized using IC 74153.

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Full adder and full subtractor using Decoder IC

Pin Details for IC 74139 (3 to 8 line decoder):

Enable 1 1EG 1Y0 4

2 1X 1Y1 5
I/Ps
3 1Y 1Y2 6
7
4 7
Enable 2EG 1Y3
1
14 3 12
2X 2Y0
9
15
2Y 2Y1 11
13
2Y2 10

9
2Y3

814

Gnd
Vcc

Enable line is active low i/p line, all o/p lines are active low

Truth Table :

G Y X Y0 Y1 Y2 Y3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

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FULL ADDER

Truth table :

Inputs Outputs
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Sum= 1Y1+1Y2 + 2Y0 + 2Y3 Carry =1Y3 +2Y1 +2Y2 +2Y3

Logic diagram

2 4
1X 1Y0
Cin 14 5
2X 1Y1
3 6
1Y 7 1Y2
B 13 7 Sum
4
5 2Y 1 1Y3
12
1 3
1G 9 2Y0
A 11
2G 2Y1
10
Carr
15 2Y2 y
9
2Y3

8 14

Gnd
Vcc

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Full Subtractor

Truth table : Inputs Outputs

A B C Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Diff = 1Y1 2+2Y0+2Y3, Borrow =1Y1 +1Y2 +1Y3+2Y3

Logic diagram

2 4
1X 1Y0
Cin 14 5
2X 1Y1
3 6
1Y 7 1Y2
B 13 7 Diff
4
5 2Y 1 1Y3
1 3 12
1G 9 2Y0
A
2G 2Y1 11
Borro
15 2Y2 10 w
9
2Y3

8 14

Gnd
Vcc

Result : The full adder and subtractor circuits are realized using IC-74139.

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Logic Design LAB Manual

VIVA QUESTIONS :

1. Define the function of Multiplier.

2. For a 16: 1 MUX, How many AND gates and select lines are needed.
3. What is the need for select lines or control lines
4. Give the relationship between number of input lines and number of select lines
5. To construct a 32:1 MUX how many 4:1 MUX is required.
6. Give some practical applications of Multiplexers.
7. Define the function of Demultiplexer.
8. What is the need for ENABLE input in DEMUX.
9. When does a DEMUX act as a decoder? What is the condition?
10. Give some practical applications of DEMUX.
11. How do you design any code converters using DEMUX IC.
12. What is a multiplexer?
13. What is a de-multiplexer?
14. What are the applications of multiplexer and de-multiplexer?
15. Derive the Boolean expression for multiplexer and de-multiplexer.
16. How do you realize a given function using multiplexer
17. What is the difference between multiplexer & demultiplexer?
18. In 2n to 1 multiplexer how many selection lines are there?
19. How to get higher order multiplexers?
20. Implement an 8:1 mux using 4:1 muxes?

Expt No. 6 Magnitude Comparator

Aim: Realization of One/Two bit comparator & study of 7485 magnitude comparator

Apparatus required: IC 7400, 7404, 7408, 7402, 7432, 7486, 7485, Trainer kit Patch chords

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Theory: comparators can be designed for comparing multibit numbers. It receives 2 n bit numbers A&B
as inputs and the outputs are A>B, A=B and A<B. depending upon the relative magnitude of the 2-
numbers one of the outputs will be high.

About IC7485: IC 74LS85 is a 4-bit magnitude comparator it can be expanded to almost any length. It
compares two 4-bit Binary, BCD or other codes and presents the 3 possible magnitude results at the
output.

Procedure :
1. Verify all the components and patch chords whether they are in good condition.
2. Make connections as shown in logic diagram.
3. Give supply to the trainer kit.
4. Provide the input data to the circuit via switches.
5. Compare the input bit combinations and observe the outputs at A>B, A=B & A<B.
One bit Comparator:
Truth Table of One bit Comparator:

I/p O/p
A B A>B A=B A<
B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

K- map

0 1 0 1
0 0 0 0
0 0
1 0 1 0
1 0
A>B=AB A<B=AB A=B=AB +AB

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Logic diagram :

A B

A>B

A=B

A<B

Truth Table of Two bit Comparator:

I/p O/p
A A B B A< A= A>
1 0 1 0 B B B
0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1

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1 1 1 1 0 1 0
K-map Simplification:
1) A<B 2) A=B
B1B0 B1B0

00 01 11 10 00 01 11 10
A1A0 A1A0

00 00 1

01 01 1
11 11 1
10 10 1

3) A>B B1B0

00 01 11 10
A1A0

00

01

11

10

A<B A 1 B1+ A0 A 1 B0+ A 0 B1B 0

A=B(A0 B0)( A 1 B 1)

A>B A 1B1 +A0B1B0 +B0 A1A0

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Logic diagram

A1 A0
B1 B0

A>B

A=B

A<B

To compare the given data using 7485 Chip :

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Logic Design LAB Manual

15
13 12 10 1 14 11 9

4 A3 A2 A1 A0 B3 B2
A>B B0
B1
16 Vcc
A<B
2 IC 7485 8
3 GND
A=B A>B A=B A<B
3

Logic 1 5 6 7

Truth Table :

A B Result
A3 A2 A1 A0 B3 B2 B1 B0
0 0 0 1 0 0 0 0 A>B
0 0 0 1 0 0 0 1 A=B
0 0 0 0 0 0 0 1 A<B

Result : The magnitude comparator is built and verified by using basic gates and universal gates followed

by using magnitude comparator circuits IC-7485.

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VIVA QUESTIONS :

1. What is a comparator?
2. What are the applications of comparator?
3. Derive the Boolean expressions of one bit comparator and two bit comparators.
4. How do you realize a higher magnitude comparator using lower bit comparator
5. Design a 2 bit comparator using a single Logic gates?
6. Design an 8 bit comparator using a two numbers of IC 7485?
7. Give the pin configuration of IC 74139 and IC 74153.
8. What is the function of comparator?
9. How can we compare any 2 bit binary numbers?
10. Is it possible to compare 2 bit binary number using IC 7483? If yes, how?
11. How do you compare 4 bit binary number?
12. What is a magnitude comparator?
13. We can divide a number into two parts. What are they?
14. If a number is a positive number, then sign bit is ----------------- and a number if negative, then sign
bit is ---------------------.
15. What is magnitude of a number?
16. What is meant by cascading inputs?
17. Define Logic 1 and logic 0?
18. Let A be a 2 bit number and B be another 2 bit number, if A > B, then Cout = ------ and S
19. Is it possible to perform comparison of two, 8-bit number using magnitude comparator?
20. Where are the comparators used?

Expt No: 7a BCD- to -7 segment Decoder/driver

Aim : To set up and test a 7 segment static dispaly system to dislay numbers 0 to 9

Components and Equipments required:

IC 7447, 7 segment display (Common Anode), resistor (I K) and IC trainer kit

Theory:

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Logic Design LAB Manual

Seven segments display is the most popular display device used in digital systems. If the o/ps are active-
low, then the 7-segments LED must be of the common anode type, whereas if the o/p are active high, the
7 segment LED must be of the common cathode type.

The decoder/driver circuit has 4 i/p lines for BCD data and 7 output lies to drive a 7-segment
display. output terminals a through g of the decoder are to be connected to a through g terminals of the
display respecti\vely.The seven-segment indicators are usually of the common-anode type, where all the
anodes are strapped together and connected to a voltage +v.It is necessary to connect a current limiting
resistor (3 0r 8) to the LE D.The seven segment decoder/driver is designed to accepts four i/ps in he
8421 BCD code and to provide the appropriate o/p to drive a seven segment numerical display.

One such decoder /driver is the 7446/7447 IC decoder which drives a common anode indicator
mentioned earlier. Logic lets inside the decoder convert the BCD I/p to the required o/p.

For Example:
If the BCD i/p 0101, the internal logic of the decoder will force LEDs a, c, d, f and g to conduct as the
relevant transistors go in to saturation.Consequently, and digit 5 will be displayed on the seven-segment
indicator.

Procedure:
1. Check all the components and IC packages using millimeter and digital IC tester.
2. Make Connection as shown in the logic diagram
3. Give supply to the trainer kit
4. Provide the input data to the circuit via switches
5. Verify the truth table sequence and observe the o/ps

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Logic diagram:
+ 5V

1K
16
(LSB) A 7 13 7 3 or 8

B 12 6
1
7 11 4
4
C 2 10 2
4
7
D 6 9 1
(MSB) 15 9
LT 14
10
BI/RBO 8 o 5 (open)
RBI .

Truth table:

Decimal
BCD Inputs Output logic levels from IC 7447 to 7 -segment number
display
D C B A a b c d e f g
0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 1 0 0 1 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0 2
0 0 1 1 0 0 0 0 1 1 0 3
0 1 0 0 1 0 0 1 1 0 0 4
0 1 0 1 0 1 0 0 1 0 0 5
0 1 1 0 1 1 0 0 0 0 0 6
0 1 1 1 0 0 0 1 1 1 1 7
1 0 0 0 0 0 0 0 0 0 0 8
1 0 0 1 0 0 0 1 1 0 0 9

Result: The BCD to 7 segment display circuit is verified using decoder IC-7447.

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Logic Design LAB Manual

Expt No: 7b Priority Encoder :

Aim: 1.To set up a circuit of decimal to- BCD encoder using IC 74147
2 to set up a circuit of Octal to binary encoder using IC 74148

Co,mponents and equipments required :

IC 74147,IC 74148, Patch cards,Power chords and IC trainer Kit

Theory :
Decimal to- BCD encoder:
One of the most commonly used i/p device for a digital system is a set of ten switches one for each
numeral between 0 & 9.These switches generate 1 or 0 logic levels in response to turning them, of or on,
when a particular number is to be fed to the digital circuit in BCD code, the switch corresponding to that
number is pressed. There is an IC available for performing this function (74147),which is a priority
encoder the block diagram of IC 74147 is given in fig A and table gives its truth table, it has active low
i/ps and o/ps the meaning of the word priority can be seen from the truth table for example if i/ps 3 &
7are ;low the o/p will be corresponding to 7 which has a higher priority than 3 that is the highest
numbered i/p has priority over lower numbered i/ps

Octal To Binary Encoder:

The octal code is often used at the i/ps of digital circuits that require manual entering off long binary
words. Priority encoder 74148 IC has been designed to achieve this operation .Its block diagram is given
in figure C and table D gives its truth table .This circuit also has active low i/ps and active low o/ps .the
enable i/p and carry o/ps, which are also active low, are used to cascade circuits to handle more i/ps

Procedure:
1. Check all the components and patch chords whether they are in good condition
2. Set up the circuits as shown in the logic diagram
3. Give supply to the trainer kit and feed the active-low i/p bit combinations
4. Observe the active low o/p corresponding to active low i/p combinations and verify the truth
table.

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Logic symbol of IC 74147

11 16 Vcc
I1
12
I2
13 (LSB)
I3 7 A0
1 4 9
Active I4 1
low i/ps 2 7 A1 Active
4
I5 7 low o/ps
3 6 A2
I6
I7 4 14 A3

(MSB)
5
I8
10 8
I9

Block diagram of 74147 decimal to BCD priority encoder

Truth table of 74147

Inputs Output
I1 I2 I3 I4 I5 I6 I7 I8 I9 A3 A2 A2 A1
1 1 1 1 1 1 1 1 0 0 1 1 0
X X X X X X X 0 1 0 1 1 1
X X X X X X 0 1 1 1 0 0 0
X X X X X 0 1 1 1 1 0 0 1
X X X X 0 1 1 1 1 1 0 1 0
X X X 0 1 1 1 1 1 1 0 1 1
X X 0 1 1 1 1 1 1 1 1 0 0
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1

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Logic Symbol of IC 74148

5
E1 16 Vcc
I1 10
I0
I2 11
I1 7 6 (MSB)
I3 12 4
I2 1 A2
Active I4 13 4 7
low i/ps I3 A1 8 Active
I5 1 9 low o/ps
I4 A0 (LSB)
I6 2 15
I7 I5 E0
3 14
I6
I8 4 Gs

I9 I7 8

Block diagram of 74148 Octal to Binary priority encoder

Truth table :

Inputs Outputs
EI I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 Gs E0
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 X X X X X X X 0 0 0 0 0 1
0 X X X X X X 0 1 0 0 1 0 1
0 X X X X X 0 1 1 0 1 0 0 1
0 X X X X 0 1 1 1 0 1 1 0 1
0 X X X 0 1 1 1 1 1 0 0 0 1
0 X X 0 1 1 1 1 1 1 0 1 0 1
0 X 0 1 1 1 1 1 1 1 1 0 0 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1

Result : The decimal to BCD and Octal to binary Priority encoder verified using 74148.

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VIVA QUESTIONS :

Decoder:
1. What are the applications of decoder?
2. What is the difference between decoder & encoder?
3. For n- 2n decoder how many i/p lines & how many o/p lines?
4. What are the different codes & their applications?
5. What are code converters?
6. Using 3:8 decoder and associated logic, implement a full adder?
7. Implement a full Subtractor using IC 74138?
8. What is the difference between decoder and de-mux?
9. What is the function of a decoder?
10. Give the pin configuration of decoder chip?

7-segment display:
1. What are the different types of LEDs?
2. Draw the internal logic diagram of an LED.
3. What are the applications of LEDs?
4. What is the difference between common cathode configuration and common anode configuration?
5. Give the difference between LED and LCD.
6. How does an LED work?
7. What is meant by active low and active High?
8. What does Pull-up resistor or current limiting resistor, mean?
9. Why R is chosen as 330?

Priority Encoder:
1. What is a priority encoder?
2. What is the role of an encoder in communication?
3. What is the advantage of using an encoder?
4. What are the uses of validating outputs?
5. What is the function of RBO, RB1 and LT?
6. What is an Encoder?
7. What is priority encoder?

Expt No: 8 MASTER SLAVE J-K FLIP FLOPS

Aim: a) Rig up a Master Slave J-K Flip-Flop and verify its Truth Table

b) Rig up a T&D Flip-Flop and verify its Truth table

Apparatus: IC 7410, IC 7400, patch Chords and Trainer kits

Theory:

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Master flip flop: It is constructed from two separate flip flops, master section and slave section in
series .A clock i/p of the slave section is compliment of the clock i/p of the master i/p section

D Flip flop: It takes the state on its i/p and holds it until clocked again .Only a single i/p line is needed
for a transfer.

T flip flop: It provides the toggle action. Due to this type of flip flop changes its state with each i/p clock
pulse and hence such flip flops are used in a counting arrangements

Procedure:
1 Check all the components and patch chords whether they are in good condition
2 Make Connection as shown in the logic diagram
3. Give supply to the trainer kit
4. For MS JK Flip flop connect PRE and CLR to 1 and apply manually operated clock pulses to the
clock terminal and observe the o/p for all possible i/p combinations
5. Verify the truth tables of D and T flip flops

Logic diagram: MS JK Flip flop

Master Slave

Pr Q
J

Clk

K
Q
Clr

Truth Table:

preset Clear J K Clock Q Q Status

n n

0 1 X X 0 1 0 Set

1 0 X X 0 0 1 Reset

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1 1 0 0 Qn Qn No Change

1 1 0 1 0 1 Reset

1 1 1 0 1 0 Set

1 1 1 1 Qn Qn Toggle

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D- FlipFlop:

Master Slave
Pr Q
D

Q
Clr

Clk
Truth Table:

Clock preset Clear D Q Q

0 0 1 X 1 0
1 1 0 X 0 1
2 1 1 0 0 1
3 1 1 1 1 0

T Flip Flop:

Master Slave
Pr
Q
T

Q
Clr

Clk

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Truth Table:
preset Clear Tn Clock Q Q
0 1 X 0 1 0
1 0 X 1 0 1
1 1 0 2 Previous state
1 1 1 3 0/1 1/0 Toggles

Result: The master slave J-K, D and T flip flop are verified .

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VIVA QUESTIONS :

1. What is the difference between Flip-Flop & latch?

2. Give examples for synchronous & asynchronous inputs?
3. What are the applications of different Flip-Flops?
4. What is the advantage of Edge triggering over level triggering?
5. What is the relation between propagation delay & clock frequency of flip-flop?
6. What is race around in flip-flop & how to over come it?
7. Convert the J K Flip-Flop into D flip-flop and T flip-flop?
8. List the functions of asynchronous inputs?
9. What is a Flip-flop?
10. What is the difference between a flip-flop & latch?
11. How J-k flip-flop can be converted into T & D types?
12. What is the difference between Synchronous and Asynchronous clock pulse.

Expt. No. 9 3 BIT SYNCHRONOUS COUNTER

Aim: To design and test a 3 bit synchronous counter using 7476 FOR the given sequence:
1. Mod 5 Synchronous counter
2. Mod 8 Synchronous counter

Components Required: IC 7476, 7408, Trainer Kit, patch chords.

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Theory:
The ripple counter requires a finite amount of time for each flip flops to change state. The propagation
delay causes case flip flop in the counter to change state at a lower time than the first, resulting in a
serious limitation in the operating frequency. This problem can be solved by using a synchronous of
parallel counter, where every flip flop is triggered in synchronism with the clock, and all o/ps scheduled
to change do so simultaneously.
The structure, waveforms & truth tables of the synchronous counters are given below. the counter
progresses upwards in a natural binary sequence from count 000 to100 , advancing one. Count with every
negative clock transition and gets back to 000 after this cycle. We call this as mod 5 counter.
Procedure:
1. Connections are made as shown in the logic diagram
2. Find the number of FFs required using the equation
i. M 2n ----- this equation determines.
3. Write the count sequence in the tabular form
4. Prepare the excitation table of the FFs and determine the FF i/ps which must be present for the
desired next state from the present state
5. In terms of flip flop outputs prepare K map for each FF i/p and simplify the K-maps expression
in to a minimized form.
6. make connections as shown in the logic diagram
7. verify the truth table sequence and observe the o/ps.

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Pin diagram :

Gnd
K1 Q1 Q1 K2 Q2
Q2 J2

16 15 14 13 12 11 10 9

IC 7476

1 2 3 4 5 6 7 8

Cp1 Pr 1 J1 VCC Pr 2 Cr2

Cr1 Cp2
S

Cp = Clock pulse
Pr = Preset
Cr = Clear
Q = uncomplemented o/p
Q = Complemented o/p
J & k = i/ps

J k Flip flop Truth table:

Pr Cr Clk J K Q+ Q+
1 1 1 0 0 Q Q
No change
1 1 2 0 1 0 1 Reset
1 1 3 1 0 1 set
1 1 4 1 1 1/0 0/1 Toggle

1. Mod 5 Synchronous counter

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Excitation Table:
Q+ Q+ j k
0 0 0 Q
0 1 1 1
1 0 X 1
1 1 X 0

Transition Table:
Present State Next State Inputs
QC QB QA QC QB QA JA KA JB KB JC KC
0 0 0 0 0 1 1 X 0 X 0 X
0 0 1 0 1 0 X 1 1 X 0 X
0 1 0 0 1 1 1 X X 0 0 X
0 1 1 1 0 0 X 1 X 1 1 X
1 0 0 0 0 0 0 X 0 X X 1

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Karnaugh Map to derive the flip flop input function:

QB QA QB QA
00 01 11 10 00 01 11 10
QC QC
0 0 X 1 1 X
JA=QC
1 1 X X X X

KA=1
QB QA QB QA

00 01 11 10 00 01 11 10
QC QC

0 0
JB=QA KB=QA
1 1

QB QA
QBQA
00 01 11 10
00 01 11 10 QC
QC
0 X X X X
0 0 0 1 0
1 1 X X X
1 X X X X

KC=1
JC=QA. QB

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Mod 5 Synchronous counter

QC
QA QB
Vcc

Logic 1

Vcc
Clr Clr Clr
Clk
Mod 8 Synchronous counter (0-7) Logic 1
Transition table

Present State Next State Inputs

QC QB QA QC QB QA JA KA JB KB JC KC
0 0 0 0 0 1 1 X 0 X 0 X
0 0 1 0 1 0 X 1 1 X 0 X
0 1 0 0 1 1 1 X X 0 0 X
0 1 1 1 0 0 X 1 X 1 1 X
1 0 0 0 0 1 1 X 0 X X 0
1 0 1 1 1 0 X 1 1 X X 0
1 1 0 1 1 1 1 X X 0 X 0
1 1 1 0 0 0 X 1 X 1 X 1

K -map
QB QA
QB QA
00 01 11 10
00 01 11 10
Qc
0 Qc X 1 1 X
JA=1
1 X 1 1 X Page 69
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KA=1
Logic Design LAB Manual

0
1

QB QA QB QA

00 01 11 10 00 01 11 10
QC
Qc 1 1 X X
0 0
KB=QA
1 1 1 X X 1

JB=QA

QB QA QB QA

00 01 11 10 00 01 11 10
Qc 1 X X 1 Qc
0 0
KC=QA.QB
1 1 X X X 1

JC=QB.QA

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Logic diagram:
Mod 8 Synchronous counter

QA QC
QB
Vcc

Vcc

Vcc
Clr Clr Clr
Clk

Result : The Mod-5, Mod-8 counters are designed, implemented and verified.

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VIVA QUESTIONS :

1. How to design a Mod-N counter?

2. How addition and subtraction is done in a parallel adder circuits.
3. Explain the design for a Sequence Generator if the sequence given is ...
4. What is the difference between a sequence generator and PRBS?
5. Give the difference between sequential and combinational circuit.
6. What is a shift register?
7. What are the different modes of operation in a shift register?
8. What is the function of mode-control pin?
9. What are synchronous counters?
10. What are the advantages of synchronous counters?
11. What is an excitation table?
12. Write the excitation table for D, T FF
13. Design mod-5 synchronous counter using T F

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Expt No: 10 SHIFT REGISTER

Aim: To conduct an experiment to perform the following operations on a given 4 bit data using 7495.
i) Right Shift ii) SIPO iii) SISO iv) PIPO v) PISO vi) Left Shift
vii) Ring Counter
Components Required :
IC-7495, patch chords, power chord.
Theory: The IC-7495 is a 4-bit shift register, which has four flip-flops arranged sequentially. These are
capable of moving the contents position wise w.r.t.the clock input. Normally the shift registers are
classified into two categories
* Unidirectional
* Bi-directional
In our syllabus we use the different unidirectional shift registers like SISO, SIPO, PISO, PIPO
depending on the way the i/ps given and the o/ps taken. The i/ps & o/ps can be serial or parallel form.

Procedure:
For Right Shift & ii) Serial in Parallel out
1) Connections are made as shown in the logic diagram.
2) Apply the data at serial i/p
3) Apply one clock pulse at clock 1(Right Shift) observe this data at QA.
4) Apply the next data at serial i/p.
5) Apply one more clock pulse at clock 1, observe that the data on QA will shift to QB and the new
data applied will appear at QA.
6) Repeat steps 2 and 3 till all the 4 bits are entered one by one into the shift.

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Serial in Serial out (SISO)

1) Connections are made as shown in the logic diagram.
2) Load the shift register with 4 bits of data one by one serially.
3) At the end of the 4th clock pulse the first data D0 appears at QD.
4) Apply another clock pulse , the second data D1 appears at QD.
5) Apply another clock pulse , the third data D2 appears at QD.
6) Application of next clock pulse will enable the fourth data D3 to appear at QD. Thus the data
applied serially at the i/p comes out serially at QD.
iv) Parallel in Parallel out
1) Connections are made as shown in the logic diagram.
2) Apply the data bit at A,B,C,D
3) Apply one clock pulse at clock 2( Note: mode control M=1)
4) The 4 bit data at A, B,C,D appears at QA,QB,QC and QD.
v) Parallel in Serial out
1) Connections are made as shown in the logic diagram.
2) Apply the desired 4 bit data at A,B,C,D
3) Keeping the mode=1. Apply one clock pulse. the data applied at A,B,C and D will appear at
QA,QB,QC and QD respectively
4) Now Mode control=0. Apply clock pulses one by one and observe the data arriving out serially at
QD.
vi) Left Shift:
1) Connections are made as shown in the logic diagram.
2) Apply the first data at D and Apply the clock pulse. this data appears at QD
3) Now the second data is made available at D and one clock pulse is applied. The data appears at QC
and the new data appears at QD.
4) Step 3 is repeated until all the 4 bits are entered one by one.
5) At the end of 4th clock pulse the 4 bits are available at QA,QB,QC and QD.

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PIN DIAGRAM OF IC 7495

O/PS

VCC QA QB QC QD CLK1 CLK2

c c

14 13 2 11 10 9 8

IC 7495

1 2 3 4 5 6 7

DS A B C D MC Gnd
S S S
I/Ps

MC-Mode Control : 0 - serial operation,1 parallel operation

DS Serial data i/p

I SISO (Serial in Serial out)

VCC QA QB QC QD CLK1
c c

14 13 2 11 10 9 8

IC 7495

1 2 3 4 5 6 7

DS MC Gnd
S

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Truth table :

Clock Mc DS QA QB QC QD
1 0 1(D0 1 X X X
)
2 0 1(D1 1 1 X X
)
3 0 0(D2 0 1 1 X
)
4 0 1(D3 1 0 1 1=D0
)
5 0 - X 1 0 1=D1
6 0 - X X 1 0=D2
7 0 - X X X 1=D3
8 0 - X X X X

II Logic diagram: SIPO (Right Shift)

Same above Circuit( i.e used for SISO)

Truth Table:

Clock Mc DS QA QB QC QD
1 0 0(D0) 0 X X X
2 0 1(D1) 1 0 X X
3 0 0(D2) 0 1 0 X
4 0 1(D3) 1 0 1 0 Parallel out
D3 D2 D1 D0
III PISO (parallel In serial out)
Out puts

VCC QA QB QC QD CLK1
c c

14 13 2 11 10 9 8

IC 7495

1 2 3 4 5 6 7

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Truth table I/Ps

CLK M A B C D Q Q Q Q
1 C A B C D
1 1 1 1 0 1 1 1 0 1
2 0 - - - - X 1 1 0
3 0 - - - - X X 1 1
4 0 - - - - X X X 1

A,B.C,& D I/Ps
QA,QB,QC,QD O/Ps

IV PIPO (Parallel in parallel out)

Truth Table : PIPO

CLK1 MC A B C D QA QB QC QD
1 1 1 0 1 0 1 0 1 0
A,B,C & D Parallel In
QA,QB,QC& QD Parallel Out

V Serial I/P Left Shift

QC
QB
QD
c
VCC QA CLK 2
c

14 13 12 11 10 9 8

IC 7495

1 2 3 4 5 6 7

MC Gnd

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Truth Table:

Clock 2 D QA QB QC QD
1 1 X X X 1
2 0 X X 1 0
3 1 X 1 0 1
4 0 1 0 1 0
5 __ 0 1 0 X
6 __ 1 0 X X
7 __ 0 X X X
8 __ X X X X
D I/P
QA,QB,QC & QD O/Ps

Result : The Shift registers are verified using IC-7495.

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VIVA QUESTIONS :

1. What are PISO, SIPO, and SISO with respect to shift register
2. Differentiate between serial data & parallel data
3. What is the significance of Mode control bit?

Expt No: 11 RING COUNTER & JOHNSON COUNTER

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Aim: To realize the operation of ring and Johnson counter using 7495.
Components Required: I.C.7495, patch chords, digital trainer.
Theory:
Ring counter
Ring counter is a basic register with direct feedback such that the contents of the registers simply
circulated around the register when the clock is running. Here the last output that is QD in a shift register
is connected back to the serial input. A four bit shift register ring counter is shown in figure.

Johnson counter
A basic ring counter can be modified slightly to produce another type of shift register counter, which
will have somewhat different properties. That type of basic shift register with inverse feed back is
called shift counter or a Johnson counter or a twisted ring counters. In Johnson counter the
compliment of the last outp8t that is QD is connected back to the not gate input and the Not gate output
is connected back to the serial input. The four bit Johnson counter gives a total of eight states. As the
clock pulse is applied at pin no 9 will fill up with one (1) from left to right and then it will fill up with
0.

Procedure :
1) Connections are made as shown in the logic diagram.
2) Apply the data 1000 at A,B,C,D respectively.
3) Keeping the mode M=1, apply one clock pulse.
4) Now the mode M is made 0 and clock pulse are applied one by one and the truth table is verified

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Logic diagram: Ring Counter

VCC QA QB QC QD CLK1
c c

14 13 2 11 10 9 8

IC 7495

1 2 3 4 5 6 7

DS A B C D MC Gnd
S S S

* MC = mode control = 0

Truth table

ClK 1 QA QB QC QD
0 1 0 0 0
1 0 1 0 0
2 0 0 1 0
3 0 0 0 1
4 1 0 0 0
5 0 1 0 0
6 0 0 1 0
7 0 0 0 1
8 1 0 0 0

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Logic diagram: Johnson Counter

VCC QA QB QC QD CLK1
c c

14 13 2 11 10 9 8

IC 7404
IC 7495

1 2 3 4 5 6 7

DS A B C D MC Gnd
S S S

Truth Table:
Mode Clock QA QB QC QD
0 0 0 0 0 0
0 1 1 0 0 0
0 2 1 1 0 0
0 3 1 1 1 0
0 4 1 1 1 1
0 5 0 1 1 1
0 6 0 0 1 1
0 7 0 0 0 1
0 8 0 0 0 0
0 9 1 0 0 0

Result: The ring and Johnson counter are verified using IC-7495.

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VIVA QUESTIONS :

1. What is a ring counter?

2. What is a Johnson counter?

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Expt No: 12 SEQUENCE GENERATOR

Aim: Design of a sequence Generator using IC 7495

Components Required: Digital trainer kit, IC 7495 & 7486, patch chords.

Theory:
A sequential circuit, which generates a prescribed sequence of bits, in synchronism with a clock, is
referred as sequence generator. For the design of sequence generator we must determine the required
number of the clocks and the logic circuit for the next state decoder. The output of next state decoder is
function of Qa, QB, QC, QD Qn. The next state decoder is the logic circuit, which decodes the output of
the shift register and generates the output to get desired sequence from QA output of the shift register.
Procedure:

1) Make connections as per the logic diagram

2) By keeping the mode=1. Load the input through A, B, C, D as 1111 by giving one clock pulse
3) For count mode make mode=0
4) And observe the sequence at QA, QB, QC and QD.

Logic diagram:

Y
VCC QA QB QC QD CLK1
c c

14 13 2 11 10 9 8

IC 7495

1 2 3 4 5 6 7

A B C D MC Gnd
Serial input
S S

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1.Sequence given ; 100010011010111

K-MAP
QA QB QC QD Y
1 1 1 1 0
0 1 1 1 0 X 1 0 1
0 0 1 1 0 0 1 0 1
0 0 0 1 1 0 1 0 1
1 0 0 0 0
0 1 0 1
0 1 0 0 0
0 0 1 0 1
1 0 0 1 1
1 1 0 0 0
Y=QcQD +QD Qc
0 1 1 0 1
Y = Qc+ QD
1 0 1 1 0
0 1 0 1 1
1 0 1 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1
1 1
1

Sequence : 1101011 sequence length =7

Truth table :
K-Map:
S QA QB QC QD
1 1 1 0 1
1 1 1 1 0 X X X X
0 1 1 1 1 X 1 1 X
1 0 1 1 1 X 1 0 1
0 1 0 1 1 X X 0 1
1 0 1 0 1
1 1 0 1 0
S = QA +QC +QD

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Logic diagram :

Y
VCC QA QB QC QD CLK1
c c

14 13 2 11 10 9 8

IC 7495

1 2 3 4 5 6 7

DS A B C D MC Gnd
S S

Result: The given sequence is designed and implemented using IC-7495.

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VIVA QUESTIONS :

1. What is the necessity for sequence generation?

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