2.

1 (a)
k = 8.617 105 eV/K
15

3/2

ni (T = 300 K) = 1.66 10 (300 K)

exp

0.66 eV
2 (8.617 105 eV/K) (300 K)

cm3

exp

0.66 eV
2 (8.617 105 eV/K) (600 K)

cm3

= 2.465 1013 cm3

15

3/2

ni (T = 600 K) = 1.66 10 (600 K)

= 4.124 1016 cm3

Compared to the values obtained in Example 2.1, we can see that the intrinsic carrier concentration
13
in Ge at T = 300 K is 2.46510
1.081010 = 2282 times higher than the intrinsic carrier concentration in
Si at T = 300 K. Similarly, at T = 600 K, the intrinsic carrier concentration in Ge is
26.8 times higher than that in Si.

4.1241016
1.541015

(b) Since phosphorus is a Group V element, it is a donor, meaning ND = 5 1016 cm3 . For an
n-type material, we have:
n = ND = 5 1016 cm3
2

[ni (T = 300 K)]

= 1.215 1010 cm3
n
[ni (T = 600 K)]2
= 3.401 1016 cm3
p(T = 600 K) =
n
p(T = 300 K) =

2.3 (a) Since the doping is uniform, we have no diffusion current. Thus, the total current is due only to
the drift component.
Itot = Idrif t
= q(nn + pp )AE
n = 1017 cm3
p = n2i /n = (1.08 1010 )2 /1017 = 1.17 103 cm3
n = 1350 cm2 /V s
p = 480 cm2 /V s
1V
E = V /d =
0.1 m
= 105 V/cm
A = 0.05 m 0.05 m
= 2.5 1011 cm2
Since nn pp , we can write
Itot qnn AE
= 54.1 A
(b) All of the parameters are the same except ni , which means we must re-calculate p.
ni (T = 400 K) = 3.657 1012 cm3
p = n2i /n = 1.337 108 cm3
Since nn pp still holds (note that n is 9 orders of magnitude larger than p), the hole
concentration once again drops out of the equation and we have
Itot qnn AE
= 54.1 A

2.4 (a) From Problem 1, we can calculate ni for Ge.

ni (T = 300 K) = 2.465 1013 cm3
Itot = q(nn + pp )AE
n = 1017 cm3
p = n2i /n = 6.076 109 cm3
n = 3900 cm2 /V s
p = 1900 cm2 /V s
1V
E = V /d =
0.1 m
= 105 V/cm
A = 0.05 m 0.05 m
= 2.5 1011 cm2
Since nn pp , we can write
Itot qnn AE
= 156 A
(b) All of the parameters are the same except ni , which means we must re-calculate p.
ni (T = 400 K) = 9.230 1014 cm3
p = n2i /n = 8.520 1012 cm3
Since nn pp still holds (note that n is 5 orders of magnitude larger than p), the hole
concentration once again drops out of the equation and we have
Itot qnn AE
= 156 A

2.5 Since theres no electric field, the current is due entirely to diffusion. If we define the current as positive
when flowing in the positive x direction, we can write


dn
dp
Itot = Idif f = AJdif f = Aq Dn
Dp
dx
dx
A = 1 m 1 m = 108 cm2

Dn = 34 cm2 /s
Dp = 12 cm2 /s
5 1016 cm3
dn
=
= 2.5 1020 cm4
dx
2 104 cm
dp
2 1016 cm3
=
= 1020 cm4
dx
2 104 cm






Itot = 108 cm2 1.602 1019 C 34 cm2 /s 2.5 1020 cm4 12 cm2 /s 1020 cm4
= 15.54 A

2.8 Assume the diffusion lengths Ln and Lp are associated with the electrons and holes, respectively, in this
material and that Ln , Lp 2 m. We can express the electron and hole concentrations as functions
of x as follows:
n(x) = N ex/Ln
p(x) = P e(x2)/Lp
Z 2
an(x)dx
# of electrons =
0

aN ex/Ln dx

2


= aN Ln ex/Ln
0


2/Ln
1
= aN Ln e
Z 2
# of holes =
ap(x)dx
0

aP e(x2)/Lp dx

2


= aP Lp e(x2)/Lp
0

2/Lp
= aP Lp 1 e

Due to our assumption that Ln , Lp 2 m, we can write

e2/Ln 0
e2/Lp 0

# of electrons aN Ln
# of holes aP Lp

2.10 (a)
nn = ND = 5 1017 cm3
pn = n2i /nn = 233 cm3
pp = NA = 4 1016 cm3
np = n2i /pp = 2916 cm3
(b) We can express the formula for V0 in its full form, showing its temperature dependence:
"
#
NA ND
kT
ln
V0 (T ) =
q
(5.2 1015 )2 T 3 eEg /kT
V0 (T = 250 K) = 906 mV
V0 (T = 300 K) = 849 mV
V0 (T = 350 K) = 789 mV
Looking at the expression for V0 (T ), we can expand it as follows:
V0 (T ) =

kT
ln(NA ) + ln(ND ) 2 ln 5.2 1015 3 ln(T ) + Eg /kT
q

Lets take the derivative of this expression to get a better idea of how V0 varies with temperature.


k
dV0 (T )
ln(NA ) + ln(ND ) 2 ln 5.2 1015 3 ln(T ) 3
=
dT
q

15
From this expression, we can see
that
if
ln(N
)
+
ln(N
)
<
2
ln
5.2

10
+ 3 ln(T ) + 3, or
A
D
h
i

15 2 3
equivalently, if ln(NA ND ) < ln 5.2 10
T 3, then V0 will decrease with temperature,
which we observe in this case. In order for this not to be true (i.e., in order for V0 to increase with
temperature), we must have either very high doping concentrations or very low temperatures.

2.11 Since the p-type side of the junction is undoped, its electron and hole concentrations are equal to the
intrinsic carrier concentration.
nn = ND = 3 1016 cm3
pp = ni = 1.08 1010 cm3


N D ni
V0 = VT ln
n2i


ND
= (26 mV) ln
ni
= 386 mV

2.12 (a)
r

qSi NA ND 1
2 NA + ND V0
Cj0
Cj = p
1 VR /V0

Cj0 =

NA = 2 1015 cm3
ND = 3 1016 cm3

VR = 1.6 V


NA ND
= 701 mV
V0 = VT ln
n2i

Cj0 = 14.9 nF/cm2

Cj = 8.22 nF/cm2

= 0.082 fF/cm2
(b) Lets write an equation for Cj in terms of Cj assuming that Cj has an acceptor doping of NA .
Cj = 2Cj
s

qSi NA ND
1
= 2Cj
2 NA + ND VT ln(NA ND /n2i ) VR
1
qSi NA ND
= 4Cj2

2 NA + ND VT ln(NA ND /n2i ) VR

NA

qSi NA ND = 8Cj2 (NA + ND )(VT ln(NA ND /n2i ) VR )

qSi ND 8Cj2 (VT ln(NA ND /n2i ) VR ) = 8Cj2 ND (VT ln(NA ND /n2i ) VR )
NA =

8Cj2 ND (VT ln(NA ND /n2i ) VR )

qSi ND 8Cj2 (VT ln(NA ND /n2i ) VR )

We can solve this by iteration (you could use a numerical solver if you have one available). Starting
with an initial guess of NA = 2 1015 cm3 , we plug this into the right hand side and solve to
find a new value of NA = 9.9976 1015 cm3 . Iterating twice more, the solution converges to
NA = 1.025 1016 cm3 . Thus, we must increase the NA by a factor of NA /NA = 5.125 5 .

2.16 (a) The following figure shows the series diodes.

ID
+

D1

VD
D2

Let VD1 be the voltage drop across D1 and VD2 be the voltage drop across D2 . Let IS1 = IS2 = IS ,
since the diodes are identical.
VD = VD1 + VD2


ID
ID
+ VT ln
= VT ln
IS
IS

ID
= 2VT ln
IS
ID = IS eVD /2VT

Thus, the diodes in series act like a single device with an exponential characteristic described by
ID = IS eVD /2VT .
(b) Let VD be the amount of voltage required to get a current ID and VD the amount of voltage
required to get a current 10ID .

ID
VD = 2VT ln
IS


10ID

VD = 2VT ln
IS



ID
10ID

ln
VD VD = 2VT ln
IS
IS
= 2VT ln (10)

= 120 mV

2.19
VX = IX R1 + VD1

IX

IX
= IX R1 + VT ln
IS

VT
IX
VX

ln
=
R1
R1
IS

For each value of VX , we can solve this equation for IX by iteration. Doing so, we find
IX (VX = 0.5 V) = 0.435 A
IX (VX = 0.8 V) = 82.3 A
IX (VX = 1 V) = 173 A
IX (VX = 1.2 V) = 267 A
Once we have IX , we can compute VD via the equation VD = VT ln(IX /IS ). Doing so, we find
VD (VX = 0.5 V) = 499 mV
VD (VX = 0.8 V) = 635 mV
VD (VX = 1 V) = 655 mV
VD (VX = 1.2 V) = 666 mV
As expected, VD varies very little despite rather large changes in ID (in particular, as ID experiences
an increase by a factor of over 3, VD changes by about 5 %). This is due to the exponential behavior
of the diode. As a result, a diode can allow very large currents to flow once it turns on, up until it
begins to overheat.

2.22
VX /2 = IX R1 = VD1 = VT ln(IX /IS )
VT
IX =
ln(IX /IS )
R1
IX = 367 A (using iteration)
VX = 2IX R1
= 1.47 V

3.1 (a)
IX =

VX
R1

VX < 0
VX > 0

IX
VX (V)

Slope = 1/R1

3.2
IX =

VX
R1

VX < 0
VX > 0

Plotting IX (t), we have

V0 /R1

0
t

V0

VX (t) (Dotted)

IX (t) for VB = 1 V (Solid)

V0

3.3
IX =

0
VX VB
R1

VX < VB
VX > VB

Plotting IX vs. VX for VB = 1 V and VB = 1 V, we get:

IX
VB = 1 V
VB = 1 V

Slope = 1/R1

Slope = 1/R1

1
VX (V)

3.4
IX =

0
VX VB
R1

VX < VB
VX > VB

Lets assume V0 > 1 V. Plotting IX (t) for VB = 1 V, we get

(V0 VB )/R1

VB

Plotting IX (t) for VB = 1 V, we get

0
t

V0

VX (t) (Dotted)

IX (t) for VB = 1 V (Solid)

V0

IX (t) for VB = 1 V (Solid)

(V0 VB )/R1

0
0

/
0
t
/
V0

VX (t) (Dotted)

V0

VB

3.5
IX =

VX VB
R1

VX < 0
VX > 0

Plotting IX vs. VX for VB = 1 V and VB = 1 V, we get:

IX
IX for VB = 1 V
IX for VB = 1 V
1/R1
Slope = 1/R1

1
VX (V)
1/R1
Slope = 1/R1

3.6 First, note that ID1 = 0 always, since D1 is reverse biased by VB (due to the assumption that VB > 0).
We can write IX as
IX = (VX VB )/R1
Plotting this, we get:

IX

VB
VX (V)

Slope = 1/R1

3.7
IX =
IR1 =

VX VB
R1
VX VB
R1 kR2

VX < VB
VX > VB

VX VB
R1

Plotting IX and IR1 for VB = 1 V, we get:

IX
IX for VB = 1 V
IR1 for VB = 1 V

Slope = 1/R1 + 1/R2

1
Slope = 1/R1

Plotting IX and IR1 for VB = 1 V, we get:

VX (V)

IX
IX for VB = 1 V
IR1 for VB = 1 V

Slope = 1/R1 + 1/R2

1
VX (V)

Slope = 1/R1

3.8
IX =

(
0

IR1 =

VX
R1

VB
R1 +R2
VX
R1

VX VB
R2

VX <
VX >

VX <
VX >

VB
R1 +R2 R1
VB
R1 +R2 R1

VB
R1 +R2 R1
VB
R1 +R2 R1

Plotting IX and IR1 for VB = 1 V, we get:

IX for VB = 1 V
IR1 for VB = 1 V

Slope = 1/R1 + 1/R2

VB /R2

Slope = 1/R1

VB
R
R1 +R2 1
VB
R1 +R2

Plotting IX and IR1 for VB = 1 V, we get:

VX (V)

IX for VB = 1 V
IR1 for VB = 1 V

Slope = 1/R1 + 1/R2

Slope = 1/R1

VB
R1 +R2
VB
R
R1 +R2 1

VX (V)

3.9 (a)

Vout (V)

Vout =

VB
Vin

Vin < VB
Vin > VB

5
Slope = 1

0
5

(b)
Vout

(
Vin VB
=
0

Vin < VB
Vin > VB

5
Vin (V)

Vout (V)

2
1
0

5
Vin (V)

2
3
Slope = 1

4
5
6
7

(c)

Vout (V)

Vout = Vin VB

3
Slope = 1

2
1
0

1
1
2
3
4
5
6
7

5
Vin (V)

Vout =

Vout (V)

(d)

Vin
VB

Vin < VB
Vin > VB

1
0
5

1
Slope = 1

5
(e)
Vout

(
0
=
Vin VB

Vin < VB
Vin > VB

5
Vin (V)

Vout (V)

Slope = 1

0
5

5
Vin (V)

3.11 For each part, the dotted line indicates Vin (t), while the solid line indicates Vout (t). Assume V0 > VB .
(a)

Vout (t) (V)

Vout =

VB
Vin

Vin < VB
Vin > VB

V0
VB

V0
(b)
Vout

(
Vin VB
=
0

Vin < VB
Vin > VB

Vout (t) (V)

V0
VB

V0

V0 VB

(c)

Vout (t) (V)

Vout = Vin VB

V0
VB
V0 VB
/

V0

V0 VB

(d)

Vout (t) (V)

Vout =

Vin
VB

Vin < VB
Vin > VB

V0
VB

V0
(e)
Vout

(
0
=
Vin VB

Vin < VB
Vin > VB

Vout (t) (V)

V0
VB
V0 VB

V0

3.12 For each part, the dotted line indicates Vin (t), while the solid line indicates Vout (t). Assume V0 > VB .
(a)

Vout (t) (V)

Vout

(
Vin VB
=
0

Vin < VB
Vin > VB

V0
VB

V0

V0 VB
(b)
Vout =

Vin
VB

Vin < VB
Vin > VB

Vout (t) (V)

V0
VB

V0

Vout

(
0
=
Vin VB

Vout (t) (V)

(c)

V0

Vin < VB
Vin > VB

VB
V0 VB

V0

(d)

Vout (t) (V)

Vout = Vin VB

V0
VB
V0 VB
/

V0

V0 VB
(e)
Vout =

VB
Vin

Vin < VB
Vin > VB

Vout (t) (V)

V0
VB

V0

3.16 (a)
IR1 =

Iin
VD,on
R1

Iin <
Iin >

VD,on
R1
VD,on
R1

IR1
VD,on /R1

VD,on /R1
Iin

Slope = 1

(b)
IR1 =

Iin
VD,on +VB
R1

Iin <
Iin >

VD,on +VB
R1
VD,on +VB
R1

IR1
(VD,on + VB ) /R1

(VD,on + VB ) /R1
Iin

Slope = 1

(c)
IR1 =

Iin
VD,on VB
R1

Iin <
Iin >

VD,on VB
R1
VD,on VB
R1

IR1

(VD,on VB ) /R1
Iin
(VD,on VB ) /R1

Slope = 1

(d)
IR1 =

Iin
VD,on
R1

Iin <
Iin >

VD,on
R1
VD,on
R1

IR1
VD,on /R1

VD,on /R1
Iin

Slope = 1

3.17 (a)
Vout =

Iin R1
VD,on

Iin <
Iin >

VD,on
R1
VD,on
R1

VD,on /R1
VD,on
0

I0 R1

0
t

(b)
Vout =

Iin R1
VD,on + VB

Iin <
Iin >

VD,on +VB
R1
VD,on +VB
R1

I0

Iin (t) (Dotted)

Vout (t) (Solid)

I0

I0
(VD,on+VB )/R1

Iin (t) (Dotted)

Vout (t) (Solid)

VD,on + VB

I0 R1

0
t

I0

(c)
Vout =

Iin R1 + VB
VD,on

Iin <
Iin >

VD,on VB
R1
VD,on VB
R1

VD,on
0

I0 R1 + VB
(VD,on VB ) /R1

0
t

I0

Iin (t) (Dotted)

Vout (t) (Solid)

I0

(d)
Vout =

Iin R1 + VB
VD,on + VB

Iin <
Iin >

VD,on
R1
VD,on
R1

I0

VD,on /R1
0

I0 R1 + VB

0
t

I0

Iin (t) (Dotted)

Vout (t) (Solid)

VD,on + VB

3.20 (a)
Vout =

Iin R1
VB VD,on

Iin >
Iin <

VB VD,on
R1
VB VD,on
R1

I0

I0 R1
VB VD,on
0

0
t

(b)
Vout =

Iin R1 + VB
VD,on

+V

B
Iin > D,on
R1
VD,on +VB
Iin <
R1

I0

Iin (t) (Dotted)

Vout (t) (Solid)

(VB VD,on ) /R1

I0

Iin (t) (Dotted)

Vout (t) (Solid)

I0 R1 + VB

VD,on

(VD,on +VB )/R1

0
t

I0

(c)
Vout =

Iin R1 + VB
VB VD,on

Iin > D,on

R1
V
Iin < D,on
R1

I0

VB VD,on
0

0
VD,on /R1

0
t

I0

Iin (t) (Dotted)

Vout (t) (Solid)

I0 R1 + VB

3.23 (a)
R2
R1 +R2 Vin

VD,on

Vout (V)

Vout =

Vin <
Vin >

R1 +R2
R2 VD,on
R1 +R2
R2 VD,on

VD,on

R1 +R2
VD,on
R2

Vin (V)
Slope = R2 / (R1 + R2 )

(b)
Vout =

R2
R1 +R2 Vin

Vin VD,on

Vin <
Vin >

R1 +R2
R1 VD,on
R1 +R2
R1 VD,on

Vout (V)

Slope = 1

R2
V
R1 D,on

Slope = R2 / (R1 + R2 )

R1 +R2
VD,on
R1

Vin (V)

3.24 (a)
IR1 =

Vin
R1 +R2
Vin VD,on
R1

ID1 =

0
Vin VD,on
R1

Vin <
Vin >

VD,on
R2

R1 +R2
R2 VD,on
R1 +R2
R2 VD,on

Vin <
Vin >

R1 +R2
R2 VD,on
R1 +R2
R2 VD,on

IR1
ID1

Slope = 1/R1

Slope = 1/R1

VD,on /R2
R1 +R2
VD,on
R2

Vin (V)

Slope = 1/ (R1 + R2 )

(b)
IR1 =

Vin
R1 +R2
VD,on
R1

ID1 =

Vin <
Vin >

Vin VD,on
R2

R1 +R2
R1 VD,on
R1 +R2
R1 VD,on

VD,on
R1

Vin <
Vin >

R1 +R2
R1 VD,on
R1 +R2
R1 VD,on

VD,on /R1
IR1
ID1
Slope = 1/R2
R1 +R2
VD,on
R1

Vin (V)

Slope = 1/ (R1 + R2 )

3.25 (a)
2
VB + R1R+R
(Vin VB )
2
Vin VD,on

Vin < VB +
Vin > VB +

R1 +R2
R1 VD,on
R1 +R2
R1 VD,on

Vout (V)

Vout =

Slope = 1

VB +

R2
V
R1 D,on

VB +
Slope = R2 / (R1 + R2 )

R1 +R2
VD,on
R1

Vin (V)

(b)
Vout =

R2
R1 +R2 Vin

Vin VD,on VB

Vin <
Vin >

R1 +R2
R1
R1 +R2
R1

(VD,on + VB )
(VD,on + VB )

Vout (V)

Slope = 1

R2
R1

(VD,on + VB )

VB +

Slope = R2 / (R1 + R2 )

R1 +R2
R1

(VD,on + VB )
Vin (V)

(c)
R2
R1 +R2

(Vin VB ) Vin > VB +

Vin + VD,on VB Vin < VB +

Vout (V)

Vout =

R1 +R2
R1 VD,on
R1 +R2
R1 VD,on

Slope = R2 / (R1 + R2 )

R2
V
R1 D,on

VB +

R1 +R2
VD,on
R1

Vin (V)
Slope = 1

(d)
R2
R1 +R2

(Vin VB ) Vin < VB +

Vin VD,on
Vin > VB +

R1 +R2
R1
R1 +R2
R1

Vout (V)

Vout =

(VD,on VB )
(VD,on VB )

Slope = 1

R2
V
R1 D,on

VB +
Slope = R2 / (R1 + R2 )

R1 +R2
R1

(VD,on VB )
Vin (V)

3.26 (a)
IR1 =

Vin VB
R1 +R2
VD,on
R1

ID1 =

Vin < VB +
Vin > VB +

Vin VD,on VB
R2

IR1
ID1

R1 +R2
R1 VD,on
R1 +R2
R1 VD,on

Vin < VB +
Vin > VB +

VD,on
R1

R1 +R2
R1 VD,on
R1 +R2
R1 VD,on

VD,on /R1

Slope = 1/R2
VB +

R1 +R2
VD,on
R1

Vin (V)
Slope = 1/ (R1 + R2 )

(b)
IR1 =

Vin
R1 +R2
VD,on +VB
R1

ID1 =

Vin <
Vin >

Vin VD,on VB
R2

R1 +R2
R1
R1 +R2
R1

(VD,on + VB )
(VD,on + VB )

VD,on +VB
R1

Vin <
Vin >

R1 +R2
R1
R1 +R2
R1

(VD,on + VB )
(VD,on + VB )

(VD,on + VB ) /R1
IR1
ID1

Slope = 1/R2
R1 +R2
R1

(VD,on + VB )
Vin (V)

Slope = 1/ (R1 + R2 )

(c)
IR1 =

Vin VB
R1 +R2
V
D,on
R1

ID1 =

0
V +VD,on +VB
in R

Vin > VB
Vin < VB

R1 +R2
R1 VD,on
R1 +R2
R1 VD,on

VD,on
R1

Vin > VB
Vin < VB

R1 +R2
R1 VD,on
R1 +R2
R1 VD,on

IR1
ID1
Slope = 1/R2
Slope = 1/ (R1 + R2 )

VB +

R1 +R2
VD,on
R1

Vin (V)
VD,on /R1
(d)
IR1 =

Vin VB
R1 +R2
VD,on VB
R1

ID1 =

0
Vin VD,on
R2

Vin < VB +
Vin > VB +

VD,on VB
R1

R1 +R2
R1
R1 +R2
R1

(VD,on VB )
(VD,on VB )

Vin < VB +
Vin > VB +

R1 +R2
R1
R1 +R2
R1

(VD,on VB )
(VD,on VB )

IR1
ID1

VB +

Slope = 1/R2

R1 +R2
R1

(VD,on VB )

(VD,on VB ) /R1
Slope = 1/ (R1 + R2 )

Vin (V)

3.27 (a)
0
R2
R1 +R2

(Vin VD,on )

Vin < VD,on

Vin > VD,on

Vout (V)

Vout =

Slope = R2 / (R1 + R2 )

VD,on
Vin (V)
(b)

Vout

VD,on
2
= R1R+R
Vin
2

Vin VD,on

2
VD,on
Vin < R1R+R
2
R1 +R2
R2 VD,on < Vin <
2
Vin > R1R+R
VD,on
1

R1 +R2
R1 VD,on

Vout (V)

Slope = 1

R2
V
R1 D,on

Slope = R2 / (R1 + R2 )

2
VD,on
R1R+R
2

R1 +R2
VD,on
R1

Vin (V)
VD,on
(c)
R2
R1 +R2

(Vin + VD,on ) VD,on

Vin

Vin < VD,on

Vin > VD,on

Vout (V)

Vout =

Slope = 1

VD,on
VD,on
Slope = R2 / (R1 + R2 )

Vin (V)

(d)
0
R2
R1 +R2

(Vin VD,on )

Vin < VD,on

Vin > VD,on

Vout (V)

Vout =

Slope = R2 / (R1 + R2 )

VD,on

VD,on
Vin (V)
(e)
Vout =

R2
R1 +R2

(Vin + VD,on ) Vin < VD,on

Vin > VD,on

Vout (V)
VD,on
Vin (V)

Slope = R2 / (R1 + R2 )

3.28 (a)
IR1 =

ID1 =

Vin VD,on
R1 +R2

Vin VD,on
R1 +R2

Vin < VD,on

Vin > VD,on
Vin < VD,on
Vin > VD,on

IR1
ID1
Slope = 1/ (R1 + R2 )

VD,on
Vin (V)
(b)

IR1 =

ID1

V +V
in
D,on

R1
Vin
R1 +R2

VD,on
R1

0
= 0

Vin VD,on
R2

2
Vin < R1R+R
VD,on
2
R1 +R2
R2 VD,on < Vin <
2
Vin > R1R+R
VD,on
1

VD,on
R1

R1 +R2
R1 VD,on

2
VD,on
Vin < R1R+R
2
R1 +R2
R2 VD,on < Vin <
2
Vin > R1R+R
VD,on
1

R1 +R2
R1 VD,on

IR1
ID1

VD,on /R1
Slope = 1/ (R1 + R2 )
Slope = 1
R1 +R2
VD,on
R1

2
VD,on
R1R+R
2
VD,on /R2

Vin (V)

Slope = 1/R1

(c)
IR1 =

ID1 =

0 Vin < VD,on

0 Vin > VD,on

Vin +VD,on
R1 +R2

Vin < VD,on

Vin > VD,on

IR1
ID1

VD,on
Vin (V)

Slope = 1/ (R1 + R2 )

(d)
IR1 =

ID1 =

Vin VD,on
R1 +R2

Vin VD,on
R1 +R2

Vin < VD,on

Vin > VD,on
Vin < VD,on
Vin > VD,on

IR1
ID1
Slope = 1/ (R1 + R2 )

VD,on
Vin (V)
(e)
IR1 =

ID1 =

0 Vin < VD,on

0 Vin > VD,on

Vin +VD,on
R1 +R2

Vin < VD,on

Vin > VD,on

IR1
ID1

VD,on
Vin (V)

Slope = 1/ (R1 + R2 )

3.29 (a)

Vout (V)

Vout

Vin < VD,on

Vin
2
2
= VD,on + R1R+R
(V

V
)
VD,on < Vin < VD,on + R1R+R
(VD,on + VB )
in
D,on
2
1

R1 +R2
Vin VD,on VB
Vin > VD,on + R1 (VD,on + VB )

Slope = 1

VD,on +

R2
R1

(VD,on + VB )

Slope = R2 / (R1 + R2 )

VD,on
Slope = 1

VD,on

VD,on +

R1 +R2
R1

(VD,on + VB )
Vin (V)

(b)
Vout =

Vin + VD,on VB
R2
R1 +R2 (Vin VD,on )

Vin < VD,on +

Vin > VD,on +

R1 +R2
R1
R1 +R2
R1

(VB 2VD,on )
(VB 2VD,on )

Vout (V)

Slope = R2 / (R1 + R2 )

R2
R1

(VB 2VD,on )
VD,on +

R1 +R2
R1

(VB 2VD,on )
Vin (V)

Slope = 1

(c)

Vout (V)

Vout =

Vin
VD,on + VB

Vin < VD,on + VB

Vin > VD,on + VB

VD,on + VB

VD,on + VB
Vin (V)

Slope = 1

(d)

Vout (V)

Vout =

Vin < VD,on

2
(Vin VD,on ) VD,on < Vin < VD,on + R1R+R
(VB + VD,on )
2

R1 +R2
VD,on + VB
Vin > VD,on + R2 (VB + VD,on )
R2
R1 +R2

VD,on + VB

Slope = R2 / (R1 + R2 )

VD,on

VD,on +

R1 +R2
R2

(VB + VD,on )
Vin (V)

3.30 (a)

IR1 =

ID1 =

Vin VD,on
R1 +R2

VD,on
+VB
R1

Vin < VD,on

2
VD,on < Vin < VD,on + R1R+R
(VD,on + VB )
1
R1 +R2
Vin > VD,on + R1 (VD,on + VB )

Vin 2VD,on VB
R2

VD,on +VB
R1

Vin < VD,on +

Vin > VD,on +

R1 +R2
R1
R1 +R2
R1

(VD,on + VB )
(VD,on + VB )

IR1
ID1
VD,on + VB

Slope = 1/ (R1 + R2 )

Slope = 1/R2

VD,on

VD,on +

R1 +R2
R1

(VD,on + VB )
Vin (V)

(b) If VB < 2VD,on :

IR1 = ID1 =

0
Vin VD,on
R1 +R2

Vin < VD,on

Vin > VD,on

IR1
ID1
Slope = 1/ (R1 + R2 )

VD,on
Vin (V)
If VB > 2VD,on :
IR1 = ID1 =

VB 2VD,on
R1
Vin VD,on
R1 +R2

Vin < VD,on +

Vin > VD,on +

R1 +R2
R1
R1 +R2
R1

(VB 2VD,on )
(VB 2VD,on )

IR1
ID1
Slope = 1/ (R1 + R2 )

VB 2VD,on
R1

VD,on +

R1 +R2
R1

(VB 2VD,on )
Vin (V)

(c)
IR1 =

ID1

0
Vin VD,on VB
R1

0
= 0

Vin 2VD,on VB
R2

Vin < VD,on + VB

Vin > VD,on + VB
Vin < VD,on + VB
VD,on + VB < Vin < 2VD,on + VB
Vin > 2VD,on + VB

IR1
ID1

Slope = 1/R1

Slope = 1/R2

VD,on + VB 2VD,on + VB
Vin (V)
(d)

IR1 =

Vin < VD,on

2
VD,on < Vin < VD,on + R1R+R
(VB + VD,on )
2
R1 +R2
Vin > VD,on + R2 (VB + VD,on )

ID1 =

Vin < VD,on

2
VD,on < Vin < VD,on + R1R+R
(VB + VD,on )
2
R1 +R2
Vin > VD,on + R2 (VB + VD,on )

Vin VD,on
R1 +R2

Vin 2V
D,on VB
R1
Vin VD,on
R1 +R2

Vin 2V
D,on VB
R1

IR1
ID1

Slope = 1/R2

VB +VD,on
R2

Slope = 1/ (R1 + R2 )

VD,on

VD,on +

R1 +R2
R2

(VB + VD,on )
Vin (V)

3.31 (a)
Vin VD,on
= 1.6 mA
R1
VT
=
= 16.25
ID1
R1
=
Vin = 98.40 mV
rd + R1

ID1 =
rd1
Vout
(b)

Vin 2VD,on
= 0.8 mA
R1
VT
= rd2 =
= 32.5
ID1
R1 + rd2
=
Vin = 96.95 mV
R1 + rd1 + rd2

ID1 = ID2 =
rd1
Vout
(c)

Vin 2VD,on
= 0.8 mA
R1
VT
= rd2 =
= 32.5
ID1
rd2
Vin = 3.05 mV
=
rd1 + R1 + rd2

ID1 = ID2 =
rd1
Vout
(d)

Vin VD,on
VD,on

= 1.2 mA
R1
R2
VT
=
= 21.67
ID2
R2 k rd2
=
Vin = 2.10 mV
R1 + R2 k rd2

ID2 =
rd2
Vout

3.32 (a)
Vout = Iin R1 = 100 mV
(b)
ID1 = ID2 = Iin = 3 mA
VT
rd1 = rd2 =
= 8.67
ID1
Vout = Iin (R1 + rd2 ) = 100.867 mV
(c)
ID1 = ID2 = Iin = 3 mA
VT
rd1 = rd2 =
= 8.67
ID1
Vout = Iin rd2 = 0.867 mV
(d)
ID2 = Iin
rd2 =

VD,on
= 2.6 mA
R2

VT
= 10
ID2

Vout = Iin (R2 k rd2 ) = 0.995 mV

3.34

Vin (t)
Vout (t)
Vp
Vp VD,on

VD,on + 0.5 V
0.5 V
/

2/
t

Vp

3.35

Vin (t)
Vout (t)
Vp

0.5 V
VD,on + 0.5 V

2/
t

Vp + VD,on
Vp

3.36
Vp VD,on
RL C1 fin
Vp = 3.5 V

VR

RL = 100
C1 = 1000 F
fin = 60 Hz
VR = 0.45 V

3.37
IL
300 mV
C1 fin
= 60 Hz

VR =
fin

IL = 0.5 A
C1

IL
= 27.78 mF
(300 mV) fin

3.38 Shorting the input and output grounds of a full-wave rectifier shorts out the diode D4 from Fig. 3.38(b).
Redrawing the modified circuit, we have:
D3
+
Vin

+
D2

RL

Vout

D1

On the positive half-cycle, D3 turns on and forms a half-wave rectifier along with RL (and CL , if
included). On the negative half-cycle, D2 shorts the input (which could cause a dangerously large
current to flow) and the output remains at zero. Thus, the circuit behaves like a half-wave recifier.
The plots of Vout (t) are shown below.

Vin (t) = V0 sin(t)

Vout (t) (without a load capacitor)
Vout (t) (with a load capacitor)
V0
V0 VD,on

VD,on
/

2/
t

V0

3.39 Note that the waveforms for VD1 and VD2 are identical, as are the waveforms for VD3 and VD4 .

Vin (t) = V0 sin(t)

Vout (t)
VD1 (t), VD2 (t)
VD3 (t), VD4 (t)
V0

V0 2VD,on

2VD,on
VD,on
/
VD,on
2VD,on

V0 + 2VD,on
V0 + VD,on
V0

2/
t

3.40 During the positive half-cycle, D2 and D3 will remain reverse-biased, causing Vout to be zero as
no current will flow through RL . During the negative half-cycle, D1 and D3 will short the input
(potentially causing damage to the devices), and once again, no current will flow through RL (even
though D2 will turn on, there will be no voltage drop across RL ). Thus, Vout always remains at zero,
and the circuit fails to act as a rectifier.

3.42 Shorting the negative terminals of Vin and Vout of a full-wave rectifier shorts out the diode D4 from
Fig. 3.38(b). Redrawing the modified circuit, we have:
D3
+
D2

Vin

RL

+
Vout

D1

On the positive half-cycle, D3 turns on and forms a half-wave rectifier along with RL (and CL , if
included). On the negative half-cycle, D2 shorts the input (which could cause a dangerously large
current to flow) and the output remains at zero. Thus, the circuit behaves like a half-wave recifier.
The plots of Vout (t) are shown below.

Vin (t) = V0 sin(t)

Vout (t) (without a load capacitor)
Vout (t) (with a load capacitor)
V0

2/
t

V0

3.44 (a) We know that when a capacitor is discharged by a constant current at a certain frequency, the
ripple voltage is given by CfIin , where I is the constant current. In this case, we can calculate the
V 5V

current as approximately p R1D,on (since Vp 5VD,on is the voltage drop across R1 , assuming
R1 carries a constant current). This gives us the following:
1 Vp 5VD,on
2 RL C1 fin
Vp = 5 V

VR

RL = 1 k
C1 = 100 F
fin = 60 Hz
VR = 166.67 mV
(b) The bias current through the diodes is the same as the bias current through R1 , which is
Vp 5VD,on
= 1 mA. Thus, we have:
R1
VT
= 26
ID
3rd
=
VR = 12.06 mV
R1 + 3rd

rd =
VR,load

3.45
ID1 =

ID2 =

Vin +VD,on +VB2

R1

Vin VD,on VB1

R1

Vin < VD,on + VB1

Vin > VD,on + VB1
Vin < VD,on VB2
Vin > VD,on VB2

Vin (t)
ID1 (t)
ID2 (t)
V0

V0 VB1 VD,on
R1

V0 +VB1 +VD,on
R1

VD,on VB2

V0
/

0
t

ID1 (t) and ID2 (t)

Vin (t)

VD,on + VB1

4.4 According to Equation (4.8), we have

AE qDn n2i VBE /VT
1
e
NB WB
1

WB

IC =

We can see that if WB increases by a factor of two, then IC decreases by a factor of two .

4.11
VBE = 1.5 V IE (1 k)
1.5 V IC (1 k) (assuming 1)

IC
= VT ln
IS
IC = 775 A
VX IC (1 k)
= 775 mV

4.12 Since we have only integer multiples of a unit transistor, we need to find the largest number that
divides both I1 and I2 evenly (i.e., we need to find the largest x such that I1 /x and I2 /x are integers).
This will ensure that we use the fewest transistors possible. In this case, its easy to see that we should
pick x = 0.5 mA, meaning each transistor should have 0.5 mA flowing through it. Therefore, I1 should
be made up of 1 mA/0.5 mA = 2 parallel transistors, and I2 should be made up of 1.5 mA/0.5 mA = 3
parallel transistors. This is shown in the following circuit diagram.
I1

VB

I2

Now we have to pick VB so that IC = 0.5 mA for each transistor.

IC
VB = VT ln
IS


5 104 A
= (26 mV) ln
3 1016 A
= 732 mV

4.15
VB VBE
= IB
R1
IC
=

[VB VT ln(IC /IS )]

IC =
R1
IC = 786 A

4.17 First, note that VBE1 = VBE2 = VBE .

VB = (IB1 + IB2 )R1 + VBE
R1
=
(IX + IY ) + VT ln(IX /IS1 )

5
IS2 = IS1
3
5
IY = IX
3
8R1
VB =
IX + VT ln(IX /IS1 )
3
IX = 509 A
IY = 848 A

4.21 (a)
VBE = 0.8 V
IC = IS eVBE /VT
= 18.5 mA
VCE = VCC IC RC
= 1.58 V
Q1 is operating in forward active. Its small-signal parameters are
gm = IC /VT = 710 mS
r = /gm = 141
ro =
The small-signal model is shown below.
B

C
+
r

gm v

(b)
IB = 10 A
IC = IB = 1 mA
VBE = VT ln(IC /IS ) = 724 mV
VCE = VCC IC RC
= 1.5 V
Q1 is operating in forward active. Its small-signal parameters are
gm = IC /VT = 38.5 mS
r = /gm = 2.6 k
ro =
The small-signal model is shown below.
B

C
+
r

gm v

(c)
VCC VBE
1+
=
IC
RC

VCC VT ln(IC /IS )

IC =
1+
RC

IE =

IC = 1.74 mA
VBE = VT ln(IC /IS ) = 739 mV
VCE = VBE = 739 mV
Q1 is operating in forward active. Its small-signal parameters are
gm = IC /VT = 38.5 mS
r = /gm = 2.6 k
ro =
The small-signal model is shown below.
B

C
+
r

gm v

4.22 (a)
IB = 10 A
IC = IB = 1 mA
VBE = VT ln(IC /IS ) = 739 mV
VCE = VCC IE (1 k)
1+
(1 k)
= VCC

= 0.99 V
Q1 is operating in forward active. Its small-signal parameters are
gm = IC /VT = 38.5 mS
r = /gm = 2.6 k
ro =
The small-signal model is shown below.
B

C
+
r

gm v

(b)
1+
VCC VBE
=
IC
1 k

VCC VT ln(IC /IS )

IC =
1+
1 k

IE =

IC = 1.26 mA
VBE = VT ln(IC /IS ) = 730 mV
VCE = VBE = 730 mV
Q1 is operating in forward active. Its small-signal parameters are
gm = IC /VT = 48.3 mS
r = /gm = 2.07 k
ro =
The small-signal model is shown below.

C
+
r

gm v

(c)
IE = 1 mA

IC =
IE = 0.99 mA
1+
VBE = VT ln(IC /IS ) = 724 mV
VCE = VBE = 724 mV
Q1 is operating in forward active. Its small-signal parameters are
gm = IC /VT = 38.1 mS
r = /gm = 2.63 k
ro =
The small-signal model is shown below.
B

C
+
r

gm v

(d)
IE = 1 mA

IC =
IE = 0.99 mA
1+
VBE = VT ln(IC /IS ) = 724 mV
VCE = VBE = 724 mV
Q1 is operating in forward active. Its small-signal parameters are
gm = IC /VT = 38.1 mS
r = /gm = 2.63 k
ro =
The small-signal model is shown below.

C
+
r

gm v

4.31
IC = IS eVBE /VT

VCE
1+
VA

IC,T otal = nIC

= nIS eVBE /VT

1+

VCE
VA

IC
VBE
IS
= n eVBE /VT
VT
IC
n
VT
= ngm

gm,T otal =

IB,T otal
r,T otal

ro,T otal

= n 0.4435 S
1
= IC,T otal

1

IB,T otal
=
VBE

1
IC,T otal

VT
1

nIC
=
VT
r
=
n
225.5
=
(assuming = 100)
n

1
IC,T otal
=
VCE
1

IC,T otal

VA
VA
=
nIC
ro
=
n
693.8
=
n

The small-signal model is shown below.

B

C
+

r,T otal

gm,T otal v

ro,T otal

4.32 (a)
VBE = VCE (for Q1 to operate at the edge of saturation)
VT ln(IC /IS ) = VCC IC RC
IC = 885.7 A
VB = VBE = 728.5 mV

(b) Let IC , VB , VBE

, and VCE
correspond to the values where the collector-base junction is forward
biased by 200 mV.

VBE
= VCE
+ 200 mV

VT ln(IC /IS ) = VCC IC RC + 200 mV

IC = 984.4 A
VB = 731.3 mV
Thus, VB can increase by VB VB = 2.8 mV if we allow soft saturation.

4.34
VBE = VCC IB RB
VT ln(IC /IS ) = VCC IC RB /
IC = 1.67 mA
VBC = VCC IB RB (VCC IC RC )
< 200 mV
IC RC IB RB < 200 mV
200 mV + IB RB
RC <
IC
200 mV + IC RB /
=
IC
RC < 1.12 k

4.41

VCC

VEB = VEC (for Q1 to operate at the edge of saturation)

IB RB = VCC IC RC
IC RB / = IC RC
RB / = RC
= RB /RC
= 100

4.44 (a)
IB = 2 A
IC = IB
= 200 A
VEB = VT ln(IC /IS )
= 768 mV
VEC = VCC IE (2 k)
1+
= VCC
IC (2 k)

= 2.1 V
Q1 is operating in forward active. Its small-signal parameters are
gm = IC /VT = 7.69 mS
r = /gm = 13 k
ro =
The small-signal model is shown below.
B

C
+
r

gm v

(b)
IE =

VCC VEB
5 k

VCC VT ln(IC /IS )

1+
IC =

5 k
IC = 340 A
VEB = 782 mV
VEC = VEB = 782 mV
Q1 is operating in forward active. Its small-signal parameters are
gm = IC /VT = 13.1 mS
r = /gm = 7.64 k
ro =
The small-signal model is shown below.

C
+
r

gm v

(c)
IE =

1+
IC = 0.5 mA

IC = 495 A
VEB = 971 mV
VEC = VEB = 971 mV
Q1 is operating in forward active. Its small-signal parameters are
gm = IC /VT = 19.0 mS
r = /gm = 5.25 k
ro =
The small-signal model is shown below.
B

C
+
r

gm v

4.49 The direction of current flow in the large-signal model (Fig. 4.40) indicates the direction of positive
current flow when the transistor is properly biased.
The direction of current flow in the small-signal model (Fig. 4.43) indicates the direction of positive
change in current flow when the base-emitter voltage vbe increases. For example, when vbe increases,
the current flowing into the collector increases, which is why ic is shown flowing into the collector in
Fig. 4.43. Similar reasoning can be applied to the direction of flow of ib and ie in Fig. 4.43.

4.53 (a)
VCB2 < 200 mV
IC2 RC < 200 mV
IC2 < 400 A
VEB2 = VE2
= VT ln(IC2 /IS2 )
< 741 mV
2
IE2 RC
1 + 2
2 1 + 1
IC1 RC
1 + 2 1
IC1
VBE1
Vin

< 200 mV
< 200 mV
< 396 A
= VT ln(IC1 /IS1 )
< 712 mV
= VBE1 + VEB2
< 1.453 V

(b)
IC1 = 396 A
IC2 = 400 A
gm1 = 15.2 mS
r1 = 6.56 k
ro1 =
gm2 = 15.4 mS
r2 = 3.25 k
ro2 =
The small-signal model is shown below.
+
vin

r1

B1
+
v1

C1
gm1 v1

E1 /E2

r2

v2
+
B2

gm2 v2
vout

C2
RC

4.55 (a)

VBE2 (VCC

VBC2 < 200 mV

IC2 RC ) < 200 mV

VT ln(IC2 /IS2 ) + IC2 RC VCC < 200 mV

IC2 < 3.80 mA
VBE2 < 799.7 mV
1 + 1
IC1 = IB2 = IC2 /2
IE1 =
1
IC1 < 75.3 A
VBE1 < 669.2 mV
Vin = VBE1 + VBE2
< 1.469 V
(b)
IC1 = 75.3 A
IC2 = 3.80 mA
gm1 = 2.90 mS
r1 = 34.5 k
ro1 =
gm2 = 146.2 mS
r2 = 342
ro2 =
The small-signal model is shown below.
B1
+

+
vin

r1

C1
gm1 v1

v1

E1 /B2

C2

vout

+
r2

gm2 v2

v2

E2

RC

5.3 (a) Looking into the base of Q1 we see an equivalent resistance of r1 , so we can draw the following
equivalent circuit for finding Rin :
R1

R2

r1

Rin

Rin = R1 + R2 k r1
(b) Looking into the emitter of Q1 we see an equivalent resistance of
following equivalent circuit for finding Rin :

1
gm1

R1

1
gm1

k r1 , so we can draw the

k r1

Rin

Rin = R1 k

1
k r1
gm1

(c) Looking down from the emitter of Q1 we see an equivalent resistance of

the following equivalent circuit for finding Rin :

1
gm2

k r2 , so we can draw

VCC
Q1

Rin

1
gm2

Rin = r1 + (1 + 1 )

k r2

1
gm2

k r2

(d) Looking into the base of Q2 we see an equivalent resistance of r2 , so we can draw the following
equivalent circuit for finding Rin :

VCC
Q1

Rin

r2

Rin = r1 + (1 + 1 )r2

5.4 (a) Looking into the collector of Q1 we see an equivalent resistance of ro1 , so we can draw the following
equivalent circuit for finding Rout :

ro1

R1
Rout

Rout = ro1 k R1
(b) Lets draw the small-signal model and apply a test source at the output.
RB
+
r1

v1

+
gm1 v1

ro1

it

vt

it = gm1 v1 +

vt
ro1

v1 = 0
vt
it =
ro1
vt
Rout =
= ro1
it
(c) Looking down from the emitter of Q1 we see an equivalent resistance of
can draw the following equivalent circuit for finding Rout :
Rout

Q1

1
gm2

k r2 k ro2

1
k r2 k ro2
Rout = ro1 + (1 + gm1 ro1 ) r1 k
gm2

1
gm2

k r2 k ro2 , so we

(d) Looking into the base of Q2 we see an equivalent resistance of r2 , so we can draw the following
equivalent circuit for finding Rout :
Rout

Q1

r2

Rout = ro1 + (1 + gm1 ro1 ) (r1 k r2 )

5.5 (a) Looking into the base of Q1 we see an equivalent resistance of r1 , so we can draw the following
equivalent circuit for finding Rin :
R1

R2

r1

Rin

Rin = R1 + R2 k r1
(b) Lets draw the small-signal model and apply a test source at the input.
+
r1

gm1 v1

v1

R1

+
it

vt

v1
gm1 v1
r1
v1 = vt
vt
+ gm1 vt
it =
r1


1
it = vt gm1 +
r1
it =

Rin =

vt
1
=
k r1
it
gm1

(c) From our analysis in part (b), we know that looking into the emitter we see a resistance of
1
gm2 k r2 . Thus, we can draw the following equivalent circuit for finding Rin :

VCC
Q1

Rin

1
gm2

Rin = r1 + (1 + 1 )

k r2

1
gm2

k r2

(d) Looking up from the emitter of Q1 we see an equivalent resistance of

the following equivalent circuit for finding Rin :

1
gm2

k r2 , so we can draw

VCC
1
gm2

k r2

Q1

Rin

Rin = r1 + (1 + 1 )

1
gm2

k r2

(e) We know that looking into the base of Q2 we see Rin = r2 if the emitter is grounded. Thus,
transistor Q1 does not affect the input impedance of this circuit.

5.6 (a) Looking into the collector of Q1 we see an equivalent resistance of ro1 , so we can draw the following
equivalent circuit for finding Rout :

ro1

RC
Rout

Rout = RC k ro1
(b) Looking into the emitter of Q2 we see an equivalent resistance of
the following equivalent circuit for finding Rout :

1
gm2

k r2 k ro2 , so we can draw

Rout

Q1

RE =

1
gm2

k r2 k ro2

1
Rout = ro1 + (1 + gm1 ro1 ) r1 k
k r2 k ro2
gm2

5.7 (a)
VCC IB (100 k) = VBE = VT ln(IC /IS )
1
VCC IC (100 k) = VT ln(IC /IS )

IC = 1.754 mA
VBE = VT ln(IC /IS ) = 746 mV
VCE = VCC IC (500 ) = 1.62 V
Q1 is operating in forward active.
(b)
IE1 = IE2 VBE1 = VBE2
VCC IB1 (100 k) = 2VBE1
1
VCC IC1 (100 k) = 2VT ln(IC1 /IS )

IC1 = IC2 = 1.035 mA

VBE1 = VBE2 = 733 mV
VCE2 = VBE2 = 733 mV
VCE1 = VCC IC (1 k) VCE2
= 733 mV
Both Q1 and Q2 are at the edge of saturation.
(c)
VCC IB (100 k) = VBE + 0.5 V
1
VCC IC (100 k) = VT ln(IC /IS ) + 0.5 V

IC = 1.262 mA
VBE = 738 mV
VCE = VCC IC (1 k) 0.5 V
= 738 mV
Q1 is operating at the edge of saturation.

5.8 See Problem 7 for the derivation of IC for each part of this problem.
(a)
IC1 = 1.754 mA
gm1 = IC1 /VT = 67.5 mS
r1 = /gm1 = 1.482 k
100 k
+
r1

v1

gm1 v1

500

(b)
IC1 = IC2 = 1.034 mA
gm1 = gm2 = IC1 /VT = 39.8 mS
r1 = r2 = /gm1 = 2.515 k
100 k
+
r1

v1

gm1 v1

1 k

+
r2

v2

gm2 v2

(c)
IC1 = 1.26 mA
gm1 = IC1 /VT = 48.5 mS
r1 = /gm1 = 2.063 k
100 k
+
r1

v1

gm1 v1

1 k

5.9 (a)
VCC VBE
VBE
IC

= IB =
34 k
16 k

VT ln(IC /IS )
VCC VT ln(IC /IS )

IC =
34 k
16 k
IC = 677 A
VBE = 726 mV
VCE = VCC IC (3 k) = 468 mV
Q1 is in soft saturation.
(b)
IE1 = IE2

VCC 2VBE
9 k

IC1 = IC2
VBE1 = VBE2 = VBE
2VBE
IC1

= IB1 =
16 k

2VT ln(IC1 /IS )

VCC 2VT ln(IC1 /IS )

IC1 =
9 k
16 k
IC1 = IC2 = 1.72 mA
VBE1 = VBE2 = VCE2 = 751 mV
VCE1 = VCC IC1 (500 ) VCE2 = 890 mV

Q1 is in forward active and Q2 is on the edge of saturation.

(c)
IC
VCC VBE 0.5 V VBE + 0.5 V

= IB =
12 k
13 k

VT ln(IC /IS ) + 0.5 V

VCC VT ln(IC /IS ) 0.5 V

IC =
12 k
13 k
IC = 1.01 mA
VBE = 737 mV
VCE = VCC IC (1 k) 0.5 V = 987 mV
Q1 is in forward active.

5.10 See Problem 9 for the derivation of IC for each part of this problem.
(a)
IC = 677 A
gm = IC /VT = 26.0 mS
r = /gm = 3.84 k

+
(34 k) k (16 k)

gm v

3 k

(b)
IC1 = IC2 = 1.72 mA
gm1 = gm2 = IC1 /VT = 66.2 mS
r1 = r2 = /gm1 = 1.51 k

+
(9 k) k (16 k)

r1

v1

gm1 v1

500

+
r2

v2

gm2 v2

(c)
IC = 1.01 mA
gm = IC /VT = 38.8 mS
r = /gm = 2.57 k

(12 k) k (13 k)

+
v

gm v

1 k

5.11 (a)

VCC

VCC

VCE VBE (in order to guarantee operation in the active mode)

IC (2 k) VBE

VCC IC (2 k) VT ln(IC /IS )

IC 886 A
VCC VBE
VBE
IC

= IB =
RB
3 k

VT ln(IC /IS ) VT ln(IC /IS )

IC

=
RB
3 k

VT ln(IC /IS )
IC
= VCC VT ln(IC /IS )
+
RB

3 k
VCC VT ln(IC /IS )
RB = I
VT ln(IC /IS )
C
+
3 k
RB 7.04 k

(b)
VCC VBE
VBE
IC

= IB =
RB
3 k

VT ln(IC /IS )
VCC VT ln(IC /IS )

IC =
RB
3 k
IC = 1.14 mA
VBE = 735 mV
VCE = VCC IC (2 k) = 215 mV
VBC = VBE VCE = 520 mV

5.13 We know the input resistance is Rin = R1 k R2 k r . Since we want the minimum values of R1 and
R2 such that Rin > 10 k, we should pick the maximum value allowable for r , which means picking
the minimum value allowable for gm (since r 1/gm ), which is gm = 1/260 S.
1
S
260
IC = gm VT = 100 A
VBE = VT ln(IC /IS ) = 760 mV
IC
IB =
= 1 A

VBE

= IB
R2
VCC VBE
R1 =
IB + VRBE
2
gm =

VCC VBE
R1

= 26 k
gm
= R1 k R2 k r

r =
Rin

VCC VBE
IB + VRBE
2

> 10 k
R2 > 23.57 k
R1 > 52.32 k

k R2 k r

5.14
IC
1

S
VT
26

r =
= 2.6 k
gm
Rin = R1 k R2 k r
r
gm =

According to the above analysis, Rin cannot be greater than 2.6 k. This means that the requirement
that Rin 10 k cannot be met. Qualitatively, the requirement for gm to be large forces r to be
small, and since Rin is bounded by r , it puts an upper bound on Rin that, in this case, is below the
required 10 k.

5.15
Rout = RC = R0
Av = gm RC = gm R0 =

IC
R0 = A0
VT

A0
VT
R0
VT
R0
r =
=
IC
A0

IC =

VBE = VT ln(IC /IS ) = VT ln

VBE
IC
VCC VBE

= IB =
R1
R2

VCC VBE
R1 = IC
VBE
+ R2

A0 VT
R0 IS

Rin = R1 k R2 k r

0 VT
VCC VT ln A
R0 IS
R

k R2 k 0
=
IC
A0 VT
VT
A
0
+ R2 ln R0 IS

In order to maximize Rin , we can let R2 . This gives us

Rin,max =

VCC VT ln
IC

A0 VT
R0 IS

k R0
A0

5.16 (a)

VBE
VCC VBE IE RE

R1

IC = 0.25 mA
VBE = 696 mV
+ IE RE
IC
= IB =
R2

R1 =

VCC VBE
IC

1+
IC RE

VBE + 1+
IC RE
R2

= 22.74 k
(b) First, consider a 5 % increase in RE .

VCC VBE IE RE
VBE

R1
VCC VT ln(IC /IS )

1+
IC RE

R1

VT ln(IC /IS ) +
R2

RE = 210
+ IE RE
IC
= IB =
R2

1+
IC RE

IC

IC = 243 A
= IB =

IC IC,nom
100 = 2.6 %
IC,nom
Now, consider a 5 % decrease in RE .
RE = 190
IC = 257 A
IC IC,nom
100 = +2.8 %
IC,nom

5.17

VCC
VBE
VCC VBE IE RE

30 k

VCE VBE (in order to guarantee operation in the active mode)

IC RC VT ln(IC /IS )
IC 833 A
IC
+ IE RE
= IB =
R2

VBE + IE RE
R2 = VCC VBE IE RE

30 k
=

VT ln(IC /IS )

IC

+ 1+
IC RE

VCC VT ln(IC /IS ) 1+

IC RE
30 k

R2 20.66 k

IC

5.18 (a) First, note that VBE1 = VBE2 = VBE , but since IS1 = 2IS2 , IC1 = 2IC2 . Also note that
1 = 2 = = 100.
IB1 =

IC1
VBE + (IE1 + IE2 )RE
VCC VBE (IE1 + IE2 )RE

R1
R2

IC1 =

VCC VT ln(IC1 /IS1 )

3 1+
2 IC1 RE

R1

VT ln(IC1 /IS1 ) +

3 1+
2 IC1 RE

R2

IC1 = 707 A
IC2 =

IC1
= 354 A
2

(b) The small-signal model is shown below.

RC

+
R1

R2

r1

v1

+
r2

gm1 v1

v2

RE

We can simplify the small-signal model as follows:

RC

+
R1 k R2

r1 k r2

gm1 v

RE

gm2 v2

gm2 v2

gm1 = IC1 /VT = 27.2 mS

r1 = 1 /gm1 = 3.677 k
gm2 = IC2 /VT = 13.6 mS
r2 = 2 /gm2 = 7.355 k

5.19 (a)

VCC 2VBE1
9 k

IE1 = IE2 VBE1 = VBE2

2VBE1
IC1

= IB1 =
16 k
1
2VT ln(IC1 /IS1 )
VCC 2VT ln(IC1 /IS1 )
1
IC1 = 1
9 k
16 k
IC1 = IC2 = 1.588 mA
VBE1 = VBE2 = VT ln(IC1 /IS1 ) = 754 mV
VCE2 = VBE2 = 754 mV
VCE1 = VCC IC1 (100 ) VCE2 = 1.587 V

(b) The small-signal model is shown below.

(9 k) k (16 k)

r1

+
v1

gm1 v1

100

r2

+
v2

gm2 v2

IC1
= 61.1 mS
VT
1
= 1.637 k
=
gm1

gm1 = gm2 =
r1 = r2

5.22
VCC IE (500 ) IB (20 k) IE (400 ) = VBE
1+
1
VCC
IC (500 + 400 ) IC (20 k) = VT ln(IC /IS )

IC = 1.584 mA
VBE = VT ln(IC /IS ) = 754 mV
VCE = VCC IE (500 ) IE (400 )
1+
IC (500 + 400 ) = 1.060 V
= VCC

Q1 is operating in forward active.

5.23

VCC IE (1 k) IB RB (VCC

VBC 200 mV
IE (1 k) IC (500 )) 200 mV
IC (500 ) IB RB 200 mV
IB RB IC (500 ) 200 mV
VCC IE (1 k) IB RB = VBE = VT ln(IC /IS )

VCC

1+
IC (1 k) IC (500 ) + 200 mV VT ln(IC /IS )

IC 1.29 mA
RB

IC (500 ) 200 mV

34.46 k

IC

5.25 (a)

VCC

IC1 = 1 mA
VCC (IE1 + IE2 )(500 ) = VT ln(IC2 /IS2 )


1+
1+

IC1 +
IC2 (500 ) = VT ln(IC2 /IS2 )

IC2 = 2.42 mA
VB (IE1 + IE2 )(500 ) = VT ln(IC1 /IS1 )


1+
1+
IC1 +
IC2 (500 ) = VT ln(IC1 /IS1 )
VB

VB = 2.68 V
(b) The small-signal model is shown below.

200

r1

+
v1

r2

+
v2

gm1 v1

500

gm1 = IC1 /VT = 38.5 mS

r1 = 1 /gm1 = 2.6 k
gm2 = IC2 /VT = 93.1 mS
r2 = 2 /gm2 = 1.074 k

gm2 v2

5.26 (a)

VCC

VCC IB (60 k) = VEB

1

IC (60 k) = VT ln(IC /IS )

pnp
IC = 1.474 mA
VEB = VT ln(IC /IS ) = 731 mV
VEC = VCC IC (200 ) = 2.205 V

Q1 is operating in forward active.

(b)

VCC VT ln

npn
1 + npn

VCC VBE1 IB2 (80 k) = VEB2

VCC VT ln(IC1 /IS ) IB2 (80 k) = VT ln(IC2 /IS )
npn
IE1
IC1 =
1 + npn
npn
IE2
=
1 + npn
npn
1 + pnp
=

IC2
1 + npn
pnp

1
1 + pnp IC2

IC2 (80 k) = VT ln(IC2 /IS )

pnp
IS
pnp
IC2 = 674 A
VBE2 = VT ln(IC2 /IS ) = 711 mV
IC1 = 680 A
VBE1 = VT ln(IC1 /IS ) = 711 mV
VCE1 = VBE1 = 711 mV
VCE2 = VCC VCE1 IC2 (300 )
= 1.585 V

Q1 is operating on the edge of saturation. Q2 is operating in forward active.

5.27 See Problem 26 for the derivation of IC for each part of this problem.
(a) The small-signal model is shown below.
60 k
+
r

gm v

IC = 1.474 mA
IC
gm =
= 56.7 mS
VT

= 1.764 k
r =
gm
(b) The small-signal model is shown below.
+
r1

v1

gm1 v1

r2

v2

gm2 v2

80 k

300

IC1 = 680 A
IC1
= 26.2 mS
gm1 =
VT
npn
r1 =
= 3.824 k
gm1
IC2 = 674 A
IC2
gm2 =
= 25.9 mS
VT
pnp
r2 =
= 1.929 k
gm2

200

5.30
VCC IC (1 k) = VEC = VEB (in order for Q1 to operate at the edge of saturation)
= VT ln(IC /IS )

VCC VEB
RB

IC = 1.761 mA
VEB = 739 mV
VEB
IC

= IB =
5 k

RB = 9.623 k

First, lets consider when RB is 5 % larger than its nominal value.

RB = 10.104 k
IC
VCC VT ln(IC /IS ) VT ln(IC /IS )

=
RB
5 k

IC = 1.411 mA
VEB = 733 mV
VEC = VCC IC (1 k) = 1.089 V
VCB = 355 mV (the collector-base junction is reverse biased)
Now, lets consider when RB is 5 % smaller than its nominal value.
RB = 9.142 k
IC
VCC VT ln(IC /IS ) VT ln(IC /IS )

=
RB
5 k

IC = 2.160 mA
VEB = 744 mV
VEC = VCC IC (1 k) = 340 mV
VCB = 405 mV (the collector-base junction is forward biased)

5.31
VBC + IC (5 k) VCC VBC IC (5 k)
IC

= IB =
10 k
10 k

VBC = 300 mV
IC = 194 A

VCC

VEB = VT ln(IC /IS ) = 682 mV

VCC IE RE IC (5 k) = VEC = VEB + 300 mV
1+

IC RE IC (5 k) = VEB + 300 mV

RE = 2.776 k

Lets look at what happens when RE is halved.

RE = 1.388 k

VCC

VCC IE RE VEB
VCC (VCC IE RE VEB )
IC

= IB =
10 k
10 k

1+
VCC VCC IC RE VT ln(IC /IS )
1+
IC RE VT ln(IC /IS )

= IC
10 k
10 k
IC = 364 A
VEB = 698 V
VEC = 164 V

Thus, when RE is halved, Q1 operates in deep saturation.

5.32

VCC

VCC IB (20 k) IE (1.6 k) = VBE = VT ln(IC /IS )

IC
1+

(20 k)
IC (1.6 k) = VBE = VT ln(IC /IS )

IC
i
IS = h
I
VCC C (20 k) 1+
IC (1.6 k) /VT
e
IC = 1 mA
IS = 3 1014 A

5.38 (a)
Av = gm1

1
gm2

k r2

Rin = r1
Rout =

1
k r2
gm2

(b)


1
Av = gm1 R1 +
k r2
gm2
Rin = r1
Rout = R1 +

1
k r2
gm2

(c)


1
k r2
Av = gm1 RC +
gm2
Rin = r1
Rout = RC +

1
k r2
gm2

(d) Lets determine the equivalent resistance seen looking up from the output by drawing a smallsignal model and applying a test source.
RC
+
vt

+
it

r2

gm2 v2

v2

v2
+ gm2 v2
r2
v2 = vt


1
it = vt
+ gm2
r2
1
vt
=
k r2
it
gm2
it =

Av = gm1

1
gm2

Rin = r1
Rout =

1
k r2
gm2

k r2

1
k r2 . If we find
(e) From (d), we know the gain from the input to the collector of Q1 is gm1 gm2
the gain from the collector of Q1 to vout , we can multiply these expressions to find the overall
gain. Lets draw the small-signal model to find the gain from the collector of Q1 to vout . Ill refer
to the collector of Q1 as node X in the following derivation.
RC
+
vX

r2

vout

+
v2

gm2 v2

vX vout
= gm2 v2
RC
v2 = vX
vX vout
= gm2 vX
RC


vout
1
gm2 =
vX
RC
RC
vout
= 1 gm2 RC
vX
Thus, we have
Av = gm1

1
gm2

k r2 (1 gm2 RC )

Rin = r1
To find the output resistance, lets draw the small-signal model and apply a test source at the
output. Note that looking into the collector of Q1 we see infinite resistance, so we can exclude it
from the small-signal model.
RC
+
r2

v2

+
gm2 v2

it

vt

it = gm2 v2 +

v2
r2

r2
vt
r2 + RC


r2
1
vt
it = gm2 +
r2 r2 + RC
vt
Rout =
it


r2 + RC
1
=
k r2
gm2
r2
v2 =

5.39 (a)


1
Av = gm1 ro1 k
k r2 k ro2
gm2
Rin = r1
Rout = ro1 k

1
k r2 k ro2
gm2

(b)



1
k r2 k ro2
Av = gm1 ro1 k R1 +
gm2
Rin = r1
Rout = ro1 k

1
R1 +
k r2 k ro2
gm2

(c)

Av = gm1 ro1

1
k RC +
k r2 k ro2
gm2

Rin = r1
Rout = ro1

1
k r2 k ro2
k RC +
gm2

(d) Lets determine the equivalent resistance seen looking up from the output by drawing a smallsignal model and applying a test source.
RC
+
vt

+
it

r2

v2

gm2 v2

ro2

it =

v2
vt vX
+
r2
RC

vX
vX vt
+ gm2 v2 +
=0
RC
ro2
v2 = vt




1
1
1
vX
= vt
+
gm2
RC
ro2
RC


1
vX = vt
gm2 (ro2 k RC )
RC


1
vt
1
vt
+

vt
gm2 (ro2 k RC )
it =
r2
RC
RC
RC




1
1
1
1
= vt
+

gm2 (ro2 k RC )
r2
RC
RC RC




1
1
ro2
1
+
+ gm2
= vt
r2
RC
RC ro2 + RC
#
"
vt
1
ro2 + RC
= r2 k RC k
it
ro2
gm2 R1C

Av = gm1 ro1 k r2

"

1
ro2 + RC
k RC k
ro2
gm2

1
RC

#!

Rin = r1
Rout = ro1 k r2

"

ro2 + RC
1
k RC k
ro2
gm2

1
RC

C
(e) From (d), we know the gain from the input to the collector of Q1 is gm1 ro1 k r2 k RC k ro2r+R
o2
If we find the gain from the collector of Q1 to vout , we can multiply these expressions to find the
overall gain. Lets draw the small-signal model to find the gain from the collector of Q1 to vout .
Ill refer to the collector of Q1 as node X in the following derivation.
RC
+
vX

r2

+
v2

vout
gm2 v2

ro2

1
gm2 R1

.

vout vX
vout
+ gm2 v2 +
=0
RC
ro2
v2 = vX
vout vX
vout
+ gm2 vX +
=0
RC
ro2




1
1
1
= vX
+
gm2
vout
RC
ro2
RC


vout
1
=
gm2 (RC k ro2 )
vX
RC
Thus, we have
Av = gm1 ro1 k r2

"

ro2 + RC
1
k RC k
ro2
gm2

1
RC

#!

1
gm2 (RC k ro2 )
RC

Rin = r1
To find the output resistance, lets draw the small-signal model and apply a test source at the
output. Note that looking into the collector of Q1 we see ro1 , so we replace Q1 in the small-signal
model with this equivalent resistance. Also note that ro2 appears from the output to ground, so
we can remove it from this analysis and add it in parallel at the end to find Rout .
RC
+

+
ro1

r2

v2

it = gm2 v2 +

gm2 v2

vt

it

v2
r2 k ro1

r2 k ro1
vt
r2 k ro1 + RC


1
r2 k ro1
it = gm2 +
vt
r2 k ro1 r2 k ro1 + RC
vt
Rout = ro2 k
it



r2 k ro1 + RC
1
= ro2 k
k r2 k ro1
gm2
r2 k ro1
v2 =

5.43
Av =

1
gm

= VT
IC

RC
+ (200 )
RC
+ (200 )

= 100
VT
RC = 100
+ 100(200 )
IC
IC RC IE (200 ) = VCE = VBE = VT ln(IC /IS )


1+
VT
+ 100(200 )
IC (200 ) = VT ln(IC /IS )
IC 100
IC

We can see that this equation has no solution. For example, if we let IC = 0, we see that according to
the left side, we should have VBE = 2.6 V, which is clearly an infeasible value. Qualitatively, we know
that in order to achieve a large gain, we need a large value for RC . However, increasing RC will result
in a smaller value of VCE , eventually driving the transistor into saturation. When Av = 100, there
is no value of RC that will provide such a large gain without driving the transistor into saturation.

5.46 (a)
Av =

R1 +

1
gm2

1
gm1

k r2

+ RE

Rin = r1 + (1 + 1 )RE
Rout = R1 +

1
k r2
gm2

(b)
RC

Av =

1
gm1

1
gm2

k r2

Rin = r1 + (1 + 1 )

1
gm2

k r2

k r2

Rout = RC
(c)
RC

Av =

1
gm1

1
gm2

k r2

Rin = r1 + (1 + 1 )

1
gm2

Rout = RC
(d)
Av =

1
gm1

RC
gm2 k r2 +
1

Rin = RB + r1 + (1 + 1 )

RB
1+1

1
gm2

k r2

k r2

Rout = RC
(e)
Av =

1
gm1

RC
gm2 k r2 +
1

Rin = RB + r1 + (1 + 1 )
Rout = RC

RB
1+1

1
gm2

5.47 (a)
Av =

RC +

1
gm2

1
gm1

k r2

+ RE

Rin = r1 + (1 + 1 ) RE
Rout = RC +

1
k r2
gm2

(b)
Av =

1
gm2

RC +
1
gm1

1
gm2
1
gm1

k r2

+ RE

1
gm2

RC +

k r2

1
gm2

k r2

k r2
+ RE

Rin = r1 + (1 + 1 ) RE
Rout =

1
k r2
gm2

(c)
Av =

RC +
1

1
gm2

gm1

k r2

1
gm3 kr3

Rin = r1 + (1 + 1 )
Rout = RC +

1
gm2

1
gm3 k r3

k r2

(d)
Av =

RC k r2
1
gm1 + RE

Rin = r1 + (1 + 1 ) RE
Rout = RC k r2

5.49 (a) Looking into the emitter of Q2 we see an equivalent resistance of

the following equivalent circuit for finding Rout :

1
gm2

k r2 k ro2 , so we can draw

Rout

Q1

1
gm2

Rout

k r2 k ro2

1
= ro1 + (1 + gm1 ro1 ) r1 k
k r2 k ro2
gm2

+RB
(b) Looking into the emitter of Q2 we see an equivalent resistance of ro2 k r2
1+2 (ro2 simply appears
in parallel with the resistance seen when VA = ), so we can draw the following equivalent circuit
for finding Rout :

Rout

Q1

ro2 k

r2 +RB
1+2

Rout = ro1 + (1 + gm1 ro1 ) r1 k ro2

r2 + RB
k
1 + 2

(c) Looking down from the emitter of Q1 we see an equivalent resistance of R1 k r2 , so we can draw
the following equivalent circuit for finding Rout :

Rout

Q1

R1 k r2

Rout = ro1 + (1 + gm1 ro1 ) (r1 k R1 k r2 )

5.50 (a) Looking into the emitter of Q1 we see an equivalent resistance of

the following equivalent circuit for finding Rout :

1
gm1

k r1 k ro1 , so we can draw

VCC
1
gm1

k r1 k ro1

Q2

Rout

1
k r1 k ro1
Rout = ro2 + (1 + gm2 ro2 ) r2 k
gm1
(b) Looking into the emitter of Q1 we see an equivalent resistance of ro1 , so we can draw the following
equivalent circuit for finding Rout :
VCC
ro1

Q2

Rout

Rout = ro2 + (1 + gm2 ro2 ) (r2 k ro1 )

Comparing this to the solution to part (a), we can see that the output resistance is larger because
instead of a factor of 1/gm1 dominating the parallel resistors in the expression, r2 dominates
(assuming ro1 r2 ).

5.52 (a)

VCC

VCC IB (100 k) IE (100 ) = VBE = VT ln(IC /IS )

1
1+
IC (100 k)
IC (100 ) = VT ln(IC /IS )

IC = 1.6 mA
1 k
Av = 1
gm + 100
gm = 61.6 mS
Av = 8.60

(b)
VCC IB (50 k) IE (2 k) = VT ln(IC /IS )
IC = 708 A
Av =

1 k
1
gm

(1 k)k(50 k)
1+

gm = 27.2 mS
Av = 21.54
(c)
IB =

IC
VCC VBE IE (2.5 k) VBE + IE (2.5 k)
=

14 k
11 k

IC =

VCC VT ln(IC /IS )

1+
IC (2.5

k)

14 k

IC = 163 A
Av =

10 k
1
gm

+ 500 +

gm = 6.29 mS
Av = 14.98

(1 k)k(14 k)k(11 k)
1+

VT ln(IC /IS ) +

1+
IC (2.5

11 k

k)

5.53 (a)
VCC 1.5 V
RC
= 4 mA

IC =

VBE = VT ln(IC /IS ) = 832 mV

VCC VBE
= 66.7 A
IB =
RB
IC
=
= 60
IB
(b) Assuming the speaker has an impedance of 8 , the gain of the amplifier is
Av = gm (RC k 8 )
IC
=
(RC k 8 )
VT
= 1.19
Thus, the circuit provides greater than unity gain.

5.54 (a)
Av = gm RC
IC
gm =
= 76.9 mS
VT
Av = 38.46
1
Rin =
k r
gm

= 1.3 k
r =
gm
Rin = 12.87
Rout = RC = 500
(b) Since Av = gm RC and gm is fixed for a given value of IC , RC should be chosen as large as
possible to maximize the gain of the amplifier. Vb should be chosen as small as possible to
maximize the headroom of the amplifier (since in order for Q1 to remain in forward active, we
require Vb < VCC IC RC ).

5.56 (a) Looking into the emitter of Q2 we see an equivalent resistance of

following equivalent circuit for finding Rin :

1
gm2

k r2 , so we can draw the

VCC
R1

Q1
1
gm2

k r2

Rin

Rin =

r1 +

1
gm2

k r2

1 + 1

(b) Looking right from the base of Q1 we see an equivalent resistance of R2 , so we can draw the
following equivalent circuit for finding Rin :
VCC
R1

Q1
R2

Rin

Rin =

r1 + R2
1 + 1

(c) Looking right from the base of Q1 we see an equivalent resistance of R2 k

draw the following equivalent circuit for finding Rin :

1
gm2

k r2 , so we can

VCC
R1

Q1
R2 k

1
gm2

k r2

Rin

Rin =

r1 + R2 k

1
gm2

k r2

1 + 1

(d) Looking right from the base of Q1 we see an equivalent resistance of R2 k r2 , so we can draw the
following equivalent circuit for finding Rin :
VCC
R1

Q1
R2 k r2

Rin

Rin =

r1 + R2 k r2
1 + 1

5.58 (a)
IB =

IC
VCC VBE IE (400 ) VBE + IE (400 )
=

13 k
12 k

IC =

VCC VT ln(IC /IS )

1+
IC (400

13 k

IC = 1.02 mA
VBE = VT ln(IC /IS ) = 725 mV
VCE = VCC IC (1 k) IE (400 ) = 1.07 V
Q1 is operating in forward active.
(b)
Av = gm (1 k)
gm = 39.2 mS
Av = 39.2

VT ln(IC /IS ) +

1+
IC (400

12 k

5.61 For small-signal analysis, we can draw the following equivalent circuit.
R1

vout
Q1
vin

Av = gm R1
Rin =

1
k r
gm

Rout = R1

5.61 For small-signal analysis, we can draw the following equivalent circuit.
R1

vout
Q1
vin

Av = gm R1
Rin =

1
k r
gm

Rout = R1

5.63 Since IS1 = 2IS2 and theyre biased identically, we know that IC1 = 2IC2 , which means gm1 = 2gm2 .
vout1
= gm1 RC = 2gm2 RC
vin
vout2
= gm2 RC
vin
vout1
vout2

=2
vin
vin

5.67
r + RS
1+
VT /IC + RS
=
1+
5

IC =
IE =
I1
1+
1+

Rout =

(1+)VT
I1

+ RS

1+

(1+)VT
I1

+ RS

1+

5
I1 8.61 mA

5.68 (a) Looking into the collector of Q2 we see an equivalent resistance of ro2 = , so we can draw the
following equivalent circuit:
VCC
vin

Q1
vout

Av = 1
Rin =
Rout =

1
k r1
gm1

(b) Looking down from the emitter of Q1 we see an equivalent resistance of

the following equivalent circuit:

1
gm2

k r2 , so we can draw

VCC
vin

Q1
vout
1
gm2

Av =

1
gm2
1
gm1

k r2

k r2
1
gm2

k r2

Rin = r1 + (1 + 1 )
Rout =

1
gm2

k r2

1
1
k r1 k
k r2
gm1
gm2

(c) Looking into the emitter of Q2 we see an equivalent resistance of

following equivalent circuit:

r2 +RS
1+2 ,

so we can draw the

VCC
vin

Q1
vout
r2 +RS
1+2

Av =

Rin
Rout

r2 +RS
1+2
r2 +RS
1
+
gm1
1+2

r2 + RS
= r1 + (1 + 1 )
1 + 2


r2 + RS
1
=
k r1 k
gm1
1 + 2

(d) Looking down from the emitter of Q1 we see an equivalent resistance of RE +

can draw the following equivalent circuit:

1
gm2

k r2 , so we

VCC
vin

Q1
vout
RE +

Av =

RE +
1
gm1

Rin
Rout

1
gm2

+ RE +

1
gm2

k r2

k r2
1
gm2

k r2

1
= r1 + (1 + 1 ) RE +
gm2


1
1
=
k r1 k RE +
gm1
gm2

(e) Looking into the emitter of Q2 we see an equivalent resistance of

following equivalent circuit:

1
gm2

k r2 , so we can draw the

VCC
vin

Q1

RE
vout
1
gm2

Av =

RE +
1

+ RE +

gm1

1
gm2

1
gm1

Rin

1
gm2

k r2

k r2
1
gm2

k r2 RE +

+ RE +

1
gm1

k r2

1
gm2

k r2
1
gm2

k r2

= r1 + (1 + 1 ) RE +

Rout =

1
gm2

k r1 + RE

1
gm2 k r2
1
k r2
gm2

k r2

5.69 (a) Looking into the base of Q2 we see an equivalent resistance of r2 (assuming the emitter of Q2 is
grounded), so we can draw the following equivalent circuit for finding the impedance at the base
of Q1 :
VCC
Q1

Req

r2

Req = r1 + (1 + 1 )r2
1
k r1 (assuming the base of
(b) Looking into the emitter of Q1 we see an equivalent resistance of gm1
Q1 is grounded), so we can draw the following equivalent circuit for finding the impedance at the
emitter of Q2 :

VCC
1
gm1

k r1

Q2

Req

Req =

r2 +

1
gm1

k r1

1 + 2

(c)
1 IB1 + 2 (1 + 1 )IB1
IC1 + IC2
=
IB1
IB1
= 1 + 2 (1 + 1 )
If we assume that 1 , 2 1, then this simplifies to 1 2 , meaning a Darlington pair has a current
gain approximately equal to the product of the current gains of the individual transistors.

5.70 (a)
RCS = ro2 + (1 + gm2 ro2 ) (r2 k RE )
(b)
Av =

ro2 + (1 + gm2 ro2 ) (r2 k RE )

gm1 + ro2 + (1 + gm2 ro2 ) (r2 k RE )
1

Rin = r1 + (1 + 1 ) [ro2 + (1 + gm2 ro2 ) (r2 k RE )]

Rout =

1
gm1

k r1 k [ro2 + (1 + gm2 ro2 ) (r2 k RE )]

5.72 (a) Looking into the base of Q2 we see an equivalent resistance of r2 , so we can draw the following
equivalent circuit for finding Rin :
VCC
Q1

Rin

RE k r2

Rin = r1 + (1 + 1 ) (RE k ro1 )

Looking into the collector of Q2 we see an equivalent resistance of ro2 . Thus,
Rout = RC k ro2
(b) Looking into the base of Q2 we see an equivalent resistance of r2 , so we can draw the following
equivalent circuit for finding vX /vin :
VCC
vin

Q1
vX
RE k r2

vX
=
vin

RE k r2 k ro1
gm1 + RE k r2 k ro1
1

We can find vout /vX by inspection.

vout
= gm2 (RC k ro2 )
vX
vX vout
Av =

vin vX
= gm2 (RC k ro2 )

RE k r2 k ro1
gm1 + RE k r2 k ro1
1

5.73 (a) Looking into the emitter of Q2 we see an equivalent resistance of

following equivalent circuit for finding Rin :

1
gm2

k r2 , so we can draw the

VCC
Q1

Rin

Rin

RE k

1
gm2

k r2

1
= r1 + (1 + 1 ) RE k
k r2
gm2

Looking into the collector of Q2 , we see an equivalent resistance of (because VA = ), so we

have
Rout = RC
(b) Looking into the emitter of Q2 we see an equivalent resistance of
following equivalent circuit for finding vX /vin :
VCC
vin

Q1
vX
RE k

vX
=
vin

1
gm2

1
gm2 k
1
1
gm1 +E k gm2

RE k

k r2

r2
k r2

We can find vout /vX by inspection.

vout
= gm2 RC
vX
vX vout

Av =
vin vX
= gm2 RC

1
gm2 k
1
1
gm1 +E k gm2

RE k

r2
k r2

1
gm2

k r2 , so we can draw the

5.74
Rout = RC = 1 k
Av = gm RC = 10
gm = 10 mS
IC = gm VT = 260 A
VCC VBE
IC
= IB =
RB

VCC VT ln(IC /IS )

RB =
IC
= 694 k
Rin = RB k r = 9.86 k > 5 k
In sizing CB , we must consider the effect a finite impedance in series with the input will have on the
circuit parameters. Any series impedance will cause Rin to increase and will not impact Rout . However,
1
a series impedance can cause gain degradation. Thus, we must ensure that |ZB | = jC
does not
B
degrade the gain significantly.
If we include |ZB | in the gain expression, we get:
Av =
Thus, we want

1
1+

|ZB |

1
gm

RC
1
gm

(|ZB |)kRB
1+

to ensure the gain is not significantly degraded.

1 1
1

1 + jCB
gm
1
1
1 1
=
1 + 2f CB
10 gm
CB = 788 nF

5.75
Rout = RC 500
To maximize gain, we should maximize RC .
RC = 500
VCC IC RC VBE 400 mV = VT ln(IC /IS ) 400 mV
IC 4.261 mA
To maximize gain, we should maximize IC .
IC = 4.261 mA
VCC VBE
IC
=
IB =

RB
IC
VCC VT ln(IC /IS )
=
=

RB
RB = 40.613 k

5.76
Rout = RC = 1 k
|Av | = gm RC
IC RC
=
VT
20
IC 520 A
In order to maximize Rin = RB k r , we need to maximize r , meaning we should minimize IC (since
T
r = V
IC ).
IC = 520 A
IC
VCC VBE
IB =
=

RB
VCC VT ln(IC /IS )
=
RB
RB = 343 k

5.77
Rout = RC = 2 k
Av = gm RC
IC RC
=
VT
= 15
IC = 195 A
VBE = VT ln(IC /IS ) = 689.2 mV
VCE VBE 400 mV = 289.2 mV
To minimize the supply voltage, we should minimize VCE .
VCE = 289.2 mV
VCC VCE
= IC
RC
VCC = 679.2 mV
Note that this value of VCC is less than the required VBE . This means that the value of VCC is
constrained by VBE , not VCE . In theory, we could pick VCC = VBE , but in this case, wed have
to set RB = 0 , which would short the input to VCC . Thus, lets pick a reasonable value for RB ,
RB = 100 .
IC
VCC VBE
= IB =
RB

VCC = 689.4 mV

5.78
|Av | = gm RC
IC RC
=
VT
= A0
Rout = RC
IC Rout
A0 =
VT
A0 VT
IC =
Rout
P = IC VCC
=

A0 VT
VCC
Rout

Thus, we must trade off a small output resistance with low power consumption (i.e., as we decrease
Rout , power consumption increases and vice-versa).

5.79
P = (IB + IC )VCC
1+
=
IC VCC

= 1 mW
IC = 396 A
VCC VBE
IC
= IB =
RB

VCC VT ln(IC /IS )

RB =
IC
= 453 k
Av = gm RC
IC RC
=
VT
= 20
RC = 1.31 k

5.81
Rout = RC 1 k
To maximize gain, we should maximize Rout .
RC = 1 k
VCC IC RC IE RE = VCE VBE 400 mV
VCC IC RC 200 mV VT ln(IC /IS ) 400 mV
IC 1.95 mA
To maximize gain, we should maximize IC .
IC = 1.95 mA
1+
IC RE = 200 mV
IE RE =

VCC

RE = 101.5
10IB R1 IE RE = VBE = VT ln(IC /IS )
R1 = 7.950 k
9IB R2 IE RE = VBE = VT ln(IC /IS )
R2 = 5.405 k

5.82
P = (10IB + IC ) VCC


IC
= 10
+ IC VCC

= 5 mW

IC = 1.82 mA
1+
IC RE = 200 mV
IE RE =

RE = 109
RC
Av = 1
gm + RE
RC
IC + RE

= VT
= 5

RC = 616
VCC 10IB R1 200 mV = VBE = VT ln(IC /IS )
R1 = 8.54 k
9IB R2 200 mV = VBE = VT ln(IC /IS )
R2 = 5.79 k

5.83
1
= 50 (since RE doesnt affect Rin )
gm
= 20 mS

Rin =
gm

IC = gm VT = 520 A
1+
IC RE = 260 mV
IE RE =

RE = 495
Av = gm RC = 20
RC = 1 k
VCC 10IB R1 IE RE = VBE = VT ln(IC /IS )
R1 = 29.33 k
9IB R2 IE RE = VBE = VT ln(IC /IS )
R2 = 20.83 k
To pick CB , we must consider its effect on Av . If we assume the capacitor has an impedance ZB and
|ZB | R1 , R2 , then we have:
Av =
Thus, we should choose

1
1+

|ZB |

RC
1
gm

|ZB |
1+

1
gm .

1
1 1
1
1
=
|ZB | =
1+
1 + 2f CB
10 gm
CB = 1.58 F

5.84
Rout = RC = 500
Av = gm RC = 8
gm = 16 mS
IC = gm VT = 416 A
1+
IC RE = 260 mV
IE RE =

RE = 619
VCC 10IB R1 IE RE = VBE = VT ln(IC /IS )
R1 = 36.806 k
9IB R2 IE RE = VBE = VT ln(IC /IS )
R2 = 25.878 k
To pick CB , we must consider its effect on Av . If we assume the capacitor has an impedance ZB and
|ZB | R1 , R2 , then we have:
Av =
Thus, we should choose

1
1+

|ZB |

RC
1
gm

|ZB |
1+

1
gm .

1
1 1
1
1
=
|ZB | =
1+
1 + 2f CB
10 gm
CB = 1.26 F

5.85
Rout = RC = 200
IC RC
= 20
Av = gm RC =
VT
IC = 2.6 mA
P = VCC (10IB + IC )


IC
= VCC 10
+ IC

= 7.15 mW

5.86
P = (IC + 10IB ) VCC


IC
= IC + 10
VCC

= 5 mW

IC = 1.82 mA
Av = gm RC
IC RC
=
VT
= 10
RC = 143
1+
IE RE =
IC RE = 260 mV

VCC

RE = 141.6
10IB R1 IE RE = VBE = VT ln(IC /IS )
R1 = 8.210 k
9IB R2 IE RE = VBE = VT ln(IC /IS )
R2 = 6.155 k

To pick CB , we must consider its effect on Av . If we assume the capacitor has an impedance ZB and
|ZB | R1 , R2 , then we have:
Av =
Thus, we should choose

1
1+

|ZB |

RC
1
gm

|ZB |
1+

1
gm .

1
1 1
1
1
=
|ZB | =
1+
1 + 2f CB
10 gm
CB = 5.52 F

5.87
1
= 50 (since RE doesnt affect Rin )
gm
= 20 mS

Rin =
gm

IC = gm VT = 520 A
Av = gm RC = 20
RC = 1 k
1+
IE RE =
IC RE = 260 mV

RE = 495
To minimize the supply voltage, we should allow Q1 to operate in soft saturation, i.e., VBC = 400 mV.
VBE = VT ln(IC /IS ) = 715 mV
VCE = VBE 400 mV = 315 mV
VCC IC RC IE RE = VCE
VCC

VCC = 1.095 V
10IB R1 IE RE = VBE
R1 = 2.308 k
9IB R2 IE RE = VBE
R2 = 20.827 k

To pick CB , we must consider its effect on Av . If we assume the capacitor has an impedance ZB and
|ZB | R1 , R2 , then we have:
Av =
Thus, we should choose

1
1+

|ZB |

RC
1
gm

|ZB |
1+

1
gm .

1
1
1 1
1
=
|ZB | =
1+
1 + 2f CB
10 gm
CB = 1.58 F

5.90 As stated in the hint, lets assume that IE RE VT . Given this assumption, we can assume that RE
does not affect the gain.
IE RE = 10VT = 260 mV
RL
Av = 1
= 0.8
gm + RL
gm = 80 mS
IC = gm VT = 2.08 mA
1+
IC RE = 260 mV

RE = 124
VCC IB R1 IE RE = VBE = VT ln(IC /IS )
R1 = 71.6 k
To pick C1 , we must consider its effect on Av . If we assume the capacitor has an impedance Z1 and
|Z1 | R1 , then we have:
Av =
Thus, we should choose

1
1+

|Z1 |

RE
1
gm

+ RE +

|Z1 |
1+

1
gm .

1
1 1
1
1
=
|Z1 | =
1+
1 + 2f C1
10 gm
C1 = 12.6 pF
To pick C2 , we must also consider its effect on Av . Since the capacitor appears in series with RL , we
need to ensure that |Z2 | RL , assuming the capacitor has impedance Z2 .
|Z2 | =

1
1
=
RL
2f C2
10

C2 = 318 pF

6.4 (a)

Q(x)

Q(x) = W Cox (VGS V (x) VT H )

= W Cox (VGS VT H ) W Cox V (x)

W Cox (VGS VT H )

Increasing VDS

The curve that intersects the axis at x = L (i.e., the curve for which the channel begins to pinch
off) corresponds to VDS = VGS VT H .
(b)
1
Q(x)

RLocal (x)

RLocal (x)

Increasing VDS

Note that RLocal diverges at x = L when VDS = VGS VT H .

6.15

ID

Increasing VDS

VT H

VGS

Initially, when VGS is small, the transistor is in cutoff and no current flows. Once VGS increases
beyond VT H , the curves start following the square-law characteristic as the transistor enters saturation.
However, once VGS increases past VDS + VT H (i.e., when VDS < VGS VT H ), the transistor goes into
triode and the curves become linear. As we increase VDS , the transistor stays in saturation up to larger
values of VGS , as expected.

6.17
1
W
n Cox
(VGS VT H ) , < 2
2
L
ID
,
VGS

W
1
= n Cox
(VGS VT H )
2
L
ID
=
VGS VT H

ID =
gm

6.21 Since theyre being used as current sources, assume M1 and M2 are in saturation for this problem.
To find the maximum allowable value of , we should evaluate when 0.99ID2 = ID1 and 1.01ID2 =
ID1 , i.e., at the limits of the allowable values for the currents. However, note that for any valid
(remember, should be non-negative), we know that ID2 > ID1 (since VDS2 > VDS1 ), so the case
where 1.01ID2 = ID1 (which implies ID2 < ID1 ) will produce an invalid value for (you can check this
yourself). Thus, we need only consider the case when 0.99ID2 = ID1 .
W
1
2
(VB VT H ) (1 + VDS2 )
0.99ID2 = 0.99 n Cox
2
L
= ID1
1
W
2
= n Cox
(VB VT H ) (1 + VDS1 )
2
L
0.99 (1 + VDS2 ) = 1 + VDS1
= 0.02 V1

5.27
VDD ID RD = VGS = VT H +

2ID
n Cox W
L

2ID
2
= (VDD VT H ID RD )
W
n Cox L
i
W h
1
2
2 2
(VDD VT H ) 2ID RD (VDD VT H ) + ID
RD
ID = n Cox
2
L

We can rearrange this to the standard quadratic form as follows:

1
W 2
W
W
1
2
2
n Cox RD ID n Cox RD (VDD VT H ) + 1 ID + n Cox
(VDD VT H ) = 0
2
L
L
2
L
Applying the quadratic formula, we have:
q
2
2
R
(V

V
)
+
1

n Cox W
4 21 n Cox W
n Cox W
DD
TH
L D
L RD (VDD VT H ) + 1
L RD (VDD VT H )

ID =
2
2 21 n Cox W
L RD
q
2
2
W
n Cox W
n Cox W
n Cox L RD (VDD VT H ) + 1
L RD (VDD VT H ) + 1
L RD (VDD VT H )
=
2
n Cox W
L RD
q
n Cox W
1 + 2n Cox W
L RD (VDD VT H ) + 1
L RD (VDD VT H )
=
2
n Cox W
L RD
Note that mathematically, there are two possible solutions for ID . However, since M1 is diodeconnected, we know it will either be in saturation or cutoff. Thus, we must reject the value of ID
that does not match these conditions (for example, a negative value of ID would not match cutoff or
saturation, so it would be rejected in favor of a positive value).

6.33 (a) Assume M1 is operating in saturation.

VGS = 1 V
1
W
2
VDS = VDD ID RD = VDD n Cox
(VGS VT H ) (1 + VDS ) RD
2
L
VDS = 1.35 V > VGS VT H , which verifies our assumption
ID = 4.54 mA
W
(VGS VT H ) = 13.333 mS
gm = n Cox
L
1
= 2.203 k
ro =
ID

+
vgs

gm vgs

ro

RD

(b) Since M1 is diode-connected, we know it is operating in saturation.

W
1
2
(VGS VT H ) (1 + VGS ) RD
VGS = VDS = VDD ID RD = VDD n Cox
2
L
VGS = VDS = 0.546 V
ID = 251 A
W
(VGS VT H ) = 3.251 mS
gm = n Cox
L
1
= 39.881 k
ro =
ID

+
vgs

gm vgs

ro

RD

(c) Since M1 is diode-connected, we know it is operating in saturation.

ID = 1 mA
r

gm =
ro =

2n Cox

W
ID = 6.667 mS
L

1
= 10 k
ID

+
vgs

gm vgs

ro

(d) Since M1 is diode-connected, we know it is operating in saturation.

VGS = VDS
1
W
n Cox
(VGS VT H )2 (1 + VGS ) (2 k)
2
L
= 0.623 V

VDD VGS = ID (2 k) =
VGS = VDS

ID = 588 A
W
gm = n Cox
(VGS VT H ) = 4.961 mS
L
1
ro =
= 16.996 k
ID

+
gm vgs

vgs

2 k

ro

(e) Since M1 is diode-connected, we know it is operating in saturation.

ID = 0.5 mA
r

gm =
ro =

2n Cox

W
ID = 4.714 mS
L

1
= 20 k
ID

+
vgs

gm vgs

ro

6.38 (a)
vout

+
vgs2

gm2 vgs2

ro2

gm1 vgs1

ro1

RD

vin

+
vgs1

(b)
vin

vout

+
vgs1

gm1 vgs1

ro1

RD

+
gm2 vgs2

ro2

vgs2

(c)
vin

vout

+
vgs1

gm1 vgs1

ro1

gm2 vgs2

ro2

+
vgs2

(d)

RD

vin

+
vgs1

gm1 vgs1

ro1

vout
+
vgs2

gm2 vgs2

ro2

(e)
vout

+
vgs1

gm1 vgs1

ro1

RD

vin
+
gm2 vgs2

ro2

vgs2

6.43 (a) Assume M1 is operating in triode (since |VGS | = 1.8 V is large).

|VGS | = 1.8 V
i
W h
1
2
2 (|VGS | |VT H |) |VDS | |VDS | (500 )
p Cox
2
L
|VDS | = 0.418 V < |VGS | |VT H | , which verifies our assumption

VDD |VDS | = |ID | (500 ) =

|ID | = 2.764 mA
(b) Since M1 is diode-connected, we know it is operating in saturation.
|VGS | = |VDS |
1
W
2
p Cox
(|VGS | |VT H |) (1 k)
2
L
|VGS | = |VDS | = 0.952 V

VDD |VGS | = |ID |(1 k) =

|ID | = 848 A
(c) Since M1 is diode-connected, we know it is operating in saturation.
|VGS | = |VDS |
|VGS | = VDD |ID |(1 k) = VDD |ID |(1 k) =
|VGS | = |VGS | = 0.952 V
|ID | = 848 A

1
W
2
p Cox
(|VGS | |VT H |) (1 k)
2
L

6.44 (a)

IX

Saturation

Cutoff

VDD VT H

VDD

VX

VDD

VX

M1 goes from saturation to cutoff when VX = VDD VT H = 1.4 V.

(b)

IX
1 + VT H

Saturation
M1 goes from saturation to triode when VX = 1 + VT H = 1.4 V.
(c)

Triode

IX
VDD VT H

Saturation

VDD

VX

VDD

VX

Cutoff

M1 goes from saturation to cutoff when VX = VDD VT H = 1.4 V.

(d)

IX

Saturation

Cutoff

VT H
M1 goes from cutoff to saturation when VX = VT H = 0.4 V.

7.1
VGS = VDD = 1.8 V
VDS > VGS VT H (in order for M1 to operate in saturation)
VDS = VDD ID (1 k)
W
1
2
(VGS VT H ) (1 k)
= VDD n Cox
2
L
> VGS VT H
W
< 2.04
L

7.3
VGS = VDD ID (100 )
VDS = VDD ID (1 k + 100 )

> VGS VT H (in order for M1 to operate in saturation)

VDD ID (1 k + 100 ) > VDD ID (100 ) VT H
ID (1 k + 100 ) < ID (100 ) + VT H
ID (1 k) < VT H
ID < 400 A
Since gm increases with ID , we should pick the maximum ID to determine the maximum transconductance that M1 can provide.
ID,max = 400 A
2ID,max
gm,max =
VGS VT H
2ID,max
=
VDD ID,max (100 ) VT H
= 0.588 mS

7.5
ID1 = 0.5 mA
VGS = VT H +

2ID1
n Cox W
L

= 0.612 V
1
ID1 R2
VGS =
10
R2 = 12.243 k
11
1
VGS = VDD ID1 R1 ID1 RS
10
10
R1 = 21.557 k

7.6
ID = 1 mA
2ID
1
gm =
=
VGS VT H
100
VGS = 0.6 V
VGS = VDD ID RD
RD = 1.2 k

7.8 First, lets analyze the circuit excluding RP .

20 k
VDD = 1.2 V
10 k + 20 k
= VG ID RS = VDS = VDD ID (1 k + 200 )

VG =
VGS

ID = 600 A
VGS = 1.08 V
2ID
W
=
= 12.9758 13
L
n Cox (VGS VT H )2
Now, lets analyze the circuit with RP .
VDD
10 k

ID + IRP

1 k

M1

20 k

RS

IRP

RP

200

VG = 1.2 V
VDD VDS
ID + IRP =
1 k + 200
VGS = VG (ID + IRP ) RS = VDS + VT H
VDD VDS
VG
RS = VDS + VT H
1 k + 200
VDS = 0.6 V
VGS = 1 V
W
1
2
(VGS VT H )
ID = n Cox
2
L
= 467 A
VDS
VDD VDS
ID + IRP = ID +
=
RP
1 k + 200
RP = 1.126 k

7.9 First, lets analyze the circuit excluding RP .

VGS = VDD = 1.8 V
VDS = VDD ID (2 k) = VGS 100 mV

W
1
2
(VGS VT H ) (2 k) = VGS 100 mV
VDD n Cox
2
L
W
= 0.255
L
Now, lets analyze the circuit with RP .
VDD
30 k

2 k
RP
IRP
M1

VGS = VDD IRP (30 k)

VGS VDS
50 mV
IRP =
=
RP
RP
VGS = VDD (ID IRP ) (2 k) + 50 mV


W
1
2
n Cox
(VGS VT H ) IRP (2 k) + 50 mV
VDD IRP (30 k) = VDD
2
L


1
W
2
VDD IRP (30 k) = VDD
n Cox
(VDD IRP (30 k) VT H ) IRP (2 k) + 50 mV
2
L
IRP = 1.380 A
50 mV
= 36.222 k
RP =
IRP

7.12 Since were not given VDS for the transistors, lets assume = 0 for large-signal calculations. Lets
also assume the transistors operate in saturation, since theyre being used as current sources.
IX =

1
W1
2
(VB1 VT H ) = 0.5 mA
n Cox
2
L1

W1 = 3.47 m
IY =

W2
1
(VB2 VT H )2 = 0.5 mA
n Cox
2
L2

W2 = 1.95 m
1
= 20 k
IX
1
= 20 k
=
IY

Rout1 = ro1 =
Rout2 = ro2

Since IX = IY and is the same for each current source, the output resistances of the current sources
are the same.

7.13 Looking into the source of M1 we see a resistance of

1
gm .

Including in our analysis, we have

1
1
=
gm
(V

V
|VT H |) (1 + VX )
p Cox W
X
B1
L
= 372

7.17 (a) Assume M1 is operating in saturation.

ID = 0.5 mA
VGS = VT H +

2ID
n Cox W
L

= 0.573 V
VDS = VDD ID RD = 0.8 volt > VGS VT H , verifying that M1 is in saturation
(b)
Av = gm RD
2ID
RD
=
VGS VT H
= 11.55

7.18 (a) Assume M1 is operating in saturation.

ID = 0.25 mA
s

VGS = VT H +

2ID
n Cox W
L

= 0.55 V
VDS = VDD ID RD = 1.3 V > VGS VT H , verifying that M1 is in saturation
(b)
VGS = 0.55 V
VDS > VGS VT H (to ensure M1 remains in saturation)

VDD ID RD > VGS VT H

W
1
2
(VGS VT H ) RD > VGS VT H
VDD n Cox
2
L
W
2 (VDD VGS + VT H )
<
L
n Cox (VGS VT H )2 RD
= 366.67
20
= 3.3
0.18
Thus, W/L can increase by a factor of 3.3 while M1 remains in saturation.
Av = gm RD

W
(VGS VT H ) RD
L

W
(VGS VT H ) RD
= n Cox
L max

= n Cox
Av,max

= 22

7.19
P = VDD ID < 1 mW
ID < 556 A
Av = gm RD
r

= 2n Cox

= 5
W
20
<
L
0.18
RD > 1.006 k

W
ID RD
L

7.20 (a)
ID1 = ID2 = 0.5 mA
Av = gm1 (ro1 k ro2 )
s



W
1
1
= 2n Cox
ID1
k
L 1
1 ID1 2 ID2

W
L

= 10
= 7.8125

(b)
VDD VB = VT H +
VB = 1.1 V

2 |ID2 |

p Cox W
L 2

p
7.22 (a) If ID1 and ID2 remain constant while W and L double, then gm1 (W/L)1 ID1 will not change
1
1
(since it depends only on the ratio W/L), ro1 ID1
will not change, and ro2 ID2
will not
change. Thus, Av = gm1 (ro1 k ro2 ) will not change .
p

1
(b) If ID1 , ID2 , W , and L double, then gm1 (W/L)1 ID1 will increase by a factor of 2, ro1 ID1
1
will halve, and ro2 ID2 will halve. This means that ro1 k ro2 will halve as well, meaning

Av = gm1 (ro1 k ro2 ) will decrease by a factor of 2 .

7.26 (a)
ID1 = ID2 = 0.5 mA
s
2ID1

VGS1 = VT H +
n Cox W
L 1
= 0.7 V

VDS1 = VGS1 VT H (in order of M1 to operate at the edge of saturation)

= VDD VGS2
s
2ID2

VGS2 = VDD VGS1 + VT H = VT H +
n Cox W
L 2

W
= 4.13
L 2
(b)
gm1
gm2
q
2n Cox
= q
2n Cox
v
u W
u L
1
= t W

Av =

W
L 1 ID1

W
L 2 ID2

= 3.667

(c) Since (W/L)1 is fixed, we must minimize (W/L)2 in order to maximize the magnitude of the gain
(based on the expression derived in part (b)). If we pick the size of M2 so that M1 operates at the
edge of saturation, then if M2 were to be any smaller, VGS2 would have to be larger (given the
same ID2 ), driving M1 into triode. Thus, (W/L)2 is its smallest possible value (without driving
M1 into saturation) when M1 is at the edge of saturation, meaning the gain is largest in magnitude
with this choice of (W/L)2 .

7.27 (a)
gm1
gm2
q
2n Cox
= q
2n Cox
v
u W
u
L 1

= t W

Av =

W
L

W
L 1 ID1

W
L 2 ID2

= 5

= 277.78

(b)

VDD VT H

VDS1 > VGS1 VT H (to ensure M1 is in saturation)

VDD VGS2 > VGS1 VT H
s
s
2ID2
2ID1
>

W
n Cox L 2
n Cox W
L 1
ID1 = ID2 < 1.512 mA

7.28 For this problem, recall that looking into the drain of a transistor with a grounded gate and source
we see a resistance of ro , and looking into either terminal of a diode-connected transistor we see a
resistance of g1m k ro .
(a)


1
k ro2
Av = gm1 ro1 k
gm2
(b)


1
k ro3
Av = gm1 ro1 k ro2 k
gm3
(c)


1
Av = gm1 ro1 k ro2 k
k ro3
gm3
(d)


1
k ro3
Av = gm2 ro2 k ro1 k
gm3
(e)


1
k ro3
Av = gm2 ro2 k ro1 k
gm3
(f) Lets draw a small-signal model to find the equivalent resistance seen looking up from the output.
RD
+

+
vt

it

gm2 vgs2

vgs2

ro2

it = gm2 vgs2 +

vt it RD
ro2

vgs2 = vt
vt it RD
it = gm2 vt +
ro2




1
RD
= vt gm2 +
it 1 +
ro2
ro2
R

D
1 + ro2
vt
ro2 + RD
=
=
it
1 + gm2 ro2
gm2 + r1o2


ro2 + RD
Av = gm1 ro1 k
1 + gm2 ro2

7.30 (a) Assume M1 is operating in saturation.

ID = 1 mA
ID RS = 200 mV
RS = 200
RD
Av = 1
gm + RS
=

RD
1
2n Cox W
L ID

= 4
W
= 1000
L
s

VGS = VT H +

VDS

+ RS

2ID
n Cox W
L

= 0.5 V
= VDD ID RD ID RS

= 0.6 V > VGS VT H , verifying that M1 is in saturation

Yes , the transistor operates in saturation.
(b) Assume M1 is operating in saturation.
50
W
=
L
0.18
RS = 200
Av =

RD
1
2n Cox W
L ID

+ RS

= 4
RD = 1.179 k
s

VGS = VT H +

VDS

2ID
n Cox W
L

= 0.590 V
= VDD ID RD ID RS

= 0.421 V > VGS VT H , verifying that M1 is in saturation

Yes , the transistor operates in saturation.

7.42 (a)
Rout = RD = 500
VG = VDD
VD > VG VT H (in order for M1 to operate in saturation)
VDD ID RD > VDD VT H
ID < 0.8 mA
(b)
ID = 0.8 mA
1
Rin =
gm
1
=q
2n Cox W
L ID
= 50
W
= 1250
L

(c)
Av = gm RD
1
gm =
S
50
RD = 500
Av = 10

7.43 (a)
ID = I1 = 1 mA
VG = VDD
VD = VG VT H + 100 mV
VDD ID RD = VG VT H + 100 mV
RD = 300
(b)
RD = 300
Av = gm RD
r
=

2n Cox

=5

W
= 694.4
L

W
ID RD
L

7.44 For this problem, recall that looking into the drain of a transistor with a grounded gate and source
we see a resistance of ro , and looking into either terminal of a diode-connected transistor we see a
resistance of g1m k ro .
(a) Referring to Eq. (7.109) with RD =

1
gm2

and gm = gm1 , we have

Av =

1
gm2
1
gm1

+ RS

(b) Lets draw a small-signal model to find the equivalent resistance seen looking up from the output.
RD
+

+
vt

it

gm2 vgs2

vgs2

it = gm2 vgs2
vgs2 = vt
it = gm2 vt
1
vt
=
it
gm2
gm1
Av =
gm2
(c) Referring to Eq. (7.119) with RD =

1
gm2 ,

Av =

R3 = R1 , and gm = gm1 , we have

R1 k

1
gm1

RS + R1 k

1
gm1

gm1
gm2

(d)


1
k ro3
Av = gm1 RD +
gm2
(e)


1
Av = gm1 RD +
gm2

7.45 (a)


vX
1
= gm1 RD1 k
vin
gm2
vout
= gm2 RD2
vX
vout
vX vout
=
vin
vin vX


1
= gm1 gm2 RD2 RD1 k
gm2
(b)
lim

RD1

gm1 gm2 RD2 RD1 k

1
gm2

= gm1 RD2

This makes sense because the common-source stage acts as a transconductance amplifier with
a transconductance of gm1 . The common-gate stage acts as a current buffer with a current
gain of 1. Thus, the current gm1 vin flows through RD2 , meaning vout = gm1 vin RD2 , so that
vout
vin = gm1 RD2 .
This type of amplifier (with RD1 = ) is known as a cascode and will be studied in detail in
Chapter 9.

7.40
ID = 0.5 mA
1
Rin =
gm
1
=q
2n Cox W
L ID

VDD

= 50
W
= 2000
L
VD > VG VT H (in order for M1 to operate in saturation)
ID RD > Vb VT H
RD < 2.4 k

Since |Av | RD , we need to maximize RD in order to maximize the gain. Thus, we should pick
RD = 2.4 k . This corresponds to a voltage gain of Av = gm RD = 48.

7.42 (a)
Rout = RD = 500
VG = VDD
VD > VG VT H (in order for M1 to operate in saturation)
VDD ID RD > VDD VT H
ID < 0.8 mA
(b)
ID = 0.8 mA
1
Rin =
gm
1
=q
2n Cox W
L ID
= 50
W
= 1250
L

(c)
Av = gm RD
1
gm =
S
50
RD = 500
Av = 10

7.43 (a)
ID = I1 = 1 mA
VG = VDD
VD = VG VT H + 100 mV
VDD ID RD = VG VT H + 100 mV
RD = 300
(b)
RD = 300
Av = gm RD
r
=

2n Cox

=5

W
= 694.4
L

W
ID RD
L

7.44 For this problem, recall that looking into the drain of a transistor with a grounded gate and source
we see a resistance of ro , and looking into either terminal of a diode-connected transistor we see a
resistance of g1m k ro .
(a) Referring to Eq. (7.109) with RD =

1
gm2

and gm = gm1 , we have

Av =

1
gm2
1
gm1

+ RS

(b) Lets draw a small-signal model to find the equivalent resistance seen looking up from the output.
RD
+

+
vt

it

gm2 vgs2

vgs2

it = gm2 vgs2
vgs2 = vt
it = gm2 vt
1
vt
=
it
gm2
gm1
Av =
gm2
(c) Referring to Eq. (7.119) with RD =

1
gm2 ,

Av =

R3 = R1 , and gm = gm1 , we have

R1 k

1
gm1

RS + R1 k

1
gm1

gm1
gm2

(d)


1
k ro3
Av = gm1 RD +
gm2
(e)


1
Av = gm1 RD +
gm2

7.45 (a)


vX
1
= gm1 RD1 k
vin
gm2
vout
= gm2 RD2
vX
vout
vX vout
=
vin
vin vX


1
= gm1 gm2 RD2 RD1 k
gm2
(b)
lim

RD1

gm1 gm2 RD2 RD1 k

1
gm2

= gm1 RD2

This makes sense because the common-source stage acts as a transconductance amplifier with
a transconductance of gm1 . The common-gate stage acts as a current buffer with a current
gain of 1. Thus, the current gm1 vin flows through RD2 , meaning vout = gm1 vin RD2 , so that
vout
vin = gm1 RD2 .
This type of amplifier (with RD1 = ) is known as a cascode and will be studied in detail in
Chapter 9.

7.48 For small-signal analysis, we can short the capacitors, producing the following equivalent circuit.
R2 k R3 k RD

vout

M1
vin
R4

Av = gm (R2 k R3 k RD )

7.49
VGS = VDS
1
W
2
VGS = VDD ID RS = VDD n Cox
(VGS VT H ) (1 + VGS ) RS
2
L
VGS = VDS = 0.7036 V
ID = 1.096 mA
Av =
gm =
ro =

1
gm

ro k RS
+ ro k RS

2n Cox

W
ID = 6.981 mS
L

1
= 9.121 k
ID

Av = 0.8628

7.50
Av =

1
gm

RS
+ RS

=
n Cox W
L

RS
1
(VGS VT H )

+ RS

= 0.8
VGS = 0.64 V
1
W
2
ID = n Cox
(VGS VT H )
2
L
= 960 A
VG = VGS + VS = VGS + ID RS
= 1.12 V

7.55 For this problem, recall that looking into the drain of a transistor with a grounded gate and source
we see a resistance of ro , and looking into either terminal of a diode-connected transistor we see a
resistance of g1m k ro .
(a)
Av =

ro1 k (RS + ro2 )

gm1 + ro1 k (RS + ro2 )
1

(b) Looking down from the output we see an equivalent resistance of ro2 + (1 + gm2 ro2 ) RS by Eq.
(7.110).
ro1 k [ro2 + (1 + gm2 ro2 ) RS ]
Av = 1
gm1 + ro1 k [ro2 + (1 + gm2 ro2 ) RS ]
(c)
Av =

ro1 k

1
gm1

1
gm2

+ ro1 k

1
gm2

(d) Lets draw a small-signal model to find the equivalent resistance seen looking down from the
output.
R1
+
R2

+
gm2 vgs2

vgs2

ro2

vt
vt
+ gm2 vgs2 +
R1 + R2
ro2
R2
=
vt
R1 + R2
R2
vt
vt
+ gm2
vt +
=
R1 + R2
R1 + R2
ro2


1
gm2 R2
1
= vt
+
+
R1 + R2
R1 + R2
ro2


R1 + R2
k ro2
= (R1 + R2 ) k
gm2 R2


1 +R2
k ro2
ro1 k (R1 + R2 ) k Rgm2
R2


=
R1 +R2
1
k ro2
+
r
k
(R
+
R
)
k
o1
1
2
gm1
gm2 R2

it =

it
it
vt
it
Av

vt

vgs2

it

(e)
Av =

ro2 k ro3 k

1
gm2

1
gm1

+ ro2 k ro3 k

1
gm1

(f) Looking up from the output we see an equivalent resistance of ro2 + (1 + gm2 ro2 ) ro3 by Eq.
(7.110).
ro1 k [ro2 + (1 + gm2 ro2 ) ro3 ]
Av = 1
gm1 + ro1 k [ro2 + (1 + gm2 ro2 ) ro3 ]

7.58
P = VDD ID = 2 mW
ID = 1.11 mA
RD ID = 1 V
RD = 900
Av = gm RD
r
=

= 5

2n Cox

W
= 69.44
L

W
ID RD
L

7.60 Lets let R1 and R2 consume exactly 5 % of the power budget (which means the branch containing RD ,
M1 , and RS will consume 95 % of the power budget). Lets also assume Vov = VGS VT H = 300 mV
exactly.
ID VDD = 0.95(2 mW)
ID = 1.056 mA
ID RS = 200 mV
RS = 189.5
Vov = VGS VT H = 300 mV
W 2
1
ID = n Cox Vov
2
L
W
= 117.3
L
RD
Av = 1
gm + RS
=

RD
1

2n Cox W
L ID

+ RS

= 4
RD = 1.326 k
2
VDD
= 0.05(2 mW)
R1 + R2
2
VDD
R1 + R2 =
0.1 mW
VG = VGS + ID RS = Vov + VT H + ID RS = 0.9 V
R2
VG =
VDD
R1 + R2
R2
= V2
= 0.9 V
DD

0.1 mW

R2 = 29.16 k
R1 = 3.24 k

7.61 Lets let R1 and R2 consume exactly 5 % of the power budget (which means the branch containing
RD , M1 , and RS will consume 95 % of the power budget).
RD = 200
ID VDD = 0.95(6 mW)
ID = 3.167 mA
ID RS = Vov = VGS VT H
Vov
RS =
ID
2ID
gm =
Vov
RD
Av = 1
gm + RS
RD
Vov
2ID + ID

= Vov
= 5

Vov = 84.44 mV
RS = 26.67
2ID
W
= 4441
=
2
L
n Cox Vov
2
VDD
= 0.05(6 mW)
R1 + R2
2
VDD
R1 + R2 =
0.3 mW
VG = VGS + ID RS = Vov + VT H + ID RS = 0.5689 V
R2
VG =
VDD
R1 + R2
R2
= V2
= 0.5689 V
DD

0.3 mW

R2 = 6.144 k
R1 = 4.656 k

7.62
Rin = R1 = 20 k
P = VDD ID = 2 mW
ID = 1.11 mA
VDS = VGS VT H + 200 mV

VDD ID RD = VDD VT H + 200 mV

RD = 180
Av = gm RD
r

2n Cox

W
ID RD
L

= 6

W
= 2500
L
s

VGS = VT H +

2ID
n Cox W
L

= 0.467 V
VGS = VDD ID RS
RS
1
2f C1
1
2f C1
f

= 1.2 k
R1
1
R1
10
= 1 MHz
=

C1 = 79.6 pF
1
1
k RS
2f CS
gm
1 1
1
=
2f CS
10 gm
r
gm =

2n Cox

CS = 52.9 nF

W
ID = 33.33 mS
L

7.64 (a)
Av = gm1 (ro1 k RG k ro2 )

(b)
P = VDD ID1 = 3 mW
ID1 = |ID2 | = 1.67 mA

VDD
|VGS2 | = |VDS2 | = VDS =
2

W
1
(|VGS2 | |VT H |)2 (1 + p |VDS2 |)
|ID2 | = p Cox
2
L 2

W
= 113
L 2
Av = gm1 (ro1 k RG k ro2 )

RG = 10 (ro1 k ro2 )
1
ro1 =
= 6 k
n ID1
1
= 3 k
ro2 =
p |ID2 |

RG = 10 (ro1 k ro2 ) = 20 k
s

W
Av = 2n Cox
ID1 (ro1 k RG k ro2 )
L 1

W
L

= 15
= 102.1
1

VIN = VGS1 = VT H +
= 0.787 V

n Cox

2I
D
(1 + n VDS1 )

W
L 1

7.66
P = VDD ID1 = 1 mW
ID1 = |ID2 | = 556 A

p
W
Vov1 = VGS1 VT H = 2ID n Cox
= 200 mV
L 1

W
= 138.9
L 1
gm1
Av =
gm2
q

2n Cox W
L 1 ID1
= q

2n Cox W
L 2 |ID2 |
v
u W
u L
1
= t W
L

W
L

= 4

= 8.68

VIN = VGS1 = Vov1 + VT H = 0.6 V

7.67
P = VDD ID = 3 mW
ID = I1 = 1.67 mA
1
1
=q
Rin =
gm
2 C
n

W
ox L ID

W
= 600
L

Av = gm RD =
RD = 250

1
RD = 5
50

= 50

7.68
P = VDD ID = 2 mW
ID = 1.11 mA
VD = VG VT H + 100 mV
VDD ID RD = VG VT H + 100 mV
VG = VDD

2ID
RD = 4
VGS VT H
VGS VT H
RD = Av
2ID
VGS VT H
= VDD VT H + 100 mV
ID Av
2ID
VGS = 0.55 V
Av = gm RD =

VDD

RD = 270
VS = VDD VGS = ID RS
RS = 1.125 k
2ID
W
=
2 = 493.8
L
n Cox (VGS VT H )

7.73
P = VDD ID1 = 3 mW
ID1 = ID2 = 1.67 mA
Av =
=

ro1 k ro2
gm1 + ro1 k ro2
1

ro1 k ro2
1
q
+ ro1
2n Cox ( W
L ) ID1
1

k ro2

= 0.9
1
= 6 k
ro1 = ro2 =
ID1

W
= 13.5
L 1
Let Vov2 = VGS2 VT H = 0.3 V. Lets assume that VOUT = VDS2 = Vov2 .

VGS2 = Vb = Vov2 + VT H = 0.7 V

2ID2
W
=
2
L 2
n Cox (VGS2 VT H ) (1 + VDS2 )
= 161

VGS1 = VT H +

n Cox

2ID1

W
L 1 (1

VDS1 = VDD VDS2 = 1.5 V

VGS1 = 1.44 V

VIN = VGS1 + VDS2 = 1.74 V

+ VDS1 )

Vout (V)

8.1

4
Vin

5
(mV)

8.11
V = V+ = Vin
R2
R4 k (R2 + R3 )
Vout = Vin
R1 + R4 k (R2 + R3 ) R2 + R3
1

R2
R4 k (R2 + R3 )
=
R1 + R4 k (R2 + R3 ) R2 + R3

V =
Vout
Vin

(R2 + R3 ) [R1 + R4 k (R2 + R3 )]

R2 [R4 k (R2 + R3 )]

If R1 0, we expect the result to be:

R2
Vout
R2 + R3
R2 + R3
R3
=
=1+
R2
R2

Vin =

Vout
Vin R1 =0

Taking limit of the original expression as R1 0, we have:

(R2 + R3 ) [R1 + R4 k (R2 + R3 )]
(R2 + R3 ) [R4 k (R2 + R3 )]
=
R1 0
R2 [R4 k (R2 + R3 )]
R2 [R4 k (R2 + R3 )]
R3
=1+
R2
lim

This agrees with the expected result. Likewise, if R3 0, we expect the result to be:
R2 k R4
Vout
R1 + R2 k R4
R1 + R2 k R4
=
R2 k R4
R1
=1+
R2 k R4

Vin =

Vout
Vin R3 =0

Taking the limit of the original expression as R3 0, we have:

lim

R3 0

(R2 + R3 ) [R1 + R4 k (R2 + R3 )]

R2 (R1 + R2 k R4 )
=
R2 [R4 k (R2 + R3 )]
R2 (R2 k R4 )
R1 + R2 k R4
=
R2 k R4
R1
=1+
R2 k R4

This agrees with the expected result.

8.14 We need to derive the closed-loop gain of the following circuit:

R1
R2

Rout
+

+
vin

A0 vX

vX

vout

R2
+ vin
R1 + R2
R1 + R2
+ vin
= (A0 vX vin )
Rout + R1 + R2




R1 + R2
R2
+ vin vin
+ vin
= A0 (vout vin )
R1 + R2
Rout + R1 + R2

vX = (vout vin )
vout

Grouping terms, we have:

R2
R1 + R2
R2
R1 + R2
Rout + R1 + R2
vout 1 + A0
= vin
A0
A0 1 +
R1 + R2 Rout + R1 + R2
Rout + R1 + R2
R1 + R2
R1 + R2



R1 + R2
R1
Rout + R1 + R2
= vin
A0
1
Rout + R1 + R2
R1 + R2
R1 + R2
1
[Rout + R1 + R2 A0 R1 R1 R2 ]
= vin
Rout + R1 + R2


A0 R1 + R1 + R2
= vin 1
Rout + R1 + R2
R1 +R1 +R2
1 AR0out
vout
+R1 +R2
=
0 R2
vin
1 + RoutA+R
1 +R2

=
=

Rout + R1 + R2 A0 R1 R1 R2
Rout + R1 + R2 + A0 R2
Rout A0 R1
Rout + R1 + (1 + A0 ) R2

To find the output impedance, we must find Zout =

vt
it

for the following circuit:

R1
R2

Rout
+

+
A0 vX

vX

it

vt

vt
vt + A0 vX
+
Rout
R1 + R2
R2
vX =
vt
R1 + R2
2
vt
vt + A0 R1R+R
vt
2
+
it =
Rout
R1 + R2


A0 R2
1
1
+
+
= vt
Rout
Rout (R1 + R2 ) R1 + R2
R1 + (1 + A0 ) R2 + Rout
= vt
Rout (R1 + R2 )
it =

Zout =

Rout (R1 + R2 )
vt
=
it
R1 + (1 + A0 ) R2 + Rout

8.15 Refer to the analysis for Fig. 8.42.

Vout R1


Vin = R2 = 4

Rin R2 = 10 k
R1 = 4R2 = 40 k

From Eq. (8.99), we have

E =1

A0
1+

A0 = 1000
Rout = 1 k
E = 0.51 %

Rout
R2

Rout
R1

+ A0 +

R1
R2

8.17
V+ = V (since A0 = )
Vin
Vout
R3 k R4
=
R2
R3 R1 + R3 k R4
Vout
R3 R1 + R3 k R4
=
Vin
R2
R3 k R4
If R1 0 or R3 0, we expect the amplifier to reduce to the standard inverting amplifier.

R3
Vout
=

Vin R1 0
R2


R1
Vout
=
Vin
R2
R3 0

The gain reduces to the expected expressions.

8.18
V+ = V (since A0 = )
R3
R2
VX =
Vout =
(Vout Vin ) + Vin
R3 + R4
R1 + R2




R3
R2
R2
Vout
= Vin 1

R3 + R4
R1 + R2
R1 + R2




R1
R3 (R1 + R2 ) R2 (R3 + R4 )
= Vin
Vout
(R1 + R2 ) (R3 + R4 )
R1 + R2
Vout
R1 (R3 + R4 )
=
Vin
R3 (R1 + R2 ) R2 (R3 + R4 )

8.22 We must find the transfer function of the following circuit:

C1
R1

vout

+
vin

Rin

+
vX

A0 vX

vout = A0 vX


1
vX vin
vX
vX = vout
+
sC1 Rin
R1


vin
1
1
= vout +
+
vX 1 +
sRin C1
sR1 C1
sR1 C1
sR1 Rin C1 vout + Rin vin
vX =
sR1 Rin C1 + R1 + Rin
sR1 Rin C1 vout + Rin vin
vout = A0
sR1 Rin C1 + R1 + Rin


Rin
sR1 Rin C1
= A0 vin
vout 1 + A0
sR1 Rin C1 + R1 + Rin
sR1 Rin C1 + R1 + Rin
vout
A0 Rin
sR1 Rin C1 + R1 + Rin
=

vin
sR1 Rin C1 + R1 + Rin sR1 Rin C1 + R1 + Rin + sR1 Rin C1 A0
A0 Rin
=
sR1 Rin C1 + R1 + Rin + sR1 Rin C1 A0
A0 Rin
=
sR1 Rin C1 (1 + A0 ) + R1 + Rin
A0 Rin
=
1 (1+A0 )
1 + s R1 RRin1C+R
in
=

A0 Rin / (R1 + Rin )

1 + s (R1 k Rin ) C1 (1 + A0 )

sp =

1
(R1 k Rin ) C1 (1 + A0 )

Comparing this to the result in Eq. (8.37), we can see that we can simply replace R1 with R1 k Rin ,
effectively increasing the pole frequency (since R1 k Rin < R1 for finite Rin ).
We can also write the result as
sp =

1
R1 C1 (1 + A0 )

1+

R1
Rin

In this form, its clear that the pole frequency increases by 1 + R1 /Rin .

8.23 We must find the transfer function of the following circuit:

C1
R1

Rout
+

+
vin

A0 vX

vX

vout

vout = A0 vX +

vin vout
Rout
R1 + sC1 1

R1
(vout vin )
R1 + sC1 1
"
#
R1
vin vout
vout = A0 vin +
(vout vin ) +
Rout
R1 + sC1 1
R1 + sC1 1
"
"
#
#
A0 R1 + Rout
A0 R1 + Rout
vout 1 +
= vin A0 +
R1 + sC1 1
R1 + sC1 1
vX = vin +

vout

R1 +

1
sC1

+ A0 R1 + Rout

R1 +

1
sC1

= vin

A0 R1 A0 sC1 1 + A0 R1 + Rout
R1 +

1
sC1

vout {1 + sC1 [(1 + A0 ) R1 + Rout ]} = vin {A0 sC1 Rout }

A0 sC1 Rout
vout
=
vin
1 + sC1 [(1 + A0 ) R1 + Rout ]
sp =

1
C1 [(1 + A0 ) R1 + Rout ]

Comparing this to the result in Eq. (8.37), we can see that the pole gets reduced in magnitude due to
Rout .

8.26 We must find the transfer function of the following circuit:

R1
C1
vout
+
vin

+
Rin

+
A0 vX

vX

vout = A0 vX


vX vout
vX = (vin vX ) sC1
Rin
R1


Rin
Rin
= vin sRin C1 + vout
vX 1 + sRin C1 +
R1
R1
vX =

vin sRin C1 + vout RRin

1
1 + sRin C1 +

vout = A0
"

vout 1 +

A0 RRin
1
1 + sRin C1 +

Rin
R1
Rin
R1

vin sRin C1 + vout RRin

1
1 + sRin C1 +

= vin

sRin C1 A0
1 + sRin C1 + RRin
1

= vin

sRin C1 A0
1 + sRin C1 + RRin
1

vout

1 + sRin C1 + (1 + A0 )

vout

Rin
1 + sRin C1 + (1 + A0 )
= vin sRin C1 A0
R1

1 + sRin C1 +

Rin
R1

"

Rin
R1

Rin
R1

vout
sR1 Rin C1 A0
=
vin
R1 + sR1 Rin C1 + (1 + A0 ) Rin
vout
lim
= sR1 C1
A0 vin
Comparing this to Eq. (8.42), we can see that if we let A0 , the result actually reduces to Eq.
(8.42).

8.27 We must find the transfer function of the following circuit:

R1
C1

Rout
+

+
vin

A0 vX

vX

vout = A0 vX +
vX = vin +

vin vout
Rout
R1 + sC1 1

1
sC1

R1 +
"

vout = A0 vin +
"

vout 1 +
vout

R1 +

1
sC1

A0 sC1 1 + Rout
R1 +

1
sC1

+ A0 sC1 1 + Rout

R1 +

1
sC1

"

= vin A0 +
= vin

vout

1
sC1

(vout vin )
1
sC1

R1 +

1
sC1

(vout vin ) +

A0 sC1 1 + Rout
R1 +

1
sC1

vin vout
Rout
R1 + sC1 1

A0 R1 A0 sC1 1 + A0 sC1 1 + Rout

R1 +

1
sC1

vout {1 + A0 + sC1 (R1 + Rout )} = vin {sC1 (A0 R1 Rout )}

vout
sC1 (A0 R1 Rout )
=
vin
1 + A0 + sC1 (R1 + Rout )
vout
= sR1 C1
lim
A0 vin
Comparing this to Eq. (8.42), we can see that if we let A0 , the result actually reduces to Eq.
(8.42).

8.28
vout = A0 v
v = vin + (vout vin )

1
sC1
1
sC1

k R1

vout = A0 vin + (vout vin )

1
sC1

k R1


+ sC1 2 k R2

k R1


k R1 + sC1 2 k R2

1
sC1

1
k R1
sC1 k R1

= vin A0 1


vout 1 + A0
1
1
1
1
+
+
k
R
k
R
k
R
k
R
1
2
1
2
sC1
sC2
sC1
sC2









1
1
1
1
1
1
k
R
k
R
k
R
k
R
k
R
k
R
+
+
A
+

1
2
1
1
2
1
0 sC1
sC1
sC2
sC1
sC2
sC1






= vin A0
vout
1
1
1
1
sC1 k R1 + sC2 k R2
sC1 k R1 + sC2 k R2






1
1
1
vout (1 + A0 )
= vin A0
k R1 +
k R2
k R2
sC1
sC2
sC2

1
sC1

1
k R2
vout

sC2
= A0
vin
(1 + A0 ) sC1 1 k R1 + sC1 2 k R2

Unity gain occurs when the numerator and denominator are the same (note that we can drop the
negative sign since we only care about the magnitude of the gain):





1
1
1
k R2 = (1 + A0 )
k R1 +
k R2
A0
sC2
sC1
sC2




1
1
k R2 = (1 + A0 )
k R1
(A0 1)
sC2
sC1


1
sC2 k R2
A +1

= 0
1
A
01
kR
sC1

It is possible to obtain unity gain by choosing the resistors and capacitors according to the above
formula.

8.31
vout = A0 vX
v1 vX
v2 vX
vX vout
+
=
R2
R1
RF
vout
v1
v2
vX
+
+
=
RF
R2
R1
R1 k R2 k RF


vout
v1
v2
vout = A0 (R1 k R2 k RF )
+
+
RF
R2
R1




v2
v1
(R1 k R2 k RF )
= A0 (R1 k R2 k RF )
+
vout 1 + A0
RF
R2
R1
v1
v2
R2 + R1
vout = A0 (R1 k R2 k RF )
2 kRF )
1 + A0 (R1 kR
RF
= A0 RF (R1 k R2 k RF )
=

v1
v2
+
R2
R1

v1
R2

v2
R1

RF + A0 (R1 k R2 k RF )

[RF k A0 (R1 k R2 k RF )]

8.32 For A0 = , we know that v+ = v , meaning that no current flows through RP . Thus, RP will have
no effect on vout .
vout = RF

v1
v2
+
R2
R1

, A0 =

For A0 < , we have to include the effects of RP .

vout = A0 vX


v2 vX
vout vX
v1 vX
RP
+
+
vX =
R2
R1
RF


1
v1
1
1
1
v2
vout
vX
=
+
+
+
+
+
RP
R1
R2
RF
R2
R1
RF


v2
vout
v1
(R1 k R2 k RF k RP )
+
+
vX =
R2
R1
RF


v1
v2
vout
vout = A0
(R1 k R2 k RF k RP )
+
+
R2
R1
RF




v1
v2
A0
(R1 k R2 k RF k RP )
(R1 k R2 k RF k RP ) = A0
+
vout 1 +
RF
R2
R1


v1
v2
(R1 k R2 k RF k RP )
vout = A0
+
A0
R2
R1 1 + R
(R1 k R2 k RF k RP )
F


v1
v2
RF A0 (R1 k R2 k RF k RP )
=
+
R2
R1 RF + A0 (R1 k R2 k RF k RP )


v1
v2
[RF k A0 (R1 k R2 k RF k RP )] , A0 <
+
=
R2
R1

8.33 We must find vout for the following circuit:

v1

R2

RF
Rout

v2

R1

vout

+
A0 vX

vX

v1 vX
v2 vX
vout = A0 vX +
Rout
+
R2
R1




v1
Rout
v2
Rout
+ Rout
+
+
= vX A0 +
R1
R2
R2
R1


v1 vX
v2 vX
vX = vout +
RF
+
R2
R1


vout
1
1
v1
v2
1
=
+
+
+
+
vX
RF
R1
R2
RF
R2
R1


vout
v1
v2
vX =
(R1 k R2 k RF )
+
+
RF
R2
R1






v1
Rout
v1
v2
Rout
v2
vout
(R1 k R2 k RF ) A0 +
+ Rout
+
+
+
+
vout =
RF
R2
R1
R1
R2
R2
R1
Grouping terms, we have:

(R1 k R2 k RF ) A0 +
vout 1 +
RF

Rout
R1 kR2

v1
Rout
v2
(R1 k R2 k RF ) A0 +
+ Rout
+
R1 k R2
R2
R1





Rout
v2
v1
(R1 k R2 k RF ) A0 +
+ Rout
+
=
R2
R1
R1 k R2


Rout


v1
v2 Rout + (R1 k R2 k RF ) A0 + R1 kR2


= RF
+
R2
R1 R + (R k R k R ) A + Rout
F
1
2
F
0
R1 kR2

vout

v2
v1
+
R2
R1

8.34 We must find vout for the following circuit:

v1

R2

RF

vout
v2

R1

Rin

+
A0 vX

vX

RP

vout = A0 vX

v1 vX 1 +
vX =
R1

RP
Rin

v2 vX 1 +
R2

Grouping terms, we have:

1
RP
1
vX
=
+ 1+
Rin
Rin R1 k R2 k RF


(R1 k R2 k RF ) + RP + Rin
vX
=
Rin (R1 k R2 k RF )
vX
vout

RP
Rin

vout vX 1 +
RF

RP
Rin

Rin

v1
v2
vout
+
+
R2
R1
RF
v1
v2
vout
+
+
R2
R1
RF


v2
vout
Rin (R1 k R2 k RF )
v1
+
+
=
R2
R1
RF (R1 k R2 k RF ) + RP + Rin


v1
v2
vout
Rin (R1 k R2 k RF )
= A0
+
+
R2
R1
RF (R1 k R2 k RF ) + RP + Rin

Grouping terms, we have:

A0
Rin (R1 k R2 k RF )
v2
v1
A0 Rin (R1 k R2 k RF )
=
vout 1 +
+
RF (R1 k R2 k RF ) + RP + Rin
R2
R1 (R1 k R2 k RF ) + RP + Rin




v1
v2
A0 Rin (R1 k R2 k RF )
RF [(R1 k R2 k RF ) + RP + Rin ] + A0 Rin (R1 k R2 k RF )
=
+
vout
RF [(R1 k R2 k RF ) + RP + Rin ]
R2
R1 (R1 k R2 k RF ) + RP + Rin
Simplifying, we have:
vout =

v1
v2
+
R2
R1

A0 RF Rin (R1 k R2 k RF )
RF [(R1 k R2 k RF ) + RP + Rin ] + A0 Rin (R1 k R2 k RF )

8.35
ID1 =

Vin
R1

Vin > 0
Vin < 0

Plotting ID1 (t), we have

ID1 (t)

V0 /R1

0
t

V0

Vin (t) = V0 cos(t) (Dotted)

V0

8.36
ID1 =

Vin
R1

Vin > 0
Vin < 0

Plotting ID1 (t), we have

ID1 (t)

V0 /R1

0
t

V0

Vin (t) = V0 cos(t) (Dotted)

V0

8.37
VY =

Vin VD,on
VDD

Vin < 0
Vout
Vin > 0

Vin
0

Vin < 0
ID1 =
Vin > 0

Vin
R1

Vin < 0
Vin > 0

Plotting VY (t) and Vout (t), we have

Vin (t) = V0 cos(t)

VY (t)
Vout (t)
VDD

V0

/
t

V0

Plotting ID1 (t), we have:

ID1 (t)
V0 /R1

/
0
t
/
V0

V0

Vin (t) = V0 cos(t) (Dotted)

8.38 Since the negative feedback loop is never broken (even when the diode is off, RP provides negative
feedback), V+ = V will always hold, meaning VX = Vin .
We must determine when D1 turns on/off to determine VY . We know that for Vin < 0, the diode will
be off, and VX will follow Vin . As Vin begins to go positive, the diode will remain off until
Vin

RP
> VD,on
R1

Once the diode turns on, VY will be fixed at Vin + VD,on . Thus, we can write:
VX = Vin


(
R1
P
Vin < VD,on R
Vin 1 + R
R1
P
VY =
R1
Vin + VD,on
Vin > VD,on R
P
Plotting VY (t) and Vout (t), we have

Vin (t) = V0 cos(t)

VX (t)
VY (t)
V0 + VD,on
V0

/
t

V0

V0 (1 + RP /R1 )

8.40 Note that although in theory the output is unbounded (i.e., by Eq. (8.66), we can take the logarithm
of an arbitrarily small positive number), in reality the output will be limited by the positive supply
rail, as shown in the following plot.

Vout
VX

VDD

0
1

R1 IS

1
Vin (V)

8.42 When Vin > 0, the feedback loop will be broken, and the output will go to the positive rail.
When Vin < 0, we have:
Vin
= IS eVBE /VT = IS eVout /VT
R1


Vin
= VT ln
R1 IS

IC =
Vout

Vout (V)

This gives us the following plot of Vout vs. Vin :

R1 IS

VDD

Note that this circuit fails to behave as a non-inverting logarithmic amplifier.

1
Vin (V)

8.44 (a)

Vin
Vout = VT ln
R1 IS


1V
0.2 V = VT ln
R1 IS
R1 IS = 456 V
(b)

dVout
dVin Vin =1 V

VT
=
Vin

Av =

Vin =1 V

= 0.026

8.45 When Vin < VT H , the output goes to the positive rail. When Vin > VT H , we have:
ID =

Vin VT H
R1

VGS = Vout = VT H +

Vout = VT H

W
L

2ID
n Cox

2 (Vin VT H )
R1 W
L n Cox

s
R1 W
2
1
dVout
L n Cox
=
dVin
2 2 (Vin VT H ) R1 W
L n Cox
s
1
=
, Vin > VT H
2R1 W

C
L n ox (Vin VT H )

8.46 When Vin > 0, the output goes to the negative rail. When Vin < 0, we have:
ID =

Vin
R1

VSG = Vout = |VT H | +

Vout = VT H +

2 |ID |
p Cox

W
L

2Vin
, Vin < 0
R1 W
L p Cox

8.49 We model an input offset with a series voltage source at one of the inputs.
R1
R2

Vin

Vout

Vos +

Vin Vos
Vout = Vin
(R1 + R2 )
R2


R1 + R2
R1 + R2
+ Vos
= Vin 1
R2
R2


R1
R1
= Vin + 1 +
Vos
R2
R2
Note that even when Vin = 0, Vout = (1 + R1 /R2 ) Vos .

8.54 Let Vin = 0.

V+ = IB1 (R1 k R2 ) = (IB2 + I) (R1 k R2 ) = V


V
Vout = V + IB2 +
R1
R2


(IB2 + I) (R1 k R2 )
R1
= (IB2 + I) (R1 k R2 ) + IB2
R2


R1
= (IB2 + I) (R1 k R2 ) 1 +
+ IB2 R1
R2
= IR1

If the magnitude of the error must be less than V , we have:

IR1 < V
R1 <
Note that this does not depend on R2 .

V
I

8.57
Vout =

A0
V
1 + s0

V = Vin +

Vout Vin
R1
R1 + sC1 1

Vout Vin
Vin +
R1
Vout
R1 + sC1 1
"
#
#
"
A0
A0
R1
R1
Vout 1 +
=
1
Vin
1 + s0 R1 + sC1 1
1 + s0
R1 + sC1 1



1 + s0
R1 + sC1 1 + A0 R1
A0 sC1 1





= Vin
Vout
1 + s0
1 + s0
R1 + sC1 1
R1 + sC1 1
A0
=
1 + s0

A0 sC1 1


s
R1 + sC1 1 + A0 R1
0

Vout
=
Vin
1+
=

A0

s
0

1+

(1 + sR1 C1 ) + sA0 R1 C1
A0

1 + s R1 C1 +
=

If 0

1
R1 C1 ,

1
0

1
+ A0 R1 C1 + s2 R1 C
0

A0
h
1 + s (1 + A0 ) R1 C1 +

we have:
Vout
=
Vin
=

1
h

1
A0

+s

1
A0

+s 1+

1+

1
A0

1
A0

1

R1 C1 +

1
0

1 C1
+ s2 R
A0 0

1 C1
R1 C1 + s2 R
A0 0

1
(assuming A0 1)
1 C1
sR1 C1 + s2 R
A0 0

1

sR1 C1 1 +

s
A0 0

1
0

1
+ s2 R1 C
0

8.61 Let E refer to the gain error.

R1
=8
R2
R1 = 8 k
R2 = 1 k
A0 RRout
R1
vout
1
=
vin
R2 1 + RRout + A0 +
2

R1
(1 E)
R2
A0 RRout
1
E =1
+
A
1 + RRout
0+
2

R1
R2

(Eq. 8.99)

R1
R2

= 0.1 %
A0 = 9103
Note that we can pick any R1 , R2 such that their ratio is 8 (i.e., this solution is not unique). However,
A0 will change depending on the values chosen.

8.66

dVout
dVin

Vin
R1 IS
R1 IS 1
= VT
Vin R1 IS
VT
=
Vin

Vout = VT ln

out
VT
No, it is not possible to satisfy both requirements. As shown above, dV
dVin = Vin , meaning for a
specified temperature and input, the gain is fixed. Assuming we could fix the temperature as part of
the design, we could still only meet one of the two constraints, since the temperatures at which the
constraints are met are not equal.

9.7 Let R2 be the resistance seen looking into the collector of Q2 .

Rout = ro1 + (1 + gm1 ro1 ) (r1 k R2 )
Note that this expressoin is maximized as R2 . This gives us
Rout,max = ro1 + (1 + gm1 ro1 ) r1

9.9
1 VA VA VT
(Eq. 9.9)
IC1 VT VA + VT
1 VA
VT
=
IC1 VT
VA
=
IC1

Rout

= ro
This resembles Eq. (9.12) because the assumption that
VA VT
can be equivalently expressed as
VT
VA

IC
IC
ro r
This is the same assumption used in arriving at Eq. (9.12).

9.12
ID = 0.5 mA
Rout = ro1 + (1 + gm1 ro1 ) ro2
!
r
1
1
1
W
=
+ 1 + 2 n Cox ID
ID
L
ID ID
50 k
0.558 V1

9.15 (a)
VD1 = VDD ID RD = 1.3 V > VG1 VT H = Vb1 VT H
Vb1 < 1.7 V
(b)
Vb1 = 1.7 V
VGS1 = Vb1 VX
s
= VT H +

= 0.824 V
VX = 0.876 V

2I
D
n Cox

W
L 1

9.16 (a) Looking down from the source of M1 , we see an equivalent resistance of
Rout = gm1 ro1

1
gm2

k ro2

1
gm2

k ro2 . Thus, we have

(b)
Rout = gm1 ro1 ro2
(c) Putting two transistors in parallel, their transconductances will add and their output resistances
will be in parallel (i.e., we can treat M1 and M3 as a single transistor with gm = gm1 + gm3 and
ro = ro1 k ro3 ). This can be seen from the small-signal model.
Rout = (gm1 + gm3 ) (ro1 k ro3 ) ro2
(d) Lets draw the small-signal model and apply a test source to find Rout .
+

vgs1

gm1 vgs1

ro1

vgs2

gm2 vgs2

+
it

vt

ro2

vgs1
vgs2 + vgs1
= gm1 vgs1 +
ro2
ro1
vgs1 = gm2 ro2 vt it ro2
vt + gm2 ro2 vt it ro2
it = gm1 (gm2 ro2 vt it ro2 ) +
ro1




ro2
1 + gm2 ro2
it 1 + gm1 ro2 +
= vt gm1 gm2 ro2 +
ro1
ro1
it = gm2 vgs2

it (gm1 ro1 ro2 ) = vt (gm1 gm2 ro1 ro2 )

Rout =

1
vt
=
it
gm2

9.17
ID = 0.5 mA
Rout = ro1 + (1 + gm1 ro1 ) ro2
s
!
W
1
1
1
=
p Cox ID
+ 1+ 2
ID
L 1
ID ID

W
L

= 40 k

W
=
= 8
L 2

9.20 (a)
Gm = gm1
Rout =

k ro1

gm2

Av = gm1

1
gm2

k ro1

(b)
Gm = gm2
Rout =

k ro2 k ro1

gm2

Av = gm2

1
gm2

k ro2 k ro1

(c) Lets draw the small-signal model to find Gm .

iout
vin

r1

+
v1

gm1 v1

RE

ro1

vin v1
v1
+
r1
RE
v1 = vin + (iout gm1 v1 ) ro1
v1 (1 + gm1 ro1 ) = vin + iout ro1
vin + iout ro1
v1 =
1 + gm1 ro1
vin + iout ro1
vin
vin + iout ro1

+
iout =
r1 (1 + gm1 ro1 ) RE
RE (1 + gm1 ro1 )




ro1
1
1
ro1
1
iout 1 +
= vin

r1 (1 + gm1 ro1 ) RE (1 + gm1 ro1 )

RE
r1 (1 + gm1 ro1 ) RE (1 + gm1 ro1 )
r1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 r1
r1 (1 + gm1 ro1 ) RE r1
iout
= vin
r1 RE (1 + gm1 ro1 )
r1 RE (1 + gm1 ro1 )
iout [r1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 r1 ] = vin [r1 (1 + gm1 ro1 ) RE r1 ]
iout
Gm =
vin
iout =

r1 (1 + gm1 ro1 ) RE r1
r1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 r1
gm1
(if r1 , ro1 are large)

1 + gm1 RE
= ro2 k [ro1 + (1 + gm1 ro1 ) (r1 k RE )]
=

Rout

Av =

r1 RE (1 + gm1 ro1 ) RE r1
{ro2 k [ro1 + (1 + gm1 ro1 ) (r1 k RE )]}
r1 RE (1 + gm1 ro1 ) + ro1 RE + ro1 r1

(d)
Gm = gm2
Rout = ro2 k [ro1 + (1 + gm1 ro1 ) (r1 k RE )]
Av = gm2 {ro2 k [ro1 + (1 + gm1 ro1 ) (r1 k RE )]}
(e) Lets draw the small-signal model to find Gm .
iout
+
vgs1

gm1 vgs1

RS

vin

ro1

Since the gate and drain are both at AC ground, the dependent current source looks like a resistor
with value 1/gm1 . Thus, we have:
Gm =

1
iout
=
1
vin
k ro1
RS + gm1

RS +

ro1
1+gm1 ro1

1 + gm1 ro1
ro1 + RS + gm1 ro1 RS
gm1

(if ro1 is large)

1 + gm1 RS
= [ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]
=

Rout

Av =

1 + gm1 ro1
{[ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]}
ro1 + RS + gm1 ro1 RS

(f) We can use the result from part (c) to find Gm here. If we simply let r (and obviously we
replace the subscripts as appropriate) in the expression for Gm from part (c), well get the result
we need here.
r2 RE (2 + gm2 ro2 ) RE r2
r2 RE (2 + gm2 ro2 ) + ro2 RE + ro2 r2
gm2 ro2
=
ro2 + RE + gm2 ro2 RE
gm2

(if ro2 is large)

1 + gm2 RE
= [ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]

Gm = lim

r2

Rout

Av =

gm2 ro2
{[ro2 + (1 + gm2 ro2 ) RE ] k [ro1 + (1 + gm1 ro1 ) RS ]}
ro2 + RE + gm2 ro2 RE

(g) Once again, we can use the result from part (c) to find Gm here (replacing subscripts as appropriate).
r2 RE (1 + gm2 ro2 ) RE r2
r2 RE (1 + gm2 ro2 ) + ro2 RE + ro2 r2
gm2

(if r2 , ro2 are large)

1 + gm2 RE
= RC k [ro2 + (1 + gm2 ro2 ) (r2 k RE )]

Gm =

Rout

Av =

r2 RE (1 + gm2 ro2 ) RE r2
{RC k [ro2 + (1 + gm2 ro2 ) (r2 k RE )]}
r2 RE (1 + gm2 ro2 ) + ro2 RE + ro2 r2

9.22
Av = gm1 [ro2 + (1 + gm2 ro2 ) (r2 k ro1 )]
IC1 IC2 = I1

VA1 = VA2 = VA




I1 VA
VA
VT VA
Av
+ 1+
k
VT I1
VT
I1
I1
= 500

VA1 = VA2 = 0.618 V1

9.23 (a) Although the output resistance of this stage is the same as that of a cascode, the transconductance
of this stage is lower than that of a cascode stage. A cascode has Gm = gm , where as this stage
m2
has Gm = 1+ggm2
ro1 .
(b)
Gm =

gm2
1 + gm2 ro1

Rout = ro2 + (1 + gm2 ro2 ) (r2 k ro1 )

Av = Gm Rout
=

gm2
[ro2 + (1 + gm2 ro2 ) (r2 k ro1 )]
1 + gm2 ro1

9.24
Gm = gm1
Rout = ro2 + (1 + gm2 ro2 ) (r2 k ro1 )
Av = gm1 [ro2 + (1 + gm2 ro2 ) (r2 k ro1 )]

9.25 (a)
Gm = gm2

RP k r1
gm1 + RP k r1
1

Rout = ro1 + (1 + gm1 ro1 ) (r1 k ro2 k RP )

Av = gm2

RP k r1
[ro1 + (1 + gm1 ro1 ) (r1 k ro2 k RP )]
gm1 + RP k r1
1

(b)
Gm = gm2
Rout = ro1 k RP + [1 + gm1 (ro1 k RP )] (r1 k ro2 )
Av = gm2 {ro1 k RP + [1 + gm1 (ro1 k RP )] (r1 k ro2 )}
(c)
gm2
1 + gm2 RE
= ro1 + (1 + gm1 ro1 ) [r1 k (ro2 + (1 + gm2 ro2 ) (r2 k RE ))]

Gm =
Rout

Av =

gm2
{ro1 + (1 + gm1 ro1 ) [r1 k (ro2 + (1 + gm2 ro2 ) (r2 k RE ))]}
1 + gm2 RE

(d)
Gm = gm2
Rout = ro1 + (1 + gm1 ro1 ) (r1 k ro2 k ro3 )
Av = gm2 [ro1 + (1 + gm1 ro1 ) (r1 k ro2 k ro3 )]

9.26
Av = gm1 {[ro2 + (1 + gm2 ro2 ) (r2 k ro1 )] k [ro3 + (1 + gm3 ro3 ) (r3 k ro4 )]}







IC
VA,N
VA,P
VA,N
N VT VA,N
VA,P
P VT VA,P
=
k
+ 1+
k
+ 1+
k
VT
IC
VT
IC
IC
IC
VT
IC
IC

i h

i
h


VA,P
VA,N
VA,N
VA,P
VA,P
VA,N
N VT
P VT
k IC
k IC
IC + 1 + VT
IC
IC + 1 + VT
IC
IC

i h

i


h
=
V
V
V
VA,P
N VT
P VT
VT VA,N + 1 + VA,N
+ IA,P
k A,N
+ 1 + VA,P
IC
VT
IC
IC
IC k IC
C
T
#"
#
"




N VT VA,N
P VT VA,P
VA,P
VA,N
VA,P
VA,N

V
VA,P
N VT
P VT
IC + 1 + VT
IC + 1 + VT
2
2
IC
IC
+ A,N
IC
IC
IC + IC
IC
# "
#
"
=




VT V

V
V

V
V
V
V
V
N
T
A,N
P
T
A,P
A,P
A,N
A,P
A,N
+

VA,N
VA,P
N VT
P VT
IC + 1 + VT
IC + 1 + VT
2
2
IC

IC

IC

IC

IC

IC

ih


i
V
N VT VA,N
P VT VA,P
VA,P
1
VA,N + 1 + VA,N
V
+
1
+
2
A,P

V
+V
V

V
+V
IC
IC
T
N T
A,N
T
P T
A,P
h


i
h


i
=
VT 1 VA,N + 1 + VA,N N VT VA,N + 1 VA,P + 1 + VA,P P VT VA,P
IC
VT
N VT +VA,N
IC
VT
P VT +VA,P
h


ih


i
VA,N
VA,P
N VT VA,N
P VT VA,P
V
+
1
+
V
+
1
+
A,N
A,P
VT
N VT +VA,N
VT
P VT +VA,P
1
h


i h


i
=
VA,N
VA,P
N VT VA,N
P VT VA,P
VT V
+
1
+
+
V
+
1
+
A,N
A,P
VT
N VT +VA,N
VT
P VT +VA,P

The result does not depend on the bias current.

9.28

|Av |

Av gm1 gm2 ro1 ro2 (Eq. 9.69)

s
s

2
W
W
1
= 2
n Cox ID 2
n Cox ID
L 1
L 2
ID
s
2
W
1
W
= 2n Cox ID
L 1 L 2 ID
s
1 1
W
W
= 2n Cox
2
ID
L 1 L 2

ID

9.30 From Problem 28, we have

1 1
Av = 2n Cox
ID 2

s

W
L

1

W
L

If we increase the transistor widths by a factor of N , we will get a new voltage gain Av :
s

W
W
1 1

2
N
Av = 2n Cox
ID 2
L 1 L 2
s
1 1
W
W
= 2N n Cox
2
ID
L 1 L 2
= N Av
Thus, the gain increases by a factor of N .

9.31 From Problem 28, we have

1 1
Av = 2n Cox
ID 2

s

W
L

1

W
L

If we decrease the transistor widths by a factor of N , we will get a new voltage gain Av :
s

W
W
1 1
1

Av = 2n Cox
ID 2 N 2 L 1 L 2
s
1
W
1 1
W
= 2 n Cox
2
N
ID
L 1 L 2
=

1
Av
N

Thus, the gain decreases by a factor of N .

9.32
Gm = gm2
Rout = ro2 k [ro3 + (1 + gm3 ro3 ) ro4 ]
Av = gm2 {ro2 k [ro3 + (1 + gm3 ro3 ) ro4 ]}

9.33
Av = gm1 {[ro2 + (1 + gm2 ro3 ) ro1 ] k [ro3 + (1 + gm3 ro3 ) ro4 ]}
= 500
s
W
gm1 = gm2 = 2
n Cox ID
L
s
W
p Cox ID
gm3 = gm4 = 2
L
1
n ID
1
=
p ID

ro1 = ro1 =
ro3 = ro4

ID = 1.15 mA

9.34 (a)
Gm = gm1
Rout = [(ro2 k RP ) + (1 + gm2 (ro2 k RP )) ro1 ] k [ro3 + (1 + gm3 ro3 ) ro4 ]
Av = gm1 {[(ro2 k RP ) + (1 + gm2 (ro2 k RP )) ro1 ] k [ro3 + (1 + gm3 ro3 ) ro4 ]}
(b)
Gm = gm1

ro1 k RP
gm2 + ro1 k RP
1

Rout = [ro2 + (1 + gm2 ro2 ) (ro1 k RP )] k [ro3 + (1 + gm3 ro3 ) ro4 ]

Av = gm1

ro1 k RP
{[ro2 + (1 + gm2 ro2 ) (ro1 k RP )] k [ro3 + (1 + gm3 ro3 ) ro4 ]}
gm2 + ro1 k RP
1

(c)
Gm = gm5
Rout = [ro2 + (1 + gm2 ro2 ) (ro1 k ro5 )] k [ro3 + (1 + gm3 ro3 ) ro4 ]
Av = gm5 {[ro2 + (1 + gm2 ro2 ) (ro1 k ro5 )] k [ro3 + (1 + gm3 ro3 ) ro4 ]}
(d)
Gm = gm5
Rout = [ro2 + (1 + gm2 ro2 ) ro1 ] k [ro3 + (1 + gm3 ro3 ) (ro4 k ro5 )]
Av = gm5 {[ro2 + (1 + gm2 ro2 ) ro1 ] k [ro3 + (1 + gm3 ro3 ) (ro4 k ro5 )]}

9.36
2

1
R2
W
I1 = n Cox
(Eq. 9.85)
VDD VT H
2
L R1 + R2


I1
R2
R2
W
=
VDD VT H
n Cox
VDD
L
R1 + R2
R1 + R2
=

R2
gm
R1 + R2

I1
. Since VGS is
Intuitively, we know that gm is the derivative of I1 with respect to VGS , or gm = V
GS
VGS
is a
linearly dependent on VDD by the relationship established by the voltage divider (meaning V
DD
I1
I1
VGS
I1
VGS
constant), wed expect VDD to also be proportional to gm , since VDD = VDD VGS = VDD gm .

9.37
2
R2
(Eq. 9.85)
VDD VT H
R1 + R2


R2
W
= n Cox
VDD VT H
L R1 + R2

1
W
I1 = n Cox
2
L
I1
VT H

The sensitivity of I1 to VT H becomes a more serious issue at low supply voltages because as VDD
becomes smaller with respect to VT H , VT H has more control over the sensitivity. When VDD is large
enough, it dominates the last term of the expression, reducing the control of VT H over the sensitivity.

9.38 As long as VREF > 0, the circuit operates in negative feedback, so that V+ = V = 0 V.
VREF
IC1 = IS1 eV1 /VT =
R

1
VREF
V1 = VT ln
= VBE2
R1 IS1
If VREF > R1 IS1 , then we have VBE2 < 0, and IX = 0. If VREF < R1 IS1 , then we have:
IX = IS2 e

VT ln

VREF
R1 IS1

/VT

V
ln REF

R1 IS1
= IS2 e
R1 IS1
= IS2
VREF

Thus, if VREF > R1 IS1 (which will typically be true, since IS1 is typically very small), then we get no
output, i.e., IX = 0. When VREF < R1 IS1 , we get an inverse relationship between IX and VREF .

9.39 As long as VREF > 0, the circuit operates in negative feedback, so that V+ = V = 0 V.
VREF
IC1 = IS1 eV1 /VT =
R

1
VREF
V1 = VT ln
= VBE2
R1 IS1
If VREF < R1 IS1 , then we have VBE2 < 0, and IX = 0. If VREF > R1 IS1 , then we have:
V ln

VREF

R1 IS1
IX = IS2 e T
VREF
= IS2
R1 IS1
IS2 VREF
=
IS1 R1
IS2
=
IC1
IS1

/VT

Thus, if VREF < R1 IS1 , then we get no output, i.e., IX = 0. When VREF > R1 IS1 (which will typically
be true, since IS1 is typically very small), we get a current mirror relationship between Q1 and Q2
(ensured by the op-amp).
(with IX copying IC1 ), where the reference current for Q1 is VREF
R1

9.46 (a)
Icopy = 5IC,REF
IREF = IC,REF + IB,REF + IB1
IC,REF
Icopy
= IC,REF +
+

IC,REF
5IC,REF
= IC,REF +
+

5
1
= IC,REF 1 + +

Icopy 6 +
=
5

Icopy =
5IREF
6+

(b)
IC,REF
5
= IC,REF + IB,REF + IB1
IC,REF
Icopy
= IC,REF +
+

IC,REF
IC,REF
+
= IC,REF +

5


1
1
= IC,REF 1 + +

5


6 + 5
= 5Icopy
5


IREF
5
=
6 + 5
5

Icopy =
IREF

Icopy

(c)
3
IC,REF
2
5
I2 = IC,REF
2
IREF = IC,REF + IB,REF + IB1 + IB2
IC,REF
Icopy
I2
= IC,REF +
+
+

3IC,REF
5IC,REF
IC,REF
+
+
= IC,REF +

2
2


3
5
1
+
= IC,REF 1 + +

2
2


2
10 + 2
= Icopy
3
2


3
2
IREF
Icopy =
10 + 2 2
Icopy =

9.49
VGS,REF = VT H +

2IREF
n Cox W
L

VGS1 = VGS,REF I1 RP
s
2IREF
I1 RP
= VT H +
n Cox W
L
s
2IREF
IREF
RP

= VT H +
2
n Cox W
L
!2
s
W
IREF
1
2IREF
RP

I1 = n Cox
2
L
2
n Cox W
L
IREF
s2
IREF
IREF
RP =

2
n Cox W
L
s
s
IREF
2IREF
IREF
RP =

W
2
n Cox W

n Cox L
L
s


IREF
=
21
n Cox W
L

2 21
RP = q
IREF n Cox W
L
=

2IREF
n Cox W
L

Given this choice of RP , I1 does not change if the threshold voltages of the transistors change by the
same amount V . Looking at the expression for I1 in the derivation above, we can see that it has no
dependence on VT H (note that RP does not depend on VT H either).

9.54
IC1 = 1 mA
1 + n
IE1 RE =
IC1 RE = 0.5 V
n
RE == 0.5 V
RE = 495.05
Rout,a = ro1 + (1 + gm1 ro1 ) (r1 k RE )
Rout,b

= 85.49 k
= ro1 + (1 + gm1 ro1 ) (r1 k ro2 )
= 334.53 k

The output impedance of the circuit in Fig. 9.72(b) is significantly larger than the output impedance
of the circuit in Fig. 9.72(a) (by a factor of about 4).

9.56 (a)
Rout = ro1 + (1 + gm1 ro1 ) ro2 = 200 k
1
ro1 = ro2 =
ID
r
W
gm1 = gm2 = 2 n Cox ID
L


W
W
=
= 1.6
L 1
L 2
(b)
Vb2 = VGS2 = VT H +
= 2.9 V

W
L

2ID
n Cox

9.57 (a) Assume IC1 IC2 , since 1.

Av = gm1 [ro2 + (1 + gm2 ro2 ) (r2 k ro1 )]
I1
gm1 = gm2 =
VT
VA
ro1 = ro2 =
I1
VT
r1 = r2 =
I
" 1
#

VIT1 VIA1
VA
I1 VA
+ 1+
Av =
VT I1
VT VIT + VIA
1
1




1
VA
VT VA
=
VA + 1 +
VT
VT VT + VA
= 500

VA = 0.618 V
(b)
Vin = VBE1 = VT ln

I1
IS1

= 714 mV
(c)
Vb1 = VBE2 + VCE1
= VBE2 + 500 mV


I1
+ 500 mV
= VT ln
IS2
= 1.214 V

9.58 Assume all of the collector currents are the same, since 1.
P = IC VCC = 2 mW
IC = 0.8 mA

IC
Vin = VT ln
= 726 mV
IS

Vb1 = VBE2 + VCE1

IC
= VT ln
+ VBE1 VBC1
IS
= 1.252 V
Vb3 = VCC VT ln

IC
IS

= 1.774 V

Vb2 = VCC VEC4 VEB3

= VCC (VEB4 VCB4 ) VT ln

IC
IS

= 1.248 V
Av = gm1 {[ro2 + (1 + gm2 ro2 ) (r2 k ro1 )] k [ro3 + (1 + gm3 ro3 ) (r3 k ro4 )]}
= 4887

9.62
Rout = RC = 500
IC RC
= 20
Av = gm2 RC =
VT
IC = 1.04 mA
P = (IC + IREF ) VCC = 3 mW
IREF = 0.16 mA
AE1
IC =
IREF
AE,REF
AE1
= 6.5

AE,REF

AE,REF = AE
AE1 = 6.5AE

9.63
Icopy = nIC,REF
IREF = IC,REF + IB,REF + IB1
IC,REF
Icopy
= IC,REF +
+

IC,REF
nIC,REF
= IC,REF +
+

n
1
= IC,REF 1 + +

Icopy n + 1 +
=
n

nIREF
Icopy =
n+1+

Since nIREF is the nominal value of Icopy , the error term, n+1+
, must be between 0.99 and 1.01 so
that the actual value of Icopy is within 1 % of the nominal value. Since the upper constraint (that the
error term must be less than 1.01) results in a negative value of n (meaning that we can only get less
than the nominal current if we include the error term), we only care about the lower error bound.

0.99
n+1+
n 0.0101
IREF 50 mA
We can see that in order to decrease the error term, we must use a smaller value for n (in the ideal

). However, the smaller value of

case, we have n approaching zero and the error term approaching 1+
n we use, the larger value we must use for IREF , meaning the more power we must consume. Thus,
we have a direct trade-off between accuracy and power consumption.

9.64
IC,M =

AE,M
IC,REF 1
AE,REF 1

IREF 1 = IC,REF 1 + IB,REF 1 + IB,M

IC,REF 1
IC,M
= IC,REF 1 +
+
n
n
AE,M IC,REF 1
IC,REF 1
+
= IC,REF 1 +
n
AE,REF 1 n


1
AE,M
= IC,REF 1 1 +
+
n
AE,REF 1 n


AE,REF 1
AE,REF 1 n + AE,REF 1 + AE,M
=
IC,M
AE,M
AE,REF 1 n


AE,M
AE,REF 1 n
IREF
IC,M =
AE,REF 1 n + AE,REF 1 + AE,M AE,REF 1
Using a similar derivation to find IC2 , we have:


AE2
AE,REF 2 p
IC,M
IC1 = IC2 =
AE,REF 2 p + AE,REF 2 + AE2 AE,REF 2



AE2
AE,REF 2 p
AE,M
AE,REF 1 p

IREF
=
AE,REF 1 p + AE,REF 1 + AE,M
AE,REF 2 p + AE,REF 2 + AE2 AE,REF 1 AE,REF 2
We want the error term to be between 0.90 and 1.10 so that IC2 is within 10 % of its nominal value.
Since the error term cannot exceed 1 (since we only lose current through the base), we only have to
worry about the lower bound.



AE,REF 1 n
AE,REF 2 p
0.90
AE,REF 1 n + AE,REF 1 + AE,M
AE,REF 2 p + AE,REF 2 + AE2
Lets let the reference transistors QREF 1 and QREF 2 have unit size AE . Then we have:
!
!
n
p
> 0.90
A
p + 1 + AAE2
n + 1 + AE,M
E
E

We can pick any AE,M and AE2 such that this constraint is satisfied. One valid solution is AE,M = AE ,
AE2 = 3.466AE , and IREF = 0.2885 mA. This gives a nominal value for IC2 of 1 mA with an error
of 10 %. This solution is not unique (for example, another solution would be AE,M = AE2 = AE and
IREF = 1 mA, which gives a nominal current of 1 mA and an error of 5.73 %).

9.68
Av = gm1 ro3 = gm1

1
= 20
p ID1

1
k ro2
gm1
ro2
=
1 + gm1 ro2

Rin =

gm1

1
n ID1

1 + gm1 n 1ID1

= 50
= 19.5 mS

ID1 = 4.88 mA
s

W
ID1
gm1 = 2n Cox
L 1

W
= 390
L 1
We need to size the rest of the transistors to ensure they provide the correct bias current to the amplifier
and to ensure they are all in saturation. VG3 will be important in determining how we should bias
VG5 , since in order for M5 to be in saturation, we require VG3 > VG5 VT Hn , and VG3 is fixed by the
previously calculated value of ID1 .
!
s
2ID1

VG3 = VDD VSG3 = VDD |VT Hp | +
p Cox W
L 3
= 0.363 V

Lets let IREF = ID5 = 1 mA (which ensures we meet our power constraint, since P = (IREF + ID5 + ID1 ) VDD =
12.4 mW) and VGS,REF = VGS5 = 0.5 V (which ensures M5 operates in saturation). Then we have

W
1
2
(VGS,REF VT H )
IREF = n Cox
2
L REF


W
W
360
=
=
L REF
L 5
0.18
(W/L)3
ID3
=
(W/L)4
ID4

8.2
W
=
L 4
0.18
(W/L)2
ID2
=
(W/L)REF
IREF

W
1756
=
L 2
0.18

10.3 (a) Looking into the collector of Q1 , we see an infinite impedance (assuming IEE is an ideal source).
Thus, the gain from VCC to Vout is 1 .
(b) Looking into the drain of M1 , we see an impedance of ro1 + (1 + gm1 ro1 ) RS . Thus, the gain from
VCC to Vout is
ro1 + (1 + gm1 ro1 ) RS
RD + ro1 + (1 + gm1 ro1 ) RS
(c) Lets draw the small-signal model.
+
r1

gm1 v1

v1

ro1

vcc

vout

vout = v1


vcc vout
r1
vout = gm1 v1 +
ro1


vcc vout
= gm1 vout +
r1
ro1


r1
r1
= vcc
vout 1 + gm1 r1 +
ro1
ro1
vout
r1


=
vcc
1 + + r1
r
o1

ro1

r1
ro1 (1 + ) + r1

(d) Lets draw the small-signal model.

+
vgs1

gm1 vgs1

vout
RS

ro1

vcc

vout = vgs1


vcc vout
RS
vout = gm1 vgs1 +
ro1


vcc vout
RS
= gm1 vout +
ro1


RS
RS
vout 1 + gm1 RS +
= vcc
ro1
ro1
vout
RS


=
vcc
ro1 1 + gm1 RS + RS
ro1

RS
ro1 (1 + gm1 RS ) + RS

10.8

VX (t)
VY (t)
2I0 RC
1.8I0 RC

I0 RC
0.8I0 RC

/
0.2I0 RC

X and Y are not true differential signals, since their common-mode values differ.

10.9 (a)
VX = VCC I1 RC
VY = VCC (I2 + IT ) RC

VX (t)
VY (t)
VCC

VCC IT RC
VCC I0 RC

VCC (I0 + IT ) RC
VCC 2I0 RC

VCC (2I0 + IT ) RC
/

/
t

(b)
VX = VCC (I1 IT ) RC
VY = VCC (I2 + IT ) RC

VX (t)
VY (t)
VCC + IT RC

VCC (I0 IT ) RC
VCC IT RC
VCC (2I0 IT ) RC
VCC (I0 + IT ) RC

VCC (2I0 + IT ) RC
/

/
t

(c)


VX VY
VX = VCC I1 +
RC
RP




VY
RC
= VCC I1
RC
VX 1 +
RP
RP


VY
RC
VCC I1 R
P
VX =
RC
1+ R
P
VCC RP (I1 RP VY ) RC
R + RC

P
VY VX
RC
VY = VCC I2 +
RP




VX
RC
= VCC I2
RC
VY 1 +
RP
RP


VX
VCC I2 R
RC
P
VY =
RC
1+ R
P
=

=
VX =
=
VX

2
RC

(RP + RC )2
2

VX

2
(RP + RC ) RC
RP + RC

VCC RP (I2 RP VX ) RC
RP + RC


2 RP VX )RC
RC
VCC RP I1 RP VCC RP (I
RP +RC
RP + RC

VCC RP I1 RP RC +

VCC RP RC I2 RP R2C +VX R2C

RP +RC

RP + RC

= VCC RP I1 RP RC +

VCC RP I1 RP RC +

VCC RP RC I2 RP R2C
RP +RC

RP + RC
2
VCC RP RC I2 RP RC
RP + RC

2
VX RP2 + 2RP RC = VCC RP (RP + RC ) I1 RP RC (RP + RC ) + VCC RP RC I2 RP RC

2
VCC RP (RP + RC ) I1 RP RC (RP + RC ) + VCC RP RC I2 RP RC
2
RP + 2RP RC
VCC RP (2RC + RP ) RP RC [I1 (RP + RC ) + I2 RC ]
=
RP (2RC + RP )

VX =

Substituting I1 and I2 , we have:

VCC RP (2RC + RP ) RP RC [(I0 + I0 cos (t)) (RP + RC ) + (I0 I0 cos (t)) RC ]
RP (2RC + RP )
VCC RP (2RC + RP ) RP RC [I0 (2RC + RP ) + I0 cos (t) RP ]
=
RP (2RC + RP )
RC RP
= VCC I0 RC + I0 cos (t)
2RC + RP

VX =

By symmetry, we can write:

VY = VCC I0 RC I0 cos (t)

RC RP
2RC + RP

VX (t)
VY (t)
RP
VCC I0 RC + I0 2RRCC+R
P

VCC I0 RC

RP
VCC I0 RC I0 2RRCC+R
P

/
t

(d)
VX = VCC I1 RC


VY
RC
VY = VCC I2 +
RP


RC
VY 1 +
= VCC I2 RC
RP
VCC I2 RC
VY =
C
1+ R
RP
=

VCC RP I2 RC RP
RP + RC

VX (t)
VY (t)
VCC

VCC I0 RC
P
VCC RPR+R
C

VCC RP I0 RC RP
RP +RC

VCC 2I0 RC
VCC RP 2I0 RC RP
RP +RC

/
t

10.11 Note that since the circuit is symmetric and IEE is an ideal source, no matter what value of VCC we
have, the current through Q1 and Q2 must be IEE /2. That means if the supply voltage increases by
some amount V , VX and VY must also increase by the same amount to ensure the current remains
the same.
VX = V
VY = V
(VX VY ) = 0
We can say that this circuit rejects supply noise because changes in the supply voltage (i.e., supply
noise) do not show up as changes in the differential output voltage VX VY .

10.23 If the temperature increases from 27 C to 100 C, then VT will increase from 25.87 mV to 32.16 mV.
Will will cause the curves to stretch horizontally, since the differential input will have to be larger in
magnitude in order to drive the current to one side of the differential pair. This stretching is shown in
the following plots.

IC1 , T
IC1 , T
IC2 , T
IC2 , T

= 27 C
= 100 C
= 27 C
= 100 C

IEE

IEE
2

Vin1 Vin2

Vout1 , T
Vout1 , T
Vout2 , T
Vout2 , T

= 27 C
= 100 C
= 27 C
= 100 C

VCC

VCC IEE RC /2

VCC IEE RC

Vin1 Vin2

Vout1 Vout2 , T = 27 C
Vout1 Vout2 , T = 100 C
IEE RC

Vin1 Vin2

IEE RC

10.33 (a) Treating node P as a virtual ground, we can draw the small-signal model to find Gm .
iout
+
vin

gm v

ro

RE

vin v
v
+
r
RE
v = vin (iout + gm v ) ro

iout =

v (1 + gm ro ) = vin + iout ro
vin + iout ro
v =
1 + gm ro
vin + iout ro
vin + iout ro
vin
iout =

+
r (1 + gm ro ) RE
RE (1 + gm ro )




ro
1
1
ro
1
= vin
iout 1 +

r (1 + gm ro ) RE (1 + gm ro )
RE
r (1 + gm ro ) RE (1 + gm ro )




r (1 + gm ro ) RE r
r RE (1 + gm ro ) + ro (r + RE )
= vin
iout
r RE (1 + gm ro )
r RE (1 + gm ro )
iout
r (1 + gm ro ) RE r
Gm =
=
vin
r RE (1 + gm ro ) + ro (r + RE )
Rout = RC k [ro + (1 + gm ro ) (r k RE )]

Av =

r (1 + gm ro ) RE r
{RC k [ro + (1 + gm ro ) (r k RE )]}
r RE (1 + gm ro ) + ro (r + RE )

(b) The result is identical to the result from part (a), except R1 appears in parallel with ro .
Av =

r (1 + gm (ro k R1 )) RE r
{RC k [(ro k R1 ) + (1 + gm (ro k R1 )) (r k RE )]}
r RE (1 + gm (ro k R1 )) + (ro k R1 ) (r + RE )

10.36
VDD

ISS RD
> VCM VT H,n
2
VDD > VCM VT H,n +
VDD > 1 V

ISS RD
2

10.38 Let JD be the current density of a MOSFET, as defined in the problem statement.
ID
11
=
n Cox (VGS VT H )2
W
2
L
s
2ID
=
W
L n Cox
s
2JD
=
1

L n Cox

JD =
(VGS VT H )equil

The equilibrium overdrive voltage increases as the square root of the current density.

10.39 Let id1 , id2 , and vP denote the changes in their respective values given a small differential input of vin
(+vin to Vin1 and vin to Vin2 ).
id1 = gm (vin vP )
id2 = gm (vin vP )
vP = (id1 + id2 ) RSS
= 2gm vP RSS
vP = 0
Note that we can justify the last step by noting that if vP 6= 0, then wed have 2gm RSS = 1, which
makes no sense, since all the values on the left side must be positive. Thus, since the voltage at P does
not change with a small differential input, node P acts as a virtual ground.

10.41
P = ISS VDD = 2 mW
ISS = 1 mA
VCM,out = VDD

ISS RD
= 1.6 V
2

RD = 800
|Av | = gm RD
s
W
= 2
n Cox ID RD
L 1

W
L

=5

W
=
= 390.625
L 2

Lets formulate the trade-off between VDD and W/L, lets assume were trying to meet an output
common-mode level of VCM,out . Then we have:
ISS =

P
VDD

ISS RD
2
P RD
= VDD
2V

DD
VDD VCM,out
RD = 2VDD
P

VCM,out = VDD

|Av | = gm RD
r
W
n Cox ISS RD
=
L
r



W
VDD VCM,out
P
=
2VDD
n Cox
L
VDD
P
To meet a certain gain, W/L and VDD must be adjusted according to the above equation. We can see
that if we decrease VDD , wed have to increase W/L in order to meet the same gain.

10.55 Lets draw the half circuit.

vout
Q3

vin

Gm = gm1 RP
2

= gm1

RP
2

Q1

k ro1 k r3

k ro1 k r3 +
RP
2 k
gm3 R2P

gm3

RP /2

1
gm3

ro1 k r3

k ro1 k r3


RP
Rout = ro3 + (1 + gm3 ro3 ) r3 k
k ro1
2



RP
gm3 2 k ro1 k r3
RP

Av = gm1
k
r
r
+
(1
+
g
r
)
r
k
o1
o3
m3 o3
3
2
1 + gm3 R2P k ro1 k r3
1+

10.60 Assume IC =

IEE
2

for all of the transistors (since 1).

Av = gm1 {[ro3 + (1 + gm3 ro3 ) (r3 k ro1 )] k [ro5 + (1 + gm5 ro5 ) (r5 k ro7 )]}
h


ih


i
VA,n
VA,p
n VT VA,n
p VT VA,p
V
+
1
+
V
+
1
+
A,n
A,p
VT
n VT +VA,n
VT
p VT +VA,p
1
h


i h


i
=
V
V

V
V
p VT VA,p
A,n
A,p
n
T
A,n
VT VA,n + 1 +
+ VA,p + 1 +
VT

= 800

VA,n = 2.16 V
VA,p = 1.08 V

n VT +VA,n

VT

p VT +VA,p

10.61




1
Av = gm1 [ro3 + (1 + gm3 ro3 ) (r3 k ro1 )] k ro5 + (1 + gm5 ro5 ) r5 k
k r7 k ro7
gm7
This topology is not a telescopic cascode. The use of NPN transistors for Q7 and Q8 drops the output
resistance of the structure from that of the typical telescopic cascode.

10.73 (a)
VN = VDD VSG3
s
= VDD

I
SS
W
L 3 p Cox

|VT Hp |

(b) By symmetry, we know that ID for M3 and M4 is the same, and we also know that their VSG
values are the same. Thus, their VSD values must also be equal, meaning VY = VN .
(c) If VDD changes by V , then both VY and VN will change by V .

10.83
P = VCC IEE = 1 mW
IEE = 0.4 mA
Av = gm1 (ro1 k ro3 k R1 )
= 100
R1 = R2 = 59.1 k

10.92
P = VCC IEE = 3 mW
IEE = 1.2 mA
Av = gm,n (ro,n k ro,p )
= 200
VA,n = 15.6 V
VA,p = 7.8 V

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