System IP - CoreLink and CoreSight

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ARM CoreLink™ system IP unleashes high performance ARM Cortex™ and Mali™ processors with lower latency, lower power interconnect, multi-channel memory controllers and enables coherent, virtualized SoC design to easily support multiple software worlds.

The CoreLink 400 series introduces new coherent interconnect, higher bus utilization dynamic memory controllers, system MMU and interrupt controllers for virtualization, and enhanced AMBA^® design tools for easy, optimal SoC design, based on AMBA 4 protocols.

CoreSight™ debug and trace IP provides world-leading visibility in to the workings of the SoC, enabling software optimization and faster time to market with more reliable, higher performance products.

Why CoreLink & CoreSight?

How to Choose

Customer Successes

Glossary of Product Codes

Resources

Maximise system performance and power efficiency

Low Risk	High Performance
Using the de-facto industry standard AMBA protocols, the CoreLink interconnect and peripheral IP is used by over 100 licensees in 1000’s of designs, giving you confidence that your design will be right first time	Whether it is lowest latency or highest bandwidth demanded by the processors, ARM CoreLink IP delivers outstanding efficiency to achieve the performance required with the lowest power and smallest area.
Low Power Leadership	Faster to Market
The ARM architecture is a leader in low power. Minimizing data transfers using on-chip cache and maximizing the efficiency of off-chip memory transfers ensures the lowest system power profile at any performance point.	Industry standard IP components and design tools for simpler configuration, integration & verification greatly reduce complexity and shorten design cycle times - enabling faster time to market.
Visibility	Experience & Expertise
CoreSight Design Kits provide the most complete on-chip debug and real-time trace solution for the entire system-on-chip (SoC), making ARM processor-based SoCs the easiest to debug and optimize.	ARM is uniquely placed to deliver system IP solutions from processors to pins. With design teams in processor design, interconnect, and memory controllers and PHYs, ARM has the skills and global support teams to deliver world-class on-chip digital highways.

CoreLink & CoreSight

CoreLink and CoreSight IP products

Explore further by clicking on the area of interest in the SoC block diagram below.

CoreLink Design Tools

Fujitsu Semiconductor will offer platforms featuring the latest ARM technology including the Cortex™-A15 processor, Mali™ graphics and CoreLink™ system IP, in order to help accelerate its customers’ product development. 28th February 2011

"The flexibility of the CoreSight technology enables us to provide a cost-effective high-performance debug solution with a number of advanced features including multi-source tracing,” said John Lenell, Engineering Director, Broadcom Corporation. “With CoreSight technology we can offer a comprehensive debug solution supported by industry standard tools enabling our customers to reduce product development time."

"All required features for SoC Architecture were available" System Architect, Networking Silicon Partner using CoreLink Network Interconnect NIC-301.

The CoreLink Memory Controllers have been licensed by over 70 ARM Partners including: Mtekvision, ZTE and

PMC Sierra

Glossary of System IP Product Codes

ARM have recently added mnemonic names, e.g. "DMC-342" for the LPDDR2 AXI Dynamic Memory Controller, to the System IP to help newcomers find their way around the CoreLink and CoreSight system IP product portfolio, without having to remember what each 3-digit "PLxxx" number stands for.

The PLxxx part numbers persist as unique identifiers for deliverables in licenses, in the ARM internal SAP database, in current technical documentation and as tags and identifiers in the products themselves. For your convenience, the look up table below lists the new mnemonic product code, SAP part number, full product name and AMBA interface protocols supported.

New Product Code	'Old' or SAP Part Number	Product Description	AMBA Protocol
DMC-400	-	LPDDR2/DDR3 Dynamic Memory Controller	AMBA 4
CCI-400	-	Cache Coherent Interconnect	AMBA 4
MMU-400	-	System Memory Management Unit	AMBA 4
NIC-400	PL401	Network Interconnect	AXI4, AHB, APB
GIC-400	-	Generic Interrupt Controller v2	AXI4
QoS-400	-	Quality of Service option for NIC-400	AXI4, AHB, APB
QVN-400	-	QoS Virtual Networks option for NIC-400	AXI4, AHB, APB
TLX-400	-	Thin Links option for NIC-400	AXI4
NIC-301	PL301	Network Interconnect	AXI, AHB, APB
QoS-301	PL501	Interconnect Quality of Service	AXI
ADK	BP010	AMBA Design Kit	AHB, APB
DMC-340	PL340	DDR/LPDDR/SDR Dynamic Memory Controller	AXI
DMC-341	PL341	DDR2 Dynamic Memory Controller	AXI
DMC-342	PL342	LPDDR2 Dynamic Memory Controller	AXI
SMC-351	PL351	NAND Flash Static Memory Controller	AXI
SMC-352	PL352	NOR Flash Static Memory Controller	AXI
SMC-353	PL353	NAND/NOR/SRAM Static Memory Controller	AXI
SMC-354	PL354	NOR/SRAM Static Memory Controller	AXI
ADR-301	FD001	AMBA Designer (tool)	AXI, AHB, APB
VPE-301	FD100	Verification & Performance Exploration (tool)	AXI
L2C-310	PL310	Level 2 Cache Controller	AXI
L2C-210	AC130	L210 Level 2 Cache Controller	AHB
DMA-330	PL330	AXI DMA Controller	AXI
DMA-230	PL230	Micro DMA Controller	AHB
GIC-390	PL390	Generic Interrupt Controller	AXI
CDK-A9	TM096	CoreSight Design Kit for Cortex-A9	ATB, APB
CDK-A8	TM094	CoreSight Design Kit for Cortex-A8	ATB, APB
PTM-A9	TM950	Program Trace Macrocell for Cortex-A9	ATB, APB
CDK-A5	TM097	CoreSight Design Kit for Cortex-A5	ATB, APB
CDK-R4	TM095	CoreSight Design Kit for Cortex-R4	ATB, APB
ETM-R4	TM930	Embedded Trace Macrocell for Cortex-R4	ATB, APB
CDK-11	TM090	CoreSight Design Kit for ARM11	ATB, APB
CDK-9	TM085	CoreSight Design Kit for ARM9E	ATB, APB

Other System IP products remain unchanged and will continue to use their current names.

CoreLink and CoreSight Whitepapers

Download	Title	Description
(930 KB)	Introduction to AMBA 4 ACE	An introduction to Cache Coherency using the AMBA 4 ACE protocol.
(1,383 KB)	Modeling and Verifying Cache-Coherent Protocols, VIP, and Designs	How Jasper Design Automation's ActiveModel™ technology can be used to model and verify ARM AMBA 4 ACE protocol deliverables.
(3,944 KB)	QoS for High-Performance and Power-Efficient HD Multimedia	How Quality of Service (QoS) can be used to increase efficiency of the interconnect and memory sub-system for use by CPU and GPU processors.
(572 KB)	*Debug and Trace for Multicore SoCs*	How to build an efficient and effective debug and trace system for multi-core SoCs.
(1,072 KB)	*Traffic Management for Optimizing Media-Intensive SoCs*	How Verification & Performance Exploration (VPE) and Quality-of-Service (QoS) mechanisms can optimize the system performance of SoCs with multiple CPU & graphics processors.

Presentations on CoreLink and CoreSight

Download	Title	Description
(2,010 KB)	*The Challenges of System Design*	How to reduce system latency and increase memory bandwidth utilization; how to provide system visibility for software optimization.
(2,984 KB)	*Effective System Design with ARM System IP*	An overview of how System IP and tools can improve your SoC design.

AMBA Design Centers

A list of ARM Approved Design Centers has been carefully chosen for their technical capabilities, ARM expertise, regional coverage, independence and quality control processes.

Documentation