CoreSight On-chip Debug & Trace IP

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The CoreSight™ debug and trace solution encompasses three main technology groups:

Debug

ARM debug interface is described by the ARM Debug Interface Architecture (ADI), this architecture is available publicly and implemented with any processor implementing the ARM architecture. The CoreSight Debug Access Port (DAP) provides an optimized implementation of the ADI architecture for ARM based SoC.

The CoreSight SoC components

The CoreSight SoC components provide all the infrastructure required at the SoC level for building a complete debug and trace infrastructure for single and multi-processing units, such as Cortex™ cores. ARM offers a public CoreSight architecture specification describing standard interfaces and programmer views; this enables ARM Partners to integrate their debug and trace solution within the ARM CoreSight solution.  

CoreSight Trace Macrocells

The CoreSight technology offers an exhaustive range of trace macrocells, this includes CoreSight Embedded Trace Macrocells (ETM) & Program Trace Macrocells (PTM) for ARM cores, instrumentation trace macrocells and bus trace. Partners can integrate their own trace macrocells to the CoreSight infrastructure by complying with the ARM CoreSight architecture.

The CoreSight technology is available for any ARM processor-based SoC (CoreSight for Cortex-A, CoreSight for Cortex-R, CoreSight for Cortex-M, CoreSight for ARM11/9) and has been designed to scale to all profiles.

CoreSight in Silicon

CoreSight on-chip debug and trace technology is today used by hundreds of thousands of software and hardware developers across all ARM processor profiles (Application, Real-time, Microcontroller) to develop, optimize, maintain ARM based SoC across many markets.

For reference, some platforms implementing CoreSight (public domain information)

Many more platforms support the CoreSight architecture, if you want your platform listed here please contact ARM.

CoreSight is the debug & trace architecture for all markets

All major silicon suppliers across all markets license CoreSight technology.
Some numbers:

• Other 130 ARM partners have licensed CPU trace macrocell (ETM technology)
• Other 70 ARM partners have licensed the CoreSight Design Kit technology introduced back in 2004.

ARM debug & trace technology is licensed across all markets.

Higher quality product to market quicker

Company	Quote
	"The flexibility of the CoreSight technology enables us to provide a cost-effective high-performance debug solution with a number of advanced features including multi-source tracing,” said John Lenell, engineering director, Broadcom Corporation. “With CoreSight technology we can offer a comprehensive debug solution supported by industry standard tools enabling our customers to reduce product development time."
	“The CoreSight technology allows us to provide our customers with comprehensive debug and trace capabilities for both ARM and our own DSP cores within complex multi-core SoCs,” said Marc Corthout, general manager, Chief Technology Office Design IP Group, Philips Semiconductors. “The visibility provided by CoreSight helps us and our customers to get higher quality products to market quicker.”

Click on the logos below for more information:

Examples of how the CoreSight technology is used

Market leading tools to provide key tasks such use CoreSight on-chip resources:

Debug of symmetric multi-processing and asymmetric multicore systems

The CoreSight Debug Access Port (DAP) and Embedded Cross Trigger (ECT) enable tools, such as the ARM RealView Debugger to provide a correlated view with synchronized control of multiple processors in a single instance of the debugger, even when processors may be in different power and clock domains.

Powerful interactive debugging with real-time visibility

Real-time updating of views in to the complete system state including memory contents, processor and peripheral registers. State-of-the-art debug features such as Green Hills' TimeMachine and Lauterbach's Context Tracking System allow stepping forward and back through trace data collected in real-time from actual applications running on final products.

Performance optimization

Optimization using actual best/worst/average execution times at the instruction, block, function and task levels. Excellent new profiling tools such as the ARM Profiler or Lauterbach's Cache Analyzer allow the developer to get 20% to 500% improvements in code performance through knowing where the program is spending its time and where and why performance bottlenecks exist.

Line and path code coverage of assembler and C/C++

Quality code coverage metrics ensure the highest product reliability through comprehensive and targeted software testing with tools such as Code Coverage Analysis and Call Graph Exploration in the ARM Profiler.

High-level system views with OS and RTOS context

Using contextual data in the ETM trace or code instrumentation via the Instrumentation Trace Macrocell (ITM), high level software context and analysis of asynchronous real-time events such as interrupts and exceptions are provided with the RTOS/OS awareness and event viewer features of many debuggers.

Real-time data monitoring, common to MCU and automotive applications

Available in many low cost MCU tools, such the ARM Keil Microcontroller Development Kit.

New tool providers

If you would like your CoreSight tools support listed here, please contact ARM

Learn how to use CoreSight STM with Linux LTTng - Whitepaper

Learn how software developers can use CoreSight System Trace with open source instrumentation framework such Linux LTTng

Better trace for better software with CoreSight STM  (726KB)

On-chip system level visibility with CoreSight - Webinar

Listen to the CoreSight on-demand webinar and find out:

• Which on-chip visibility shall be implemented on your next generation SoC
• How to use CoreSight enabled SoC such OMAP35x to accelerate and de-risk your product development
  

Download the webinar presentation  

CoreSight Whitepaper

How to build an efficient and effective debug and trace system for multi-core SoCs -  (572 KB)

Low Pin-count Debug Interfaces - Single Wire Debug Whitepaper

Low Pin-count Debug Interfaces for Multi-device Systems -  (160KB)

CoreSight Flyer

 CoreSight, the industry name for on-chip debug & trace -  (314 KB)

Debug & Trace panel organised by ARM at IP-ESC09

ARM, Nokia, Texas Instruments and Lauterbach discussed at IP-ESC 09 how scalable on-chip system visibility can be delivered cost effectively.

Access to the on-demand webinar to learn more about major mobile OEM requirements such Nokia and how debug & trace IP can address these.