Core area, frequency range and power consumption are dependent on process, libraries and optimizations. The numbers quoted above are illustrative of synthesized cores using general purpose TSMC process technologies and ARM Artisan standard cell libraries and RAMs. The speed optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve the target frequency performance. The area optimized implementations refer to the library choices and synthesis flow decisions and tradeoffs made in order to achieve a target area density. The cache sizes are specified as InstructionCache/DataCache. The area w/o cache numbers quoted exclude RAM area, but include all logic including memory management, cache control and debug. The area with cache numbers quoted includes the core, the specified instruction and data caches and all necessary RAMs. * Worst case conditions – 0.18µm process - 1.62V, 125C, slow silicon ; 0.13µm process - 1.08V, 125C, slow silicon ; 90nm process - 0.9V, 125C, slow silicon
† Typical case conditions– 0.18µm process–1.8V, 25C, typical silicon ; 0.13µm process - 1.2V, 25C, typical silicon ; 90nm process - 1V, 25C, typical silicon | 
