 IBM Reveals Breakthrough eDRAM Memory TechnologyIn papers presented at the International Solid State Circuits Conference, IBM revealed a first-of-its-kind, on-chip memory technology that features the fastest access times ever recorded in eDRAM (Embedded ... | |
 Renesas, Matsushita Develop Technique for Stablizing Operation of 45nm On-Chip SRAMFeb 13, 2007 | pda version
Renesas Technology and Matsushita Electric Industrial today announced the development of a technique that achieves stable operation with 45nm process generation bulk CMOS for SRAM (Static Random Access Memory) ... | |
Sony Cutting Semiconductor InvestmentFeb 13, 2007 | pda version
(AP) -- Sony Corp. plans to cut capital expenditures at its semiconductor operations by a "large amount," a company executive said Tuesday, weeks after the electronics giant reported a drop in profits for the latest quarter. | |
 Intel Producing First Processor Prototypes With New, Tiny 45 Nanometer TransistorsIn one of the biggest advancements in fundamental transistor design, Intel Corporation today revealed that it is using two dramatically new materials to build the insulating walls and switching gates of its ... | |
AMD and IBM Detail Early Results Using Immersion and Ultra Low-K in 45nm ChipsAt the International Electron Device Meeting today, IBM and AMD presented papers describing the use of immersion lithography, ultra-low-K interconnect dielectrics, and multiple enhanced transistor strain techniques for application ... | |
IMEC demonstrates viability of laser anneal for the 32nm nodeAt today�s IEEE International Electron Devices Meeting, IMEC reports that laser anneal is a promising option for further transistor scaling to the 32nm node. By device demonstration, IMEC shows that laser anneal allows to ... | |
ASM, IMEC Demonstrate Tree Generations of Aurora Low-K MaterialsASM International and IMEC announce that they have demonstrated three generations of ASM�s Aurora� low-k and SiC dielectric barrier materials for IMEC�s 300mm pilot line. | |
UMC Produces Working 45-nanometer ICsUMC, a leading global semiconductor foundry, today announced that it has successfully produced functional 45-nanometer SRAM chips that feature an impressive bit cell size of less than 0.25um2. The ICs, produced using UMC's ... | |
IMEC demonstrates feasibility of double patterning immersion litho for 32nm nodeIMEC showed in collaboration with ASML the potential of double patterning 193nm immersion lithography at 1.2NA for 32nm node Flash and logic. | |
IBM, Chartered, Infineon And Samsung Announce Process And Design Readiness For Silicon Circuits On 45nm Low-Power TechnoIBM, Chartered Semiconductor Manufacturing, Infineon Technologies, and Samsung Electronics Co., Ltd. today announced first silicon-functional circuits and the availability of design kits based on their collaboration for 45nm ... | |
 Intel Researchers Improve Tri-Gate TransistorIntel Corporation researchers today disclosed they have developed new technology designed to enable next era in energy-efficient performance. Intel's research and development involving new types of transistors ... | |
Infineon Successfully Produced First 65nm Samples in Multiple FabsInfineon Technologies AG has produced first sample chips in its advanced 65nm low-power and high-performance CMOS platform technology. Infineon leveraged the results of the industry leading 65nm/45nm alliance composed of ... | |
 Intel reaches 45 nanometer chip milestoneIntel said Wednesday it had produced the semiconductor industry's first chip using milestone 45-nanometer process technology. | |
 Applied Materials, IMEC Team to Develop Innovative 32nm, 22nm InterconnectsApplied Materials and IMEC, Europe's leading independent nanoelectronics and nanotechnology research center, announced today a significant joint effort to develop 32nm and 22nm-node copper/low k interconnect ... | |
IMEC reports CMOS integration of Hf-based dielectrics with Ni FUSI gatesDec 07, 2005 | pda version
At today�s IEEE International Electron Devices Meeting, IMEC announces a simple CMOS integration scheme of a NiSi gate for NMOS and a Ni2Si gate for PMOS on HfSiON with simultaneous 2-step silicidation. The potential of this ... | |
